1
Rev. 4158I–AERO–07/07
Features
Operating Voltage: 3.3V
Access Time: 40 ns
Very Low Power Consumption
Active: 160 mW (Max)
Standby: 70 µW (Typ)
Wide Temperature Range: -55°C to +125°C
MFP 32 leads 400 Mils Width Package
TTL Compatible Inputs and Outputs
Asynchronous
Designed on 0.35µm Process
No Single Event Latch-up below a LET threshold of 80 MeV/mg/cm
2
Tested up to a Total Dose of 200 Krad (Si) according to MIL STD 883 Method 1019
Quality grades: QML Q or V with SMD 5962-02501
Description
The M65609E is a very low power CMOS static RAM organized as 131,072 x 8 bits.
Utilizing an array of six transistors (6T) memory cells, the M65609E combines an
extremely low standby supply current with a fast access time at 40 ns. The high stabil-
ity of the 6T cell provides excellent protection against soft errors due to noise.
The M65609E is processed according to the methods of the latest revision of the MIL
PRF 38535 and ESCC 9000.
It is produced on the same process as the MH1RT sea of gates series.
Rad Hard
128K x 8
3.3-volt
Very Low Power
CMOS SRAM
M65609E
2
M65609E
4158I–AERO–07/07
Block Diagram
Pin Configuration
32 pins Flatpack 400 MILS
Pin Description
Name Description
A0 - A16 Address Inputs
I/O1 - I/O8 Data Input/Output
CS
1
Chip Select 1
CS
2
Chip Select 2
WE Write Enable
OE Output Enable
V
CC
Power
GND Ground
3
M65609E
4158I–AERO–07/07
Table 1. Truth Table
Note: L = low, H = high, X = H or L, Z = high impedance.
CS
1
CS
2
WE OE
Inputs/
Outputs Mode
H X X X Z Deselect/
Power-down
X L X X Z Deselect/
Power-down
L H H L Data Out Read
L H L X Data In Write
L H H H Z Output
Disable
4
M65609E
4158I–AERO–07/07
Electrical Characteristics
Absolute Maximum Ratings
Military Operating Range
Recommended DC Operating Conditions
Capacitance
Note: 1. Guaranteed but not tested.
Supply Voltage to GND Potential............................ -0.5V + 5V
DC Input Voltage............................ GND - 0.3V to
V
CC
+ 0.3V
DC Output Voltage High Z State .... GND - 0.3V to
V
CC
+ 0.3V
Storage Temperature .................................... -65°C to + 150°C
Output Current Into Outputs (Low) ............................... 20 mA
Electro Statics Discharge Voltage................................. > 500V
(MIL STD 883D Method 3015.3)
*NOTE:
Stresses greater than those listed under Absolute Max-
imum Ratings may cause permanent damage to the
device. This is a stress rating only and functional oper-
ation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
Operating Voltage Operating Temperature
3.3V + 0.3V -55
°
C to + 125
°
C
Parameter Description Min Typ Max Unit
V
CC
Supply voltage 3 3.3 3.6 V
Gnd Ground 0.0 0.0 0.0 V
V
IL
Input low voltage GND - 0.3 0.0 0.8 V
V
IH
Input high voltage 2.2
V
CC
+ 0.3 V
Parameter Description Min Typ Max Unit
C
IN(1)
Input low voltage 8 pF
C
OUT(1)
Output high voltage 8 pF
5
M65609E
4158I–AERO–07/07
DC Parameters
DC Test Conditions
Consumption
Parameter Description Minimum Typical Maximum Unit
IIX
(1)
1. Gnd < Vin <
V
CC
, Gnd < Vout <
V
CC
Output Disabled.
Input leakage
current -1 1 µA
IOZ
(1)
Output leakage
current -1 1 µA
VOL
(2)
2.
V
CC
min. IOL = 4 mA.
Output low voltage - 0.4 V
VOH
(3)
3.
V
CC
min. IOH = -2 mA.
Output high voltage 2.4 V
Symbol Description 65609E-40 Unit Value
ICCSB
(1)
Standby supply current 1.5 mA max
ICCSB
1 (2)
Standby supply current 1 mA max
ICCOP
(3)
Dynamic operating
current 45 mA max
1. CS
1
> VIH or CS
2
< VIL and CS
1
< VIL.
2. CS
1
>
V
CC
- 0.3V or, CS
2
< Gnd + 0.3V and CS
1
< 0.2V
3. F = 1/T
AVAV
, I
OUT
= 0 mA, W = OE = VIH, Vin = Gnd or
V
CC
,
V
CC
max.
6
M65609E
4158I–AERO–07/07
Write Cycle
Note: 1. Parameters guaranteed, not tested, with 5 pF output loading (see Section “AC Test Conditions” Figure 2).
Read Cycle
Note: 1. Parameters guaranteed, not tested, with 5 pF output loading (seeSection “AC Test Conditions” Figure 2).
Symbol Parameter 65609E-40 Unit Value
t
AVAW
Write cycle time 35 ns min
t
AVWL
Address set-up time 0 ns min
t
AVWH
Address valid to end of write 28 ns min
t
DVWH
Data set-up time 18 ns min
t
E1LWH
CS
1
low to write end 28 ns min
t
E2HWH
CS
2
high to write end 28 ns min
t
WLQZ
Write low to high Z
(1)
15 ns max
t
WLWH
Write pulse width 28 ns min
t
WHAX
Address hold from to end of
write 3 ns min
t
WHDX
Data hold time 0 ns min
t
WHQX
Write high to low Z
(1)
0 ns min
Symbol Parameter 65609E-40 Unit Value
t
AVAV
Read cycle time 40 ns min
t
AVQV
Address access time 40 ns max
t
AVQX
Address valid to low Z 3 ns min
t
E1LQV
Chip-select
1
access
time 40 ns max
t
E1LQX
CS
1
low to low Z
(1)
3 ns min
t
E1HQZ
CS
1
high to high Z
(1)
15 ns max
t
E2HQV
Chip-select
2
access
time 40 ns max
t
E2HQX
CS
2
high to low Z
(1)
3 ns min
t
E2LQZ
CS
2
low to high Z
(1)
15 ns max
t
GLQV
Output Enable access
time 12 ns max
t
GLQX
OE low to low Z
(1)
0 ns min
t
GHQZ
OE high to high Z
(1)
10 ns max
7
M65609E
4158I–AERO–07/07
AC Parameters
AC Test Conditions
AC Test Loads Waveforms
Input Pulse Level:......................................................... GND to 3.0V
Input Rise/Fall Time: .................................................... 5 ns
Input Timing Reference Level: ..................................... 1.5V
Output loading IOL/IOH (see figure 1 and 2)................ +30 pF
Figure 1 Figure 2 Figure 3
R1 2552
R1 2552
2824
2824
1340
3.3V 3.3V
V
8
M65609E
4158I–AERO–07/07
Data Retention Mode
Atmel CMOS RAM’s are designed with battery backup in mind. Data retention voltage
and supply current are guaranteed over temperature. The following rules ensure data
retention:
1. During data retention CS1 must be held high within V
CC
to V
CC
- 0.2V or chip
select CS2 must be held down within GND to GND +0.2V.
2. Output Enable (OE) should be held high to keep the RAM outputs high imped-
ance, minimizing power dissipation.
3. During power-up and power-down transitions CS1 and OE must be kept
between V
CC
+ 0.3V and 70% of V
CC
, or with BS between GND and GND -0.3V.
4. The RAM can begin operation > t
R
ns after V
CC
reaches the minimum operation
voltages (3V).
Figure 1. Data Retention Timing
Data Retention Characteristics
Notes: 1. TAVAV = Read Cycle Time
2. CS1 =
V
CC
or CS2 = CS1 = GND, V
IN
= GND/
V
CC
.
Parameter Description Min Typical T
A
= 25°C Max Unit
V
CC
DR
V
CC
for data
retention 2.0 V
T
CDR
Chip deselect to
data retention time 0.0 ns
t
R
Operation recovery
time t
AVAV(1)
ns
I
CCDR1(2)
Data retention
current at 2.0V 0.010 1.0 mA
9
M65609E
4158I–AERO–07/07
Write Cycle 1. WE Controlled.
OE High During Write
Write Cycle 2. WE Controlled.
OE Low
10
M65609E
4158I–AERO–07/07
Write Cycle 3. CS1 or CS2
Controlled
(1)
Note: 1. The internal write time of the memory is defined by the overlap of CS1 LOW and CS2 HIGH and W LOW. Both signals must
be activated to initiate a write and either signal can terminate a write by going in activated. The data input setup and hold
timing should be referenced to the actived edge of the signal that terminates the write. Data out is high impedance if OE =
V
IH
.
11
M65609E
4158I–AERO–07/07
Read Cycle nb 1
Read Cycle nb 2
Read Cycle nb 3
12
M65609E
4158I–AERO–07/07
Ordering Information
Note: 1. Contact Atmel for availability.
Part Number Temperature Range Speed Package Flow
MMDJ-65609EV-40-E 25°C 40 ns FP32.4 Engineering Samples
5962-0250101QXC -55 to +125°C 40 ns FP32.4 QML Q
5962-0250101VXC -55 to +125°C 40 ns FP32.4 QML V
5962R0250101VXC -55 to +125°C 40ns FP32.4 QML V RHA
SMDJ-65609EV-40SCC -55 to +125°C 40 ns FP32.4 ESCC
MM0 -65609EV-40-E
(1)
25°C 40 ns Die Engineering Samples
MM0 -65609EV-40SV
(1)
-55 to +125°C 40 ns Die QML V
13
M65609E
4158I–AERO–07/07
Package Drawing
32-pin Flat Pack (400 Mils)
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4158H–AERO–05/07 /xM
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