AR0331 AR0331 1/3Inch 3.1 Mp/Full HD Digital Image Sensor General Description The ON Semiconductor AR0331 is a 1/3-inch CMOS digital image sensor with an active-pixel array of 2048 (H) x 1536 (V). It captures images in either linear or high dynamic range modes, with a rolling-shutter readout. It includes sophisticated camera functions such as in-pixel binning, windowing and both video and single frame modes. It is designed for both low light and high dynamic range scene performance. It is programmable through a simple two-wire serial interface. The AR0331 produces extraordinarily clear, sharp digital pictures, and its ability to capture both continuous video and single frames makes it the perfect choice for a wide range of applications, including surveillance and HD video. The ON Semiconductor AR0331 can be operated in its default mode or programmed for frame size, exposure, gain, and other parameters. The default mode output is a 1080p-resolution image at 60 frames per second (fps). In linear mode, it outputs 12-bit or 10-bit A-Law compressed raw data, using either the parallel or serial (HiSPi) output ports. In high dynamic range mode, it outputs 12-bit compressed data using parallel output. In HiSPi mode, 12- or 14-bit compressed, or 16-bit linearized data may be output. The device may be operated in video (master) mode or in single frame trigger mode. FRAME_VALID and LINE_VALID signals are output on dedicated pins, along with a synchronized pixel clock in parallel mode. The AR0331 includes additional features to allow applicationspecific tuning: windowing and offset, auto black level correction, and on-board temperature sensor. Optional register information and histogram statistic information can be embedded in the first and last 2 lines of the image frame. The sensor is designed to operate in a wide temperature range (-30C to +85C). Features * * * * * * * * * * * * * * * Superior Low-light Performance Latest 2.2 m Pixel with ON Semiconductor A-PixTM Technology Full HD Support at 1080 P 60 fps for Superior Video Performance Linear or High Dynamic Range Capture 3.1 M (4:3) and 1080 P Full HD (16:9) Images Optional Adaptive Local Tone Mapping (ALTM) Interleaved T1/T2 Output Support for External Mechanical Shutter Support for External LED or Xenon Flash Slow-motion Video (VGA 120 fps) On-chip Phase-locked Loop (PLL) Oscillator Integrated Position-based Color and Lens Shading Correction Slave Mode for Precise Frame-rate Control Stereo/3D Camera Support Statistics Engine (c) Semiconductor Components Industries, LLC, 2011 March, 2017 - Rev. 14 1 www.onsemi.com ILCC48 10x10 CASE 847AG IBGA52 9x9 CASE 503AA ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. * Data Interfaces: Four-lane Serial High-speed * * * Pixel Interface (HiSPi) Differential Signaling (SLVS and HiVCM), or Parallel Auto Black Level Calibration High-speed Context Switching Temperature Sensor Applications * * * * * * * Video Surveillance Stereo Vision Smart Vision Automation Machine Vision 1080p60 Video Applications High Dynamic Range Imaging Publication Order Number: AR0331/D AR0331 Table 1. KEY PARAMETERS Parameter Typical Value Optical Format 1/3-inch (5.8 mm) Note: Sensor optical format will also work with lenses designed for 1/3.2" format. Active Pixels 2048 (H) x 1536 (V) (4:3, mode) Pixel Size 2.2 m x 2.2 m Color Filter Array RGB Bayer Shutter Type Electronic rolling shutter and GRR Input Clock Range 6 - 48 MHz Output Clock Maximum 148.5 Mp/s (4-lane HiSPi) 74.25 Mp/s (Parallel) Output Frame Rate Serial HiSPi 10-, 12-, 14-, or 16-bit Parallel 10-, 12-bit Full Resolution 30 fps 1080p 60 fps Responsivity 1.9 V/lux-sec SNRMAX 39 dB Max Dynamic Range Up to 100 dB Supply Voltage I/O 1.8 or 2.8 V Digital 1.8 V Analog 2.8 V HiSPi 0.3 V-0.6 V, 1.7 V-1.9 V Power Consumption (Typical) <780 mW Operating Temperature (Ambient) -30C to +85 C Package Options 10 x 10 mm 48 pin iLCC 9.5 x 9.5 mm 63-pin iBGA ORDERING INFORMATION Table 2. AVAILABLE PART NUMBERS Part Number Product Description Orderable Product Attribute Description AR0331SRSC00SHCA0-DRBR 48-pin iLCC HiSPi, 0 CRA Dry Pack without Protective Film, Double Side BBAR Glass AR0331SRSC00SHCAD3-GEVK 48-pin iLCC HiSPi, 0 CRA Demo Kit 3 AR0331SRSC00SHCAD-GEVK 48-pin iLCC HiSPi, 0 CRA Demo Kit AR0331SRSC00SHCAH-GEVB 48-pin iLCC HiSPi, 0 CRA Demo Board AR0331SRSC00SUCA0-DPBR 48-pin iLCC Parallel, 0 CRA Dry Pack with Protective Film, Double Side BBAR Glass AR0331SRSC00SUCA0-DRBR 48-pin iLCC Parallel, 0 CRA Dry Pack without Protective Film, Double Side BBAR Glass AR0331SRSC00SUCAD3-GEVK 48-pin iLCC Parallel, 0 CRA Demo Kit 3 AR0331SRSC00SUCAD-GEVK 48-pin iLCC Parallel, 0 CRA Demo Kit AR0331SRSC00SUCAH-GEVB 48-pin iLCC Parallel, 0 CRA Demo Board AR0331SRSC00XUEAD3-GEVK 63-pin iBGA Demo Kit 3 AR0331SRSC00XUEAD-GEVK 63-pin iBGA Demo Kit AR0331SRSC00XUEAH-GEVB 63-pin iBGA Demo Board AR0331SRSC00XUEE0-BY-DRBR 63-pin iBGA, 0 CRA Dry Pack without Protective Film, Double Side BBAR Glass AR0331SRSC00XUEE0-DPBR 63-pin iBGA, 0 CRA Dry Pack with Protective Film, Double Side BBAR Glass AR0331SRSC00XUEE0-DRBR 63-pin iBGA, 0 CRA Dry Pack without Protective Film, Double Side BBAR Glass AR0331SRSC00XUEE0-DRBR1 63-pin iBGA, 0 CRA Dry Pack without Protective Film, Double Side BBAR Glass www.onsemi.com 2 AR0331 FUNCTIONAL OVERVIEW The AR0331 is a progressive-scan sensor that generates a stream of pixel data at a constant frame rate. It uses an on-chip, phase-locked loop (PLL) that can be optionally enabled to generate all internal clocks from a single master input clock running between 6 and 48 MHz. The maximum output pixel rate is 148.5 Mp/s, corresponding to a clock rate of 74.25 MHz. Figure 1 shows a block diagram of the sensor. 12 ADC data Row noise correction Companding Black level correction Test pattern generator Pixel defect correction 12 Adaptive CD filter 12 bits ( HDR and Linear), 12 or 10 bits Linear 16, 14, or 12 bits Motion correction and Blue Halo filter Parallel HiSPi HDR linearization (ME or DLO) 16 Smooting filter Digital gain and pedestal Figure 1. Block Diagram (providing offset correction and gain), and then through an analog-to-digital converter (ADC). The output from the ADC is a 12-bit value for each pixel in the array. The ADC output passes through a digital processing signal chain (which provides further data path corrections and applies digital gain). The sensor also offers a high dynamic range mode of operation where multiple images are combined on-chip to produce a single image at 16-bit per pixel value. A compression mode is further offered to allow the 16-bit pixel value to be transmitted to the host system as a 12-bit value with close to zero loss in image quality. User interaction with the sensor is through the two-wire serial bus, which communicates with the array control, analog signal chain, and digital signal chain. The core of the sensor is a 3.1 Mp Active-pixel Sensor array. The timing and control circuitry sequences through the rows of the array, resetting and then reading each row in turn. In the time interval between resetting a row and reading that row, the pixels in the row integrate incident light. The exposure is controlled by varying the time interval between reset and readout. Once a row has been read, the data from the columns is sequenced through an analog signal chain www.onsemi.com 3 VDD_IO VDD 1.5 kW2 1.5 kW2 Digital Digital I/0 Core Power1 Power1 Master clock (6-48 MHz) EXTCLK From Controller SADDR SDATA SCLK TRIGGER OE_BAR RESET_BAR HiSPi Power1 PLL Analog Analog Power1 Power1 Power1 VDD_SLVS AR0331 VDD_PLL VAA VAA_PIX SLVS1_N SLVS2_P SLVS2_N SLVS3_P SLVS3_N SLVSC_P FLASH SHUTTER DGND VDD VDD_SLVS VDD_PLL VAA AGND VAA_PIX Digital ground Notes: To Controller SLVSC_N TEST VDD_IO SLVS0_P SLVS0_N SLVS1_P Analog ground 1. 2. 3. 4. All power supplies should be adequately decoupled. ON Semiconductor recommends a resistor value of 1.5 k, but a greater value may be used for slower two-wire speed. The parallel interface output pads can be left unconnected if the serial output interface is used. ON Semiconductor recommends that 0.1 F and 10 F decoupling capacitors for each power supply are mounted as close as possible to the pad. Actual values and results may vary depending on layout and design considerations. Refer to the AR0331 demo headboard schematics for circuit recommendations. 5. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is minimized. 6. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents. Figure 2. Typical Configuration: Serial Four-Lane HiSPi Interface www.onsemi.com 4 AR0331 Master clock (6-48 MHz) PLL Analog Analog Power1 Power1 Power1 VDD_PLL VAA VAA_PIX VDD_IO VDD 1.5k2 1.5k2 Digital Digital I/0 Core Power1 Power1 DOUT [11:0] EXTCLK PIXCLK LINE_VALID FRAME_VALID SADDR SDATA SCLK TRIGGER OE_BAR From Controller To Controller FLASH SHUTTER RESET_BAR TEST DGND VDD_IO VDD VDD_PLL VAA VAA_PIX Digital ground Notes: AGND Analog ground 1. 2. 3. 4. All power supplies should be adequately decoupled. ON Semiconductor recommends a resistor value of 1.5 k, but a greater value may be used for slower two-wire speed. The serial interface output pads and VDDSLVS can be left unconnected if the parallel output interface is used. ON Semiconductor recommends that 0.1 F and 10 F decoupling capacitors for each power supply are mounted as close as possible to the pad. Actual values and results may vary depending on layout and design considerations. Refer to the AR0331 demo headboard schematics for circuit recommendations. 5. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is minimized. 6. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents. 7. The EXTCLK input is limited to 6-48 MHz. Figure 3. Typical Configuration: Parallel Pixel Data Interface www.onsemi.com 5 5 4 3 2 1 48 47 46 45 44 EXTCLK VDD_PLL DOUT6 DOUT5 DOUT4 DOUT3 DOUT2 DOUT1 DOUT0 DGND 43 NC 6 DGND AR0331 10 DOUT10 AGND 39 11 DOUT11 VAA_PIX 38 12 VDD_IO VAA_PIX 37 13 PIXCLK VAA 36 14 VDD AGND 35 15 SCLK VAA 34 16 SDATA Reserved 33 17 RESET_BAR NC 32 18 VDD_IO Reserved 31 DGND 40 LINE_VALID VAA FRAME_VALID DOUT9 TRIGGER 9 FLASH 41 TEST NC SADDR DOUT8 OE_BAR 8 NC 42 NC NC NC DOUT7 VDD 7 19 20 21 22 23 24 25 26 27 28 29 30 Figure 4. 48 iLCC Package, Parallel Output Table 3. PIN DESCRIPTION Pin Number Name Type 1 DOUT4 Output Parallel Pixel Data Output 2 DOUT5 Output Parallel Pixel Data Output 3 DOUT6 Output Parallel Pixel Data Output 4 VDD_PLL Power PLL Power 5 EXTCLK Input 6 DGND Power Digital Ground 7 DOUT7 Output Parallel Pixel Data Output 8 DOUT8 Output Parallel Pixel Data Output 9 DOUT9 Output Parallel Pixel Data Output 10 DOUT10 Output Parallel Pixel Data Output Description External Input Clock www.onsemi.com 6 AR0331 Table 3. PIN DESCRIPTION (continued) Pin Number Name Type 11 DOUT11 Output Parallel Pixel Data Output (MSB) 12 VDD_IO Power I/O Supply Power 13 PIXCLK Output Pixel Clock Out. DOUT is Valid on Rising Edge of this Clock 14 VDD Power Digital Power 15 SCLK Input 16 SDATA I/O 17 RESET_BAR Input 18 VDD_IO Power I/O Supply Power 19 VDD Power Digital Power 20 NC 21 NC 22 NC 23 OE_BAR Input Output Enable (Active LOW) 24 SADDR Input Two-wire Serial Address Select. 0: 0x20. 1: 0x30 25 TEST Input Manufacturing Test Enable Pin (Connect to DGND) 26 FLASH Output 27 TRIGGER Input 28 FRAME_VALID Output Asserted when DOUT Frame Data is Valid 29 LINE_VALID Output Asserted when DOUT Line Data is Valid. 30 DGND Power Digital Ground 31 Reserved 32 SHUTTER Output Control for External Mechanical Shutter. Can be Left Floating if not Used 33 Reserved Description Two-wire Serial Clock Input Two-wire Serial Data I/O Asynchronous Reset (Active LOW). All Settings are Restored to Factory Default Flash Output Control Receives Slave Mode VD Signal for Frame Rate Synchronization and Trigger to Start a GRR Frame 34 VAA Power Analog Power 35 AGND Power Analog Ground 36 VAA Power Analog Power 37 VAA_PIX Power Pixel Power 38 VAA_PIX Power Pixel Power 39 AGND Power Analog Ground 40 VAA Power Analog Power 41 NC 42 NC 43 NC 44 DGND Power Digital Ground 45 DOUT0 Output Parallel Pixel Data Output (LSB) 46 DOUT1 Output Parallel Pixel Data Output 47 DOUT2 Output Parallel Pixel Data Output 48 DOUT3 Output Parallel Pixel Data Output www.onsemi.com 7 6 5 4 3 2 1 48 47 46 45 44 43 NC SLVS0_N SLVS0_P SLVS1_N SLVS1_P SLVSC_N SLVSC_P SLVS2_N SLVS2_P SLVS3_N SLVS3_P DGND AR0331 10 VDD NC 39 11 EXTCLK VAA 38 12 VDD NC 37 13 DGND VAA_PIX 36 14 VDD_IO VAA_PIX 35 15 SDATA SHUTTER 34 16 SCLK Reserved 33 17 TEST VAA 32 18 RESET_BAR AGND 31 Reserved 40 VDD_PLL NC DGND DGND FLASH 9 TRIGGER 41 OE_BAR VAA NC VDD_IO SADDR 8 NC 42 VDD_IO AGND DGND VDD_SLVS VDD 7 19 20 21 22 23 24 25 26 27 28 29 30 Figure 5. 48 iLCC Package, HiSPi Output Table 4. PIN DESCRIPTION, 48 ILCC Pin Number Name Type 1 SLVSC_N Output HiSPi Serial DDR Clock Differential N 2 SLVS1_P Output HiSPi Serial Data, Lane 1, Differential P 3 SLVS1_N Output HiSPi Serial Data, Lane 1, Differential N 4 SLVS0_P Output HiSPi Serial Data, Lane 0, Differential P 5 SLVS0_N Output HiSPi Serial Data, Lane 0, Differential N 6 NC 7 VDD_SLVS Power 0.3 V-0.6 V or 1.7 V-1.9 V Port to HiSPi Output Driver. Set the High_VCM (R0x306E[9]) Bit to 1 when Configuring VDD_SLVS to 1.7-1.9 V 8 VDD_IO Power I/O Supply Power 9 DGND Power Digital Ground 10 VDD Power Digital Power Description www.onsemi.com 8 AR0331 Table 4. PIN DESCRIPTION, 48 ILCC (continued) Pin Number Name Type Description 11 EXTCLK Input 12 VDD Power 13 DGND 14 VDD_IO Power 15 SDATA I/O 16 SCLK Input 17 TEST 18 RESET_BAR Input 19 VDD Power Digital Power 20 DGND Power Digital Ground 21 VDD_IO Power I/O Supply Power 22 NC 23 SADDR 24 NC 25 OE_BAR 26 TRIGGER Input 27 FLASH Output 28 DGND Power 29 VDD_PLL Power PLL Power 30 Reserved 31 AGND Power Analog Ground 32 VAA Power Analog Power 33 Reserved 34 SHUTTER Output Control for External Mechanical Shutter. Can be Left Floating if not Used 35 VAA_PIX Power Pixel Power 36 VAA_PIX Power Pixel Power 37 NC 38 VAA Power Analog Power 39 NC 40 NC 41 VAA Power Analog Power 42 AGND Power Analog Ground 43 DGND Power Digital Ground 44 SLVS3_P Output HiSPi Serial Data, Lane 3, Differential P 45 SLVS3_N Output HiSPi Serial Data, Lane 3, Differential N 46 SLVS2_P Output HiSPi Serial Data, Lane 2, Differential P 47 SLVS2_N Output HiSPi Serial Data, Lane 2, Differential N 48 SLVSC_P Output HiSPi Serial DDR Clock Differential P External Input Clock Digital Power Digital Ground I/O Supply Power Two-wire Serial Data I/O Two-wire Serial Clock Input Manufacturing Test Enable Pin (Connect to DGND) Input Asynchronous Reset (Active LOW). All Settings are Restored to Factory Default Two-wire Serial Address Select. 0: 0x20. 1: 0x30 Output Enable (active LOW) Receives Slave Mode VD Signal for Frame Rate Synchronization and Trigger to Start a GRR Frame Flash Output Control www.onsemi.com 9 AR0331 1 A B VDD_PLL C EXTCLK D SADDR E LINE_ VALID 2 3 4 SLVS0_N SLVS0_P SLVS1_N SLVS_CN SLVSC_P SLVS2_N SLVS3_N SLVS3_P SDATA FRAME_ VALID VDD_ SLVS SCLK 5 6 7 8 SLVS1_P VDD VDD NC SLVS2_P VDD VAA VAA DGND VDD AGND AGND DGND DGND VDD VAA_PIX VAA_PIX PIXCLK FLASH DGND VDD_IO NC SHUTTER F DOUT8 DOUT9 DOUT10 DOUT11 DGND VDD_IO TEST Reserved (NC) G DOUT4 DOUT5 DOUT6 DOUT7 DGND VDD_IO TRIGGER OE_BAR H DOUT0 DOUT1 DOUT2 DOUT3 DGND VDD_IO VDD_IO RESET_ BAR Top View (Ball Down) Figure 6. 9.5 x 9.5 mm 63-Ball IBGA Package Table 5. PIN DESCRIPTIONS, 9.5 x 9.5 mm, 63-BALL IBGA Name iBGA Pin Type Description SLVS0_N A2 Output HiSPi Serial Data, Lane 0, Differential N SLVS0_P A3 Output HiSPi Serial Data, Lane 0, Differential P SLVS1_N A4 Output HiSPi Serial Data, Lane 1, Differential N SLVS1_P A5 Output HiSPi Serial Data, Lane 1, Differential P VDD_PLL B1 Power PLL power. SLVSC_N B2 Output HiSPi Serial DDR Clock Differential N SLVSC_P B3 Output HiSPi Serial DDR Clock Differential P SLVS2_N B4 Output HiSPi Serial Data, Lane 2, Differential N SLVS2_P B5 Output HiSPi Serial Data, Lane 2, Differential P VAA B7, B8 Power Analog Power EXTCLK C1 Input VDD_SLVS C2 Power 0.3 V-0.6 V or 1.7 V-1.9 V port to HiSPi Output Driver. Set the High_VCM (R0x306E[9]) bit to 1 when configuring VDD_SLVS to 1.7-1.9 V SLVS3_N C3 Output HiSPi Serial Data, Lane 3, Differential N SLVS3_P C4 Output HiSPi Serial Data, Lane 3, Differential P DGND C5, D4, D5, E5, F5, G5, H5 Power External Input Clock. Digital Ground www.onsemi.com 10 AR0331 Table 5. PIN DESCRIPTIONS, 9.5 x 9.5 mm, 63-BALL IBGA (continued) Name iBGA Pin Type Description VDD A6, A7, B6, C6, D6 Power Digital Power AGND C7, C8 Power Analog Ground SADDR D1 Input Two-wire Serial Address Select. 0: 0x20. 1: 0x30 SCLK D2 Input Two-wire Serial Clock Input SDATA D3 I/O VAA_PIX D7, D8 Power Pixel Power Two-Wire Serial Data I/O LINE_VALID E1 Output Asserted when DOUT Line Data is Valid FRAME_VALID E2 Output Asserted when DOUT Frame Data is Valid. PIXCLK E3 Output Pixel Clock Out. DOUT is Valid on Rising Edge of this Clock. VDD_IO E6, F6, G6, H6, H7 Power I/O Supply Power DOUT8 F1 Output Parallel Pixel Data Output DOUT9 F2 Output Parallel Pixel Data Output DOUT10 F3 Output Parallel Pixel Data Output DOUT11 F4 Output Parallel Pixel Data Output (MSB) TEST F7 Input. Manufacturing Test Enable Pin (Connect to DGND) DOUT4 G1 Output Parallel Pixel Data Output DOUT5 G2 Output Parallel Pixel Data Output DOUT6 G3 Output Parallel Pixel Data Output Parallel Pixel Data Output DOUT7 G4 Output TRIGGER G7 Input Exposure Synchronization Input OE_BAR G8 Input Output Enable (Active LOW) DOUT0 H1 Output Parallel Pixel Data Output (LSB) DOUT1 H2 Output Parallel Pixel Data Output DOUT2 H3 Output Parallel Pixel Data Output DOUT3 H4 Output Parallel Pixel Data Output RESET_BAR H8 Input Asynchronous reset (active LOW). All settings are restored to factory default SHUTTER E8 Output Control for external mechanical shutter. Can be left floating if not used FLASH E4 Output Flash Control Output NC A8, E7 Reserved F8 www.onsemi.com 11 AR0331 PIXEL DATA FORMAT Pixel Array Structure always performed for monochrome or color versions. The active area is surrounded with optically transparent dummy pixels to improve image uniformity within the active area. Not all dummy pixels or barrier pixels can be read out. While the sensor's format is 2048 x 1536, additional active columns and active rows are included for use when horizontal or vertical mirrored readout is enabled, to allow readout to start on the same pixel. The pixel adjustment is 2064 16 barrier + 4 border pixels 2052 1 x 1536 4.51mm x 3.38 mm 1578 2 barrier + 4 border pixels 2 barrier + 4 border pixels 18 barrier + 4 border pixels Light dummy pixel Active pixel 1. Maximum of 2048 columns is supported. Additional columns included for mirroring operations. Figure 7. Pixel Array Description RowReadout Direction Column Readout Direction Active Pixel (0,0) Array Pixel (0, 0) R G R G R G R G G B G B G B G B R G R G R G R G G B G B G B G B R G R G R G R G G B G B G B G B Figure 8. Pixel Color Pattern Detail (Top Right Corner) www.onsemi.com 12 AR0331 Default Readout Order When the sensor is imaging, the active surface of the sensor faces the scene as shown in Figure 9. When the image is read out of the sensor, it is read one row at a time, with the rows and columns sequenced as shown in Figure 9. By convention, the sensor core pixel array is shown with pixel (0,0) in the top right corner (see Figure 8). This reflects the actual layout of the array on the die. Also, the first pixel data read out of the sensor in default condition is that of pixel (0, 0). Lens Scene Sensor (rear view) Row Readout Order Column Readout Order Pixel (0,0) Figure 9. Imaging a Scene www.onsemi.com 13 AR0331 PIXEL OUTPUT INTERFACES Parallel Interface When the parallel pixel data interface is in use, the serial data output signals can be left unconnected. Set reset_register [bit 12 (R0x301A[12] = 1)] to disable the serializer while in parallel output mode. The parallel pixel data interface uses these output-only signals: * FRAME_VALID * LINE_VALID * PIXCLK * DOUT[11:0] Output Enable Control When the parallel pixel data interface is enabled, its signals can be switched asynchronously between the driven and High-Z under pin or register control, as shown in Table 6. The parallel pixel data interface is disabled by default at power up and after reset. It can be enabled by programming R0x301A. Table 7 shows the recommended settings. Table 6. OUTPUT ENABLE CONTROL OE_BAR Pin Drive Pins R0x301A[6] Description 1 0 Interface High-Z X 1 Interface Driven 0 X Interface Driven Configuration of the Pixel Data Interface Fields in R0x301A are used to configure the operation of the pixel data interface. The supported combinations are shown in Table 7. Table 7. CONFIGURATION OF THE PIXEL DATA INTERFACE Serializer Disable R0x301 A[12] Parallel Enable R0x301 A[7] 0 0 Power up default Serial pixel data interface and its clocks are enabled. Transitions to soft standby are synchronized to the end of frames on the serial pixel data interface 1 1 Parallel pixel data interface, sensor core data output. Serial pixel data interface and its clocks disabled to save power. Transitions to soft standby are synchronized to the end of frames in the parallel pixel data interface Description High Speed Serial Pixel Data Interface by the sensor is transmitted at the same length. The Packetized SP protocol will transmit only the active data ignoring line-to-line and frame-to-frame blanking data. These protocols are further described in the High-Speed Serial Pixel (HiSPi) Interface Protocol Specification V1.50.00. The HiSPi interface building block is a unidirectional differential serial interface with four data and one double data rate (DDR) clock lanes. One clock for every four serial data lanes is provided for phase alignment across multiple lanes. Figure 10 shows the configuration between the HiSPi transmitter and the receiver. The HiSPi interface building block is a unidirectional differential serial interface with four data and one double data rate (DDR) clock lanes. One clock for every four serial data lanes is provided for phase alignment across multiple lanes. Figure 10 shows the configuration between the HiSPi transmitter and the receiver. The High Speed Serial Pixel (HiSPi) interface uses four data lanes and one clock as output. * SLVSC_P * SLVSC_N * SLVS0_P * SLVS0_N * SLVS1_P * SLVS1_N * SLVS2_P * SLVS2_N * SLVS3_P * SLVS3_N The HiSPi interface supports three protocols, Streaming-S, Streaming-SP, and Packetized SP. The streaming protocols conform to a standard video application where each line of active or intra-frame blanking provided www.onsemi.com 14 AR0331 A camera containing the HiSPi transmitter A host (DSP) containing the HiSPi receiver Dp0 Dp0 Tx PHY0 Dn0 Dn0 Dp1 Dp1 Dn1 Dn1 Dp2 Dp2 Dn2 Dn2 Dp3 Dp3 Dn3 Dn3 Cp0 Cp0 Cn0 Cn0 Rx PHY0 Figure 10. HiSPi Transmitter and Receiver Interface Block Diagram The PHY will serialize 10-, 12-, 14-, or 16-bit data words and transmit each bit of data centered on a rising edge of the clock, the second on the falling edge of the clock. Figure 11 shows bit transmission. In this example, the word is transmitted in order of MSB to LSB. The receiver latches data at the rising and falling edge of the clock. HiSPi Physical Layer The HiSPi physical layer is partitioned into blocks of four data lanes and an associated clock lane. Any reference to the PHY in the remainder of this document is referring to this minimum building block. TxPost cp ... cn TxPre ... MSB dn 1 UI Figure 11. Timing Diagram DLL Timing Adjustment can be used to compensate for skew introduced in PCB design. Delay compensation may be set for clock and/or data lines in the hispi_timing register R0x31C0. If the DLL timing adjustment is not required, the data and clock lane delay settings should be set to a default code of 0x000 to reduce jitter, skew, and power dissipation. del 2[2: 0] del 1[2: 0] delclock[2:0] The specification includes a DLL to compensate for differences in group delay for each data lane. The DLL is connected to the clock lane and each data lane, which acts as a control master for the output delay buffers. Once the DLL has gained phase lock, each lane can be delayed in 1/8 unit interval (UI) steps. This additional delay allows the user to increase the setup or hold time at the receiver circuits and DATA0_DEL[2:0] LSB del 3[2: 0] dp delay delay delay delay delay data _lane 0 data _lane 1 clock_lane0 data_lane2 data_lane3 Figure 12. Block Diagram of DLL Timing Adjustment www.onsemi.com 15 AR0331 1 UI dataN (DATAN_DEL = 000) cp (CLOCK_DEL = 000) cp (CLOCK_DEL = 001) cp (CLOCK_DEL = 010) cp (CLOCK_DEL = 011) cp (CLOCK_DEL = 100) cp (CLOCK_DEL = 101) cp (CLOCK_DEL = 110) cp (CLOCK_DEL = 111) Increasing CLOCK_DEL[2:0] Increases Clock Delay Figure 13. Delaying the Clock with Respect to Data cp (CLOCK_DEL = 000) dataN (DATAN_DEL = 000) dataN (DATAN_DEL = 001) dataN (DATAN_DEL = 010) dataN (DATAN_DEL = 011) dataN (DATAN_DEL = 100) dataN (DATAN_DEL = 101) dataN (DATAN_DEL = 110) dataN (DATAN_DEL = 111) Increasing DATAN_DEL[2:0] Increases Data Delay t DLLSTEP 1 UI Figure 14. Delaying Data with Respect to the Clock The serial_format register (R0x31AE) controls which serial format is in use when the serial interface is enabled (reset_register[12] = 0). The following serial formats are supported: * 0x0304 - Sensor supports quad-lane HiSPi operation * 0x0302 - Sensor supports dual-lane HiSPi operation * 0x0301 - Sensor supports single-lane HiSPi operation HiSPi Protocol Layer The HiSPi protocol is described the HiSPi Protocol Specification document. Serial Configuration The serial format should be configured using R0x31AC. Refer to the AR0331 Register Reference document for more detail regarding this register. www.onsemi.com 16 AR0331 PIXEL SENSITIVITY Row Integration (TINTEGRATION) Row Reset (Start of Integration) Row Readout Figure 15. Integration Control in ERS Readout The coarse integration time is defined by the number of row periods (TROW) between a row's reset and the row read. The row period is defined as the time between row read operations (see Sensor Frame Rate). A pixel's integration time is defined by the number of clock periods between a row's reset and read operation. Both the read followed by the reset operations occur within a row period (TROW) where the read and reset may be applied to different rows. The read and reset operations will be applied to the rows of the pixel array in a consecutive order. T COARSE + T ROW coarse_integration_time (eq. 1) TCOARSE = coarse_integration_time x TROW 8.33 ms = 563 rows x 22.2 s/row Read Reset Horizontal Blanking Vertical Blanking TFRAME = frame_length_lines x TROW 16.6 ms = 750 rows x 22.22 s/row Vertical Blanking Figure 16. Example of 8.33 ms Integration in 16.6 ms Frame www.onsemi.com 17 AR0331 TCOARSE = coarse_integration_time x TROW 20.7 ms = 1390 rows x 14.8 s/row Read Pointer Horizontal Blanking Vertical Blanking TFRAME = frame_length_lines x TROW Image 16.6 ms = 1125rows x 14.8 s/row Vertical Blanking Time Shutter Pointer Horizontal Blanking Extended Vertical Blanking 4.1 ms Image Figure 17. The Row Integration Time is Greater Than the Frame Readout Time The minimum frame-time is defined by the number of row periods per frame and the row period. The sensor frame-time will increase if the coarse_integration_time is set to a value equal to or greater than the frame_length_lines. GAIN STAGES The analog gain stages of the AR0331 sensor are shown in Figure 18. The sensor analog gain stage consists of a variable ADC reference. The sensor will apply the same analog gain to each color channel. Digital gain can be configured to separate levels for each color channel. ADC Digital Gain Reference with Dithering 1x, 2x, 4x, and 8x 1x to 16x (128 steps per 6dB) Figure 18. Gain Stages in AR0331 Sensor The level of analog gain applied is controlled by the coarse_gain register. The recommended analog gain settings are listed in Table 8. A minimum analog gain of 1.23x is recommended. Changes to these registers should be done prior to streaming images. www.onsemi.com 18 AR0331 Table 8. RECOMMENDED SENSOR GAIN coarse_gain(0x3060[5:4])/ coarse_gain_cb (0x3060[13:12]) fine_gain (0x3060[3:0])/ fine_gain_cb (0x3060[11:8]) ADC Gain 0 6 1.23 0 7 1.28 0 8 1.34 0 9 1.39 0 10 1.45 0 11 1.52 0 12 1.60 0 13 1.69 0 14 1.78 0 15 1.88 1 0 2.00 1 2 2.14 1 4 2.28 1 6 2.47 1 8 2.67 1 10 2.91 1 12 3.20 1 14 3.56 2 0 4 2 4 4.56 2 8 5.34 2 12 6.41 3 0 8 Each digital gain can be configured from a gain of 0 to 15.992. The digital gain supports 128 gain steps per 6dB of gain. The format of each digital gain register is "xxxx.yyyyyyy" where "xxxx" refers an integer gain of 1 to 15 and "yyyyyyy" is a fractional gain ranging from 0/128 to 127/128. The sensor includes a digital dithering feature to reduce quantization noise resulting from using digital gain. It can be disabled by setting R0x30BA[5] to 0. The default value is 1. PEDESTALS There are two types of constant offset pedestals that may be adjusted at the end of the datapath. The data pedestal is a constant offset that is added to pixel values at the end of the datapath. The default offset when ALTM is disabled is 168 and is a 12-bit offset. This offset matches the maximum range used by the corrections in the digital readout path. The purpose of the data pedestal is to convert negative values generated by the digital datapath into positive output data. It is recommended that the data pedestal be set to 16 when ALTM is enabled. The data pedestal value can be changed from its default value by adjusting register R0x301E. The ALTM pedestal (R0x2450) is also located at the end of the datapath. The ALTM pedestal default offset is 0. www.onsemi.com 19 AR0331 HIGH DYNAMIC RANGE MODE By default, the sensor powers up in HDR Mode. The HDR scheme used is multi-exposure HDR. This allows the sensor to handle up to 100 dB of dynamic range. In HDR mode, the sensor sequentially captures two exposures by maintaining two separate read and reset pointers that are interleaved within the rolling shutter readout. The intermediate pixel values are stored in line buffers while waiting for the two exposure values to be present. As soon as a pixel's two exposure values are available, they are combined to create a linearized 16-bit value for each pixel's response. Depending on whether HiSPi or Parallel mode is selected, the full 16 bit value may be output, it can be compressed to 12 bits using Adaptive Local Tone Mapping (ALTM), or companded to 12 or 14 bits. range of display devices. Today's typical LCD monitor has a contrast ratio around 1000:1 while it is not atypical for an HDR image having a contrast ratio of around 250000:1. Therefore, in order to reproduce HDR images on a low dynamic range display device, the captured high dynamic range must be compressed to the available range of the display device. This is commonly called tone mapping. The AR0331 has implemented an adaptive local tone mapping (ALTM) feature to reproduce visually appealing images that increase the local contrast and the visibility of the images. When ALTM is enabled, the gamma in the backend ISP should be set to 1 for proper display. See the AR0331 Developer Guide for more information on ALTM. Adaptive Local Tone Mapping Companding Real- world scenes often have a very high dynamic range (HDR) that far exceeds the electrical dynamic range of the imager. Dynamic range is defined as the luminance ratio between the brightest and the darkest objects in a scene. Even though the AR0331 can capture full dynamic range images, the images are still limited by the low dynamic The 16-bit linearized HDR image may be compressed to 12 bits using on-chip companding. Figure 19 illustrates the compression from 16- to 12-bits. Companding is enabled by setting R0x31D0. Table 10 shows the knee points for the different modes. 4500 4000 3500 12-bit Code Output 3000 2500 2000 1500 1000 500 0 0 10000 20000 30000 40000 16-bit Code Input Figure 19. HDR Data Compression www.onsemi.com 20 50000 60000 70000 AR0331 Table 9. COMPANDING TABLE Segment 1 Segment 2 Segment 3 Segment 4 Input Code Range 0 to 1023 1024 to 4095 4096 to 32767 32768 to 65535 Output Code Range 0 to 1023 1024 to 2559 2560 to 3455 3456 to 3967 Companding Formula Pout = Pin Pout = (Pin - 1024)/2 + 1024 Pout = (Pin - 4096)/32 + 2560 Pout = (Pin - 32768)/64 + 3456 Decompanding Formula Pout = Pin Pout = (Pin - 1024)*2 + 1024 Pout = (Pin - 2560)*32 + 4096 Pout = (Pin - 3456)*64 + 32768 Table 9 illustrates the input and output codes as well as companding and decompanding formulas for each of the four colored segments in Figure 19. Table 10. KNEE POINTS FOR COMPRESSION FROM 16 BITS TO 12 BITS T1/T2 Exposure Ratio (R1) R0x3082[3:2] P1 POUT1 = P1 P2 POUT2= (P2 - P1)/2 + 1024 P3 POUT3= (P3 - P2)/32 + 2560 PMAX POUTMAX = (PMAX - P3)/64 + 3456 4x, 8x, 16x, 32x 210 1024 212 2560 215 3456 216 3968 As described in Table 10, the AR0331 companding block operates on 16-bit input only. For the exposure ratios that do not result in 16-bits, bit shifting occurs before the data enters the companding block. As a result of the bit shift, data needs to be unshifted after linearization in order to obtain the proper image. Table 11 provides the bit operation that should occur to the data after linearization. Table 11. BIT OPERATION AFTER LINEARIZATION ratio_t1_t2 (R0x3082[3:2])/ratio_t1_t2_cb (R0x3084[3:2]) Bit Shift Operation after Linearization 4x Right Shift 2 Bits 8x Right Shift 1 Bit 16x No Shift 32x Left Shift 1 Bit HDR-Specific Exposure Settings then relinearization would still follow the programmed ratio. For example if the T1/T2 ratio was programmed to 16x but coarse integration was increased beyond 1120 then one would still use the 16x relinearization formulas. An additional limitation is the maximum number of exposure lines in relation to the frame_length_lines register. In linear mode, maximum coarse_integration_time = frame_length_lines - 1. However in HDR mode, since the coarse integration time register controls T1, the max coarse integration time is frame_length_lines - 71. Putting the two criteria listed above together, the formula is as follows: In HDR mode, pixel values are stored in line buffers while waiting for both exposures to be available for final pixel data combination. There are 70 line buffers used to store intermediate T1 data. Due to this limitation, the maximum coarse integration time possible for a given exposure ratio is equal to 70*T1/T2 lines. For example, if R0x3082[3:2] = 2, the sensor is set to have T1/T2 ratio = 16x. Therefore the maximum number of integration lines is 70*16 = 1120 lines. If coarse integration time is greater than this, the T2 integration time will stay at 70. The sensor will calculate the ratio internally, enabling the linearization to be performed. If companding is being used, maximum coarse_integration_time + minimum(70 There is a limitation of the minimum number of exposure lines, which is one row time for linear mode. In HDR mode, T1 , frame_length_lines-71) T2 (eq. 2) the minimum number of rows required is half of the ratio T1/T2. www.onsemi.com 21 AR0331 Motion Compensation The motion compensation feature can be enabled by setting R0x318C[14] = 1. Additional parameters are available to control the extent of motion detection and correction as per the requirements of the specific application. For more information, refer to the AR0331 Register Reference document and the AR0331 Developer Guide. In typical multi-exposure HDR systems, motion artifacts can be created when objects move during the T1 or T2 integration time. When this happens, edge artifacts can potentially be visible and might look like a ghosting effect. To correct this, the AR0331 has special 2D motion compensation circuitry that detects motion artifacts and corrects the image. RESET Soft Reset of Logic The AR0331 may be reset by the RESET_BAR pin (active LOW) or the reset register. Soft reset of logic is controlled by the R0x301A Reset register. Bit 0 is used to reset the digital logic of the sensor. Furthermore, by asserting the soft reset, the sensor aborts the current frame it is processing and starts a new frame. This bit is a self-resetting bit and also returns to "0" during two-wire serial interface reads. Hard Reset of Logic The RESET_BAR pin can be connected to an external RC circuit for simplicity. The recommended RC circuit uses a 10 k resistor and a 0.1 F capacitor. The rise time for the RC circuit is 1 s maximum. SENSOR PLL VCO EXTCLK (6-48 MHz) pll_multiplier 58(32-384) pre_pll_clk_div 2(1-64) FVC0 Figure 20. PLL Dividers Affecting VCO Frequency The sensor contains a phase-locked loop (PLL) that is used for timing generation and control. The required VCO clock frequency is attained through the use of a pre-PLL clock divider followed by a multiplier. The PLL multiplier should be an even integer. If an odd integer (M) is programmed, the PLL will default to the lower (M-1) value to maintain an even multiplier value. The multiplier is followed by a set of dividers used to generate the output clocks required for the sensor array, the pixel analog and digital readout paths, and the output parallel and serial interfaces. Use of the PLL is required when using the HiSPi interface. www.onsemi.com 22 AR0331 Dual Readout Paths output pixel rate. For example, if CLK_PIX is 74.25 MHz in a 4-lane HiSPi configuration, the CLK_OP should be equal to 37.125 MHz. There are two readout paths within the sensor digital block. The sensor PLL should be configured such that the total pixel rate across both readout paths is equal to the CLK_PIX All Digital Blocks Serial Output (HiSPi) Pixel Array Pixel Rate = 2 x CLK_PIX = # data lanes x CLK_OP (HiSPi) = CLK_OP (Parallel) All Digital Blocks CLK_PIX Figure 21. Sensor Dual Readout Paths The sensor row timing calculation refers to each data-path individually. For example, the sensor default configuration uses 1100 clocks per row (line_length_pck) to output 1928 active pixels per row. The aggregate clocks per row seen by the receiver will be 2200 clocks (1100 x 2 readout paths). Parallel PLL Configuration FVC0 EXTCLK (6-48 MHz) pre_pll_clk_div 2(1-64) vt_sys_clk_div 1 (1,2,4,6,8,10 12,14,160 pll_multiplier 58(32-384) vt_pix_clk_div 6(4-16) CLK_OP (Max 74.25 Mp/s) CLK_PIX (Max 37.125 Mp/s) Figure 22. PLL for the Parallel Interface The maximum output of the parallel interface is 74.25 MPixel/s. This will limit the readout clock (CLK_PIX) to 37.125 MPixel/s. The sensor will not use the FSERIAL, FSERIAL_CLK, or CLK_OP when configured to use the parallel interface. Table 12. PLL PARAMETERS FOR THE PARALLEL INTERFACE Parameter Symbol Min Max Unit External Clock EXTCLK 6 48 MHz VCO Clock FVCO 384 768 MHz Readout Clock CLK_PIX 37.125 Mpixel/s Output Clock CLK_OP 74.25 Mpixel/s www.onsemi.com 23 AR0331 Table 13. EXAMPLE PLL CONFIGURATION FOR THE PARALLEL INTERFACE Parameter Value Output 445.5 MHz (Max) FVCO vt_sys_clk_div 1 vt_pix_clk_div 6 CLK_PIX 37.125 MPixel/s (= 445.5 MHz / 12) CLK_OP 74.25 MPixel/s (= 445.5 MHz / 6) Output pixel rate 74.25 MPixel/s Serial PLL Configuration FVC0 pre_pll_clk_div 2 (1-64) pll_multiplier 58 (32-384) Vt_sys_clk_div 1 (1, 2, 4, 6, 8, 10,11, 12,14, 16) Vt_pix_clk_div 6 (4-16) op_sys_clk_div (default = 1) op_pix_clk_div 12 (8,10, 12) CLK_PIX CLK_OP FVC0 FSERIAL Figure 23. PLL for the Serial Interface The PLL must be enabled when HiSPi mode is selected. The sensor will use op_sys_clk_div and op_pix_clk_div to configure the output clock per lane (CLK_OP). The configuration will depend on the number of active lanes (1, 2, or 4) configured. To configure the sensor protocol and number of lanes, refer to "Serial Configuration". Table 14. PLL PARAMETERS FOR THE SERIAL INTERFACE Parameter Symbol Min Max Unit External Clock EXTCLK 6 48 MHz External Clock EXTCLK 6 48 MHz 384 VCO Clock FVCO 768 MHz Readout Clock CLK_PIX 74.25 Mpixel/s Output Clock CLK_OP 37.125 Mpixel/s Output Serial Data Rate Per Lane FSERIAL 300 (HiSPi) 700 (HiSPi) Mbps Output Serial Clock Speed Per Lane FSERIAL_CLK 150 (HiSPi) 350 (HiSPi) MHz www.onsemi.com 24 AR0331 Configure the serial output so that it adheres to the following rules: * The maximum data-rate per lane (FSERIAL) is 700 Mbps/lane (HiSPi). * Configure the output pixel rate per lane (CLK_OP) so that the sensor output pixel rate matches the peak pixel rate (2 x CLK_PIX). 4-lane: 4 x CLK_OP = 2 x CLK_PIX = Pixel Rate (max: 148.5 Mpixel/s) 2-lane: 2 x CLK_OP = 2 x CLK_PIX = Pixel Rate (max: 74.25 Mpixel/s) 1-lane: 1 x CLK_OP = 2 x CLK_PIX = Pixel Rate (max: 37.125 Mpixel/s) Table 15. EXAMPLE PLL CONFIGURATIONS FOR THE SERIAL INTERFACE 4-lane 2-lane 1-lane Parameter 16-bit 14-bit 12-bit 10-bit 12-bit 10-bit 10-bit Units FVCO 594 519.75 445.5 742.5 445.5 742.5 742.5 MHz vt_sys_clk_div 1 1 1 2 1 2 4 vt_pix_clk_div 8 7 6 5 12 10 10 op_sys_clk_div 1 1 1 2 1 2 2 op_pix_clk_div 16 14 12 10 12 10 10 FSERIAL 594 519.75 445.5 371.25 445.5 371.25 371.25 MHz FSERIAL_CLK 297 259.875 222.75 185.63 222.75 185.63 185.63 MHz CLK_PIX 74.25 74.25 74.25 74.25 37.125 37.125 18.563 Mpixel/s CLK_OP 37.125 37.125 37.125 37.125 37.125 37.125 37.125 Mpixel/s Pixel Rate 148.5 148.5 148.5 148.5 74.25 74.25 37.125 Mpixel/s Stream/Standby Control A specific sequence needs to be followed to enter and exit from Soft Standby. The sensor supports a soft standby mode. In this mode, the external clock can be optionally disabled to further minimize power consumption. If this is done, then the "Power-Up Sequence" must be followed. When the external clock is disabled, the sensor will be unresponsive to register writes and other operations. Soft Standby is a low-power state that is controlled through register R0x301A[2]. The sensor will go to Standby after completion of the current frame readout. When the sensor comes back from Soft Standby, previously written register settings are still maintained. Soft Standby will not occur if the Trigger pin is held high. Entering Soft Standby: 1. Set R0x301A[12] = 1 if serial mode was used 2. Set R0x301A[2] = 0 and drive Trigger pin low. 3. Turn off external clock to further minimize power consumption Exiting Soft Standby: 1. Enable external clock if it was turned off 2. Set R0x301A[2] = 1 or drive Trigger pin high. 3. Set R0x301A[12] = 0 if serial mode is used www.onsemi.com 25 AR0331 SENSOR READOUT Image Acquisition Modes * * current resolution. In this mode, the end point of the pixel integration time is controlled by an external electromechanical shutter, and the AR0331 provides control signals to interface to that shutter. The AR0331 supports two image acquisition modes: Electronic rolling shutter (ERS) mode: This is the normal mode of operation. When the AR0331 is streaming, it generates frames at a fixed rate, and each frame is integrated (exposed) using the ERS. When the ERS is in use, timing and control logic within the sensor sequences through the rows of the array, resetting and then reading each row in turn. In the time interval between resetting a row and subsequently reading that row, the pixels in the row integrate incident light. The integration (exposure) time is controlled by varying the time between row reset and row readout. For each row in a frame, the time between row reset and row readout is the same, leading to a uniform integration time across the frame. When the integration time is changed (by using the two-wire serial interface to change register settings), the timing and control logic controls the transition from old to new integration time in such a way that the stream of output frames from the AR0331 switches cleanly from the old integration time to the new while only generating frames with uniform integration. See "Changes to Integration Time" in the AR0331 Register Reference. Global reset mode: This mode can be used to acquire a single image at the The benefit of using an external electromechanical shutter is that it eliminates the visual artifacts associated with ERS operation. Visual artifacts arise in ERS operation, particularly at low frame rates, because an ERS image effectively integrates each row of the pixel array at a different point in time. Window Control The sequencing of the pixel array is controlled by the x_addr_start, y_addr_start, x_addr_end, and y_addr_end registers. Readout Modes Horizontal Mirror When the horiz_mirror bit (R0x3040[14]) is set in the read_mode register, the order of pixel readout within a row is reversed, so that readout starts from x_addr_end + 1 and ends at x_addr_start. Figure 24 shows a sequence of 6 pixels being read out with R0x3040[14] = 0 and R0x3040[14] = 1. LINE_VALID horizontal_mirror = 0 DOUT[11:0] G0[11:0] R0[11:0] G1[11:0] R1[11:0] G2[11:0] R2[11:0] horizontal_mirror = 1 DOUT[11:0] G3[11:0] R2[11:0] G2[11:0] R1[11:0] G1[11:0] R0[11:0] Figure 24. Effect of Horizontal Mirror on Readout Order and ends at y_addr_start. Figure 30 shows a sequence of 6 rows being read out with R0x3040[15] = 0 and R0x3040[15] = 1. Vertical Flip When the vert_flip bit (R0x3040[15]) is set in the read_mode register, the order in which pixel rows are read out is reversed, so that row readout starts from y_addr_end FRAME_VALID vertical_flip = 0 DOUT[11:0] vertical_flip = 1 DOUT[11:0] Row0[11:0] Row1[11:0] Row2[11:0] Row3[11:0] Row4[11:0] Row6[11:0] Row5[11:0] Row4[11:0] Row3[11:0] Row2[11:0] Row1[11:0] Figure 25. Effect of Vertical Flip on Readout Order www.onsemi.com 26 Row5[11:0] AR0331 SUBSAMPLING The AR0331 supports subsampling. Subsampling allows the sensor to read out a smaller set of active pixels by either skipping, binning, or summing pixels within the readout window. The following examples are configured to use either 2 x 2 or 3 x 3 subsampling. Isb Isb Isb Isb Isb Isb Figure 26. Horizontal Binning in the AR0331 Sensor Horizontal binning is achieved either in the pixel readout or the digital readout. The sensor will sample the combined 2x or 3x adjacent pixels within the same color plane. e- e- e- e- Figure 27. Vertical Row Binning in the AR0331 Sensor the y-direction will reduce the number of rows from the sensor effectively reducing the frame time. Skipping will introduce image artifacts from aliasing. Refer to the AR0331 Developer Guide for details on configuring skipping, binning, and summing modes for color and monochrome operation. Vertical row binning is applied in the pixel readout. Row binning can be configured as 2x or 3x rows within the same color plane. Pixel skipping can be configured up to 2x and 3x in both the x-direction and y-direction. Skipping pixels in the x-direction will not reduce the row time. Skipping pixels in www.onsemi.com 27 AR0331 SENSOR FRAME RATE The time required to read out an image frame (TFRAME) can be derived from the number of clocks required to output each image and the pixel clock. The frame-rate is the inverse of the frame period. fps + 1 T FRAME * The number of clocks required for each sensor row (eq. 3) * The number of clocks can be simplified further into the following parameters: T FRAME + 1 (CLK_PIX) * [frame_length_lines (line_length_pck) This parameter also determines the sensor row period when referenced to the sensor readout clock. (TROW = line_length_pck x 1/CLK_PIX) The number of row periods per frame (frame_length_lines) An extra delay between frames used to achieve a specific output frame period (extra_delay) line_length_pck ) extra_delay] (eq. 4) Figure 28. Frame Period Measured in Clocks Row Period (TROW) Output Interface Limitations: line_length_pck will determine the number of clock periods per row and the row period (TROW) when combined with the sensor readout clock. line_length_pck includes both the active pixels and the horizontal blanking time per row. The sensor utilizes two readout paths, as seen in Figure 21, allowing the sensor to output two pixels during each pixel clock. The minimum line_length_pck is defined as the maximum of the following three equations: 1 2 frame_length_lines determines the number of row periods (TROW) per frame. This includes both the active and blanking rows. The minimum vertical blanking value is defined by the number of OB rows read per frame, two embedded data rows, and two blank rows. A minimum number of idle rows equal to the T2 integration time should be added in HDR mode to allow for changes in integration time by an auto exposure algorithm. For example, if the coarse integration time is 320 lines and the exposure ratio is 16x, then the minimum vertical blanking would be 8 + 2 + 2 + 20 = 32 rows. The minimum (default) number of idle rows is 4. (eq. 5) Digital Readout Limitation: 1 3 )1 x_addr_end-x_addr_start (x_odd_inc ) 1) 0.5 Minimum frame_length_lines + (eq. 7) Row Periods Per Frame ADC Readout Limitation: line_length_pck 1100 )1 x_addr_end-x_addr_start ) 96 (x_odd_inc ) 1) 0.5 (eq. 6) y_addr_end-y_addr_start ) 1 ) min_vertical_blanking (y_odd_inc)1) 2 The sensor is configured to output frame information in two embedded data rows by setting R0x3064[8] to 1 (default). If R0x3064[8] is set to 0, the sensor will instead (eq. 8) output two blank rows. The data configured in the two embedded rows is defined in "Embedded Data and Statistics". www.onsemi.com 28 AR0331 Table 16. MINIMUM VERTICAL BLANKING CONFIGURATION R0x3180[7:4] OB Rows min_vertical_blanking (Note 1) 0x8 (Default) 8 OB Rows 8 OB + 8 = 16 0x4 4 OB Rows 4 OB + 8 = 12 0x2 2 OB Rows 2 OB + 8 = 10 1. min_vertical_blanking includes the default number (4) of idle rows. The locations of the OB rows, embedded rows, and blank rows within the frame readout are identified in Figure 29: "Slave Mode Active State and Vertical Blanking," . SLAVE MODE The slave mode feature of the AR0331 supports triggering the start of a frame readout from a VD signal that is supplied from an external ASIC. The slave mode signal allows for precise control of frame rate and register change updates. The VD signal is an edge triggered input to the trigger pin and must be at least 3 PIXCLK cycles wide. Frame Valid VD Signal Time Start of frame N OB Rows (2, 4, or 8 rows) Embedded Data Row (2 rows) Active Data Rows Blank Rows (2 rows) Extra Vertical Blanking (frame_length_lines - min_frame_length_lines) Extra Delay (clocks) The period between the rising edge of the VD signal and the slave mode ready state is TFRAME + 16 clock Slave Mode Active State End of frame N Start of frame N + 1 Figure 29. Slave Mode Active State and Vertical Blanking slave mode will remain inactive for the period of one frame time plus 16 clock periods (TFRAME + (16 / CLK_PIX)). After this period, the slave mode will re-enter the active state and will respond to the VD signal. If the slave mode is disabled, the new frame will begin after the extra delay period is finished. The slave mode will react to the rising edge of the input VD signal if it is in an active state. When the VD signal is received, the sensor will begin the frame readout and the www.onsemi.com 29 AR0331 Frame Valid Rising Edge Rising Edge Rising Edge VD Signal Slave Mode Trigger Inactive Active Inactive Row Reset (start of integration) Active Row reset and read operations begin after the rising edge of the VD signal. Rising edge of VD signal triggers the start of the frame readout. Row Readout Programmed Integration Integration due to Slave Mode Delay Row 0 Row N The Slave Mode will become "Active" after the last row period. Both the row reset and row read operations will wait until the rising edge of the VD signal. . Note: The integration of the last row is started before the end of the programmed integration for the first row. Figure 30. Slave Mode Example with Equal Integration and Frame Readout Periods 2. If the sensor integration time is configured to be less than the frame period, then the sensor will not have reset all of the sensor rows before it begins waiting for the input VD signal. This error can be minimized by configuring the frame period to be as close as possible to the desired frame rate (period between VD signals). The row shutter and read operations will stop when the slave mode becomes active and is waiting for the VD signal. The following should be considered when configuring the sensor to use the slave mode: 1. The frame period (TFRAME) should be configured to be less than the period of the input VD signal. The sensor will disregard the input VD signal if it appears before the frame readout is finished. Frame Valid Rising Edge Rising Edge Rising Edge VD Signal Slave Mode Trigger Inactive Active 8.33 ms 8.33 ms Row 0 Inactive Row Reset (start of integration) Active Row reset and read operations begin after the rising edge of the Vd signal. Row Readout Programmed Integration Integration due to Slave Mode Delay Row N Reset operation is held during slave mode "Active" state. Note: The sensor read pointer will have paused at row 0 while the shutter pointer pauses at row N/2. The extra integration caused by the slave mode delay will only be seen by rows 0 to N/2. The example below is for a frame readout period of 16.6 ms while the integration time is configured to 8.33 ms. Figure 31. Slave Mode Example Where the Integration Period is Half of the Frame Readout Period www.onsemi.com 30 AR0331 pulse arrives while the slave mode is inactive, the VD pulse will be ignored and will wait until the next VD pulse has arrived. To enter slave mode: 1. While in soft-standby, set R0x30CE[4] = 1 to enter slave mode 2. Enable the input pins (TRIGGER) by setting R0x301A[8] = 1 3. Enable streaming by setting R0x301A[2] = 1 4. Apply sync-pulses to the TRIGGER input When the slave mode becomes active, the sensor will pause both row read and row reset operations. (Note: The row integration period is defined as the period from row reset to row read.) The frame-time should therefore be configured so that the slave mode "wait period" is as short as possible. In the case where the sensor integration time is shorter than the frame time, the "wait period" will only increase the integration of the rows that have been reset following the last VD pulse. The period between slave mode pulses must also be greater than the frame period. If the rising edge of the VD FRAME READOUT The sensor readout begins with vertical blanking rows followed by the active rows. The frame readout period can be defined by the number of row periods within a frame (frame_length_lines) and the row period 1/60s 1/60s Row Reset (line_length_pck/clk_pix). The sensor will read the first vertical blanking row at the beginning of the frame period and the last active row at the end of the row period. Row Read Row Reset Row Read Vertical Blanking Active Rows Row Reset Time Row Read Row Reset Row Read End of Frame Readout Start of Frame Start of Active Row HB (136 Pixels/Column) 1928 x 1088 VB (37 Rows) Serial SYNC Codes Start of Vertical Blanking VB (37 Rows) End of Frame Readout HB (136Pixels/Column) 1928 x 1088 End of Line End of Frame Frame Valid Line Valid Note: The frame valid and line valid signals mentioned in this diagram represent internal signals within the sensor. The SYNC codes represented in this diagram represent the HiSPi Streaming-SP protocol. Figure 32. Example of the Sensor Output of a 1928 x 1088 Frame at 60 fps Figure 32 aligns the frame integration and readout operation to the sensor output. It also shows the sensor output using the HiSPi Streaming-SP protocol. Different sensor protocols will list different SYNC codes. www.onsemi.com 31 AR0331 Table 17. SERIAL SYNC CODES INCLUDED WITH EACH PROTOCOL INCLUDED WITH THE AR0331 SENSOR Start of Vertical Blanking Row (SOV) Interface/Protocol Parallel Start of Frame (SOF) Start of Active Line (SOL) End of Line (EOL) End of Frame (EOF) Parallel interface uses FRAME VALID (FV) and LINE VALID (LV) outputs to denote start and end of line and frame. HiSPi Streaming-S Required Unsupported Required Unsupported Unsupported HiSPi Streaming-SP Required Required Required Unsupported Unsupported HiSPi Packetized SP Unsupported Required Required Required Required Figure 33 illustrates how the sensor active readout time can be minimized while reducing the frame rate. 1125 VB rows were added to the output frame to reduce the 1928 x1088 frame rate from 60 fps to 30 fps without increasing the delay between the readout of the first and last active row. 1/30 s 1/30 s Row Reset Row Read Row Reset Row Read Vertical Blanking Active Rows Row Reset Row Read Row Reset Row Read End of Frame Readout End of Frame Readout Time Serial SYNC Codes Start of Vertical Blanking VB (37 Rows) Start of Frame 1928 x 1088 H B (1236 P ix e ls ) VB (37 Rows) 1928 x 1088 H B (1236 P ix e ls ) Start of Active Row End of Line End of Frame Frame Valid Line Valid Note: The frame valid and line valid signals mentioned in this diagram represent internal signals within the sensor. The SYNC codes represented in this diagram represent the HiSPi Streaming-SP protocol. Figure 33. Example of the Sensor Output of a 1928 x 1088 Frame at 30 fps www.onsemi.com 32 AR0331 CHANGING SENSOR MODES Register Changes bit in R0x30B0[13]. When the context switch is configured to context A the sensor will reference the context A registers. If the context switch is changed from A to B during the readout of frame n, the sensor will then reference the context B coarse_integration_time registers in frame n+1 and all other context B registers at the beginning of reading frame n+2. The sensor will show the same behavior when changing from context B to context A. All register writes are delayed by one frame. A register that is written to during the readout of frame n will not be updated to the new value until the readout of frame n+2. This includes writes to the sensor gain and integration registers. Real-Time Context Switching In the AR0331, the user may switch between two full register sets A and B by writing to a context switch change Table 18. LIST OF CONFIGURABLE REGISTERS FOR CONTEXT A AND CONTEXT B Context A Register Description Context B Address Register Description Address coarse_integration_time 0x3012 coarse_integration_time_cb 0x3016 line_length_pck 0x300C line_length_pck_cb 0x303E frame_length_lines 0x300A frame_length_lines_cb 0x30AA row_bin 0x3040[12] row_bin_cb 0x3040[10] col_bin 0x3040[13] col_bin_cb 0x3040[11] fine_gain 0x3060[3:0] fine_gain_cb 0x3060[11:8] coarse_gain 0x3060[5:4] coarse_gain_cb 0x3060[13:12] x_addr_start 0x3004 x_addr_start_cb 0x308A y_addr_start 0x3002 y_addr_start_cb 0x308C x_addr_end 0x3008 x_addr_end_cb 0x308E y_addr_end 0x3006 y_addr_end_cb 0x3090 y_odd_inc 0x30A6 y_odd_inc_cb 0x30A8 x_odd_inc 0x30A2 x_odd_inc_cb 0x30AE green1_gain 0x3056 green1_gain_cb 0x30BC blue_gain 0x3058 blue_gain_cb 0x30BE red_gain 0x305A red_gain_cb 0x30C0 green2_gain 0x305C green2_gain_cb 0x30C2 global_gain 0x305E global_gain_cb 0x30C4 operation_mode_ctrl 0x3082 operation_mode_ctrl_cb 0x3084 bypass_pix_comb 0x318E[13:12] bypass_pix_comb_cb 0x318E[15:14] www.onsemi.com 33 AR0331 1/30 s 1/60 s 1/60 s Vertical Blanking Active Rows Time Start of Frame HB (136 Pixels/Column) 1928x1088 Frame N HB (136 Pixels/Column) 1928x1088 Frame N + 1 Integration time of context Write context A to B during readout of Frame N B mode implemented during readout of frame N+1 Start of Active Row End of Frame End of Frame Readout End of Frame Readout VB (37 Rows) Start of Vertical Blanking VB (37 Rows) Serial SYNC Codes VB (37 Rows) End of Frame Readout HB (76 Pixels/Column) ) 2048x1536 Frame N + 2 Context B mode is implemented in frame N+2 Figure 34. Example of Changing the Sensor from Context A to Context B Combi Mode Compression To facilitate faster switching between linear and HDR modes, the AR0331 includes a Combi Mode feature. When enabled, Combi Mode loads a single (HDR) sequencer. When switching from HDR to linear modes, the sequencer remains the same, but only the T1 image is output. While not optimized for linear mode operation, it allows faster mode switching as a new sequencer load is not needed. Combi Mode is enabled by setting bit R0x30BA[8]. See the AR0331 Developer Guide for more information on Combi Mode. When the AR0331 is configured for linear mode operation, the sensor can optionally compress 12-bit data to 10-bit using A-law compression. The compression is applied after the data pedestal has been added to the data. See "Pedestals". The A-law compression is disabled by default and can be enabled by setting R0x31D0 from "0" to "1". Table 19. A-LAW COMPRESSION TABLE FOR 12-10 BITS Input Values Compressed Codeword Input Range 11 10 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 0 to 127 0 0 0 0 0 a b c d e f g 0 0 0 a b c d e f g 128 to 255 0 0 0 0 1 a b c d e f g 0 0 1 a b c d e f g 256 to 511 0 0 0 1 a b c d e f g X 0 1 0 a b c d e f g 512 to 1023 0 0 1 a b c d e f g X X 0 1 1 a b c d e f g 1024 to 2047 0 1 a b c d e f g h X X 1 0 a b c d e f g h 2048 to 4095 1 a b c d e f g h X X X 1 1 a b c d e f g h Temperature Sensor PTAT device characteristic response is quite linear in the temperature range of operation required, a simple linear function in the format of the equation below can be used to convert the ADC output value to the final temperature in degrees Celsius. The AR0331 sensor has a built-in PTAT-based temperature sensor, accessible through registers, that is capable of measuring die junction temperature. The temperature sensor can be enabled by writing R0x30B4[0]=1 and R0x30B4[4]=1. After this, the temperature sensor output value can be read from R0x30B2[9:0]. The value read out from the temperature sensor register is an ADC output value that needs to be converted downstream to a final temperature value in degrees Celsius. Since the Temperature + slope R0x30B2[9 : 0] ) T 0 (eq. 9) For this conversion, a minimum of two known points are needed to construct the line formula by identifying the slope and y-intercept "T0". These calibration values can be read from registers R0x30C6 and R0x30C8, which correspond to www.onsemi.com 34 AR0331 * Embedded Data: value read at 70C and 55C respectively. Once read, the slope and y-intercept values can be calculated and used in Equation 9. For more information on the temperature sensor registers, refer to the AR0331 Register Reference. * Embedded Data and Statistics The AR0331 has the capability to output image data and statistics embedded within the frame timing. There are two types of information embedded within the frame readout. If enabled, these are displayed on the two rows immediately before the first active pixel row is displayed. Embedded Statistics: If enabled, these are displayed on the two rows immediately after the last active pixel row is displayed. Register Data Image HBlank Status & Statistics Data VBlank Figure 35. Frame Format with Embedded Data Lines Enabled Embedded Data The embedded data contains the configuration of the image being displayed. This includes all register settings used to capture the current frame. The registers embedded in these rows are as follows: * Line 1: Registers R0x3000 to R0x312F * Line 2: Registers R0x3136 to R0x31BF, R0x31D0 to R0x31FF Embedded Statistics The embedded statistics contain frame identifiers and histogram information of the image in the frame. This can be used by downstream auto-exposure algorithm blocks to make decisions about exposure adjustment. This histogram is divided into 244 bins with a bin spacing of 64 evenly spaced bins for digital code values 0 to 28, 120 evenly spaced bins for values 28 to 212, 60 evenly spaced bins for values 212 to 216. In HDR with a 16x exposure ratio, this approximately corresponds to the T1 and T2 exposures respectively. The statistics found in line 2 are for backwards compatibility. It is recommended that auto exposure algorithms be developed using the histogram statistics on line 1. The first pixel of each line in the embedded statistics is a tag value of 0x0B0. This signifies that all subsequent statistics data is 10 bit data aligned to the MSB of the 12-bit pixel. Figure 36 summarizes how the embedded statistics transmission looks like. It should be noted that data, as shown in Figure 36, is aligned to the MSB of each word: NOTE: All undefined registers will have a value of 0. The format of the embedded register data transmission is defined per the embedded data section of the SMIA Function Specification. In parallel mode, since the pixel word depth is 12 bits/pixel, the sensor 16-bit register data will be transferred over 2 pixels where the register data will be broken up into 8 MSB and 8 LSB. The alignment of the 8-bit data will be on the 8 MSB bits of the 12-bit pixel word. For example, if a register value of 0x1234 is to be transmitted, it will be transmitted over two, 12-bit pixels as follows: 0x120, 0x340. www.onsemi.com 35 AR0331 statsline1 data_format_ code=8'h0B #words= 10'h1EC {2'b00,frame {2'b00,frame {2'b00,frame _countLSB} _IDMSB} _IDLSB} histogram bin0[19:10] histogram bin0[9:0] histogram bin243 [19:0] histogram bin243 [9:0] 8'h07 histBegin [9:0] histEnd [19:10] histEnd [9:0] histogram bin1 [19:0] histogram bin1[9:0] mean [19:10] mean [9:0] 8'h07 statsline2 data_format_ code=8'h0B #words= 10'h00C histBegin [19:10] lowEndMean lowEndMean perc_lowEnd perc_lowEnd norm_abs_ [19:10] [9:0] [19:10] [9:0] dev[19:10] norm_abs_ dev[9:0] 8'h07 Figure 36. Format of Embedded Statistics Output within a Frame Test Patterns The statistics embedded in these rows are as follows: The AR0331 has the capability of injecting a number of test patterns into the top of the datapath to debug the digital logic. With one of the test patterns activated, any of the datapath functions can be enabled to exercise it in a deterministic fashion. Test patterns are selected by Test_Pattern_Mode register (R0x3070). Only one of the test patterns can be enabled at a given point in time by setting the Test_Pattern_Mode register according to Table 20. When test patterns are enabled the active area will receive the value specified by the selected test pattern and the dark pixels will receive the value in Test_Pattern_Green (R0x3074 and R0x3078) for green pixels, Test_Pattern_Blue (R0x3076) for blue pixels, and Test_Pattern_Red (R0x3072) for red pixels. Line 1: * 0x0B0 - identifier * Register 0x303A - frame_count * Register 0x31D2 - frame ID * Histogram data - histogram bins 0-243 Line 2: * 0x0B0 (TAG) * Mean * Histogram Begin * Histogram End * Low End Histogram Mean * Percentage of Pixels Below Low End Mean * Normal Absolute Deviation Table 20. TEST PATTERN MODES Test_Pattern_Mode Test Pattern Output 0 No Test Pattern (Normal Operation) 1 Solid Color Test Pattern 2 100% Vertical Color Bars Test Pattern 3 Fade-to-Gray Vertical Color Bars Test Pattern 256 Walking 1s Test Pattern (12-bit) Walking 1s When the walking 1 s mode is selected, a walking 1 s pattern will be sent through the digital pipeline. The first value in each row is 1. Solid Color When the color field mode is selected, the value for each pixel is determined by its color. Green pixels will receive the value in Test_Pattern_Green, red pixels will receive the value in Test_Pattern_Red, and blue pixels will receive the value in Test_Pattern_Blue. Vertical Color Bars When the vertical color bars mode is selected, a typical color bar pattern will be sent through the digital pipeline. www.onsemi.com 36 AR0331 TWO-WIRE SERIAL REGISTER INTERFACE The two-wire serial interface bus enables read/write access to control and status registers within the AR0331. The interface protocol uses a master/slave model in which a master controls one or more slave devices. The sensor acts as a slave device. The master generates a clock (SCLK) that is an input to the sensor and is used to synchronize transfers. Data is transferred between the master and the slave on a bidirectional signal (SDATA). SDATA is pulled up to VDD_IO off-chip by a 1.5 k resistor. Either the slave or master device can drive SDATA LOW--the interface protocol determines which device is allowed to drive SDATA at any given time. The protocols described in the two-wire serial interface specification allow the slave device to drive SCLKLOW; the AR0331 uses SCLK as an input only and therefore never drives it LOW. address) and 0x21 (read address) in accordance with the specification. Alternate slave addresses of 0x30 (write address) and 0x31 (read address) can be selected by enabling and asserting the SADDR input. An alternate slave address can also be programmed through R0x31FC. Message Byte Message bytes are used for sending register addresses and register write data to the slave device and for retrieving register read data. Acknowledge Bit Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the SCLK clock period following the data transfer. The transmitter (which is the master when writing, or the slave when reading) releases SDATA. The receiver indicates an acknowledge bit by driving SDATA LOW. As for data transfers, SDATA can change when SCLK is LOW and must be stable while SCLK is HIGH. Protocol Data transfers on the two-wire serial interface bus are performed by a sequence of low-level protocol elements: 1. a (repeated) start condition 2. a slave address/data direction byte 3. an (a no) acknowledge bit 4. a message byte 5. a stop condition No-Acknowledge Bit The no-acknowledge bit is generated when the receiver does not drive SDATA LOW during the SCLK clock period following a data transfer. A no-acknowledge bit is used to terminate a read sequence. The bus is idle when both SCLK and SDATA are HIGH. Control of the bus is initiated with a start condition, and the bus is released with a stop condition. Only the master can generate the start and stop conditions. Typical Sequence A typical READ or WRITE sequence begins by the master generating a start condition on the bus. After the start condition, the master sends the 8-bit slave address/data direction byte. The last bit indicates whether the request is for a read or a write, where a "0" indicates a write and a "1" indicates a read. If the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowledge bit on the bus. If the request was a WRITE, the master then transfers the 16-bit register address to which the WRITE should take place. This transfer takes place as two 8-bit sequences and the slave sends an acknowledge bit after each sequence to indicate that the byte has been received. The master then transfers the data as an 8-bit sequence; the slave sends an acknowledge bit at the end of the sequence. The master stops writing by generating a (re)start or stop condition. If the request was a READ, the master sends the 8-bit write slave address/data direction byte and 16-bit register address, the same way as with a WRITE request. The master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, 8 bits at a time. The master generates an acknowledge bit after each 8-bit transfer. The slave's internal register address is automatically incremented after every 8 bits are transferred. The data transfer is stopped when the master sends a no-acknowledge bit. Start Condition A start condition is defined as a HIGH-to-LOW transition on SDATA while SCLK is HIGH. At the end of a transfer, the master can generate a start condition without previously generating a stop condition; this is known as a "repeated start" or "restart" condition. Stop Condition A stop condition is defined as a LOW-to-HIGH transition on SDATA while SCLK is HIGH. Data Transfer Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer mechanism is used for the slave address/data direction byte and for message bytes. One data bit is transferred during each SCLK clock period. SDATA can change when SCLK is LOW and must be stable while SCLK is HIGH. Slave Address/Data Direction Byte Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. A "0" in bit [0] indicates a WRITE, and a "1" indicates a READ. The default slave addresses used by the AR0331 are 0x20 (write www.onsemi.com 37 AR0331 Single READ from Random Location register data. The master terminates the READ by generating a no-acknowledge bit followed by a stop condition. Figure 37 shows how the internal register address maintained by the AR0331 is loaded and incremented as the sequence proceeds. This sequence (Figure 37) starts with a dummy WRITE to the 16-bit address that is to be used for the READ. The master terminates the WRITE by generating a restart condition. The master then sends the 8-bit read slave address/data direction byte and clocks out one byte of Previous Reg Address, N S Slave Address 0 A S = Start Condition P = Stop Condition Sr = Restart Condition A = Acknowledge A = No-acknowledge Reg Address[15:8] Reg Address, M Reg Address[7:0] A A Sr Slave Address 1 A M+1 Read Data A P Slave to Master Master to Slave Figure 37. Single READ from Random Location Single READ From Current Location master terminates the READ by generating a no-acknowledge bit followed by a stop condition. The figure shows two independent READ sequences. This sequence (Figure 38) performs a read using the current value of the AR0331 internal register address. The Previous Reg Address, N S Slave Address 1 A Read Data N+1 A N+2 Read Data A N+L-1 Read Data A Read Data N+L A P Figure 38. Single READ from Current Location Sequential READ, Start From Random Location has been transferred, the master generates an acknowledge bit and continues to perform byte WRITEs until "L" bytes have been written. The WRITE is terminated by the master generating a stop condition. This sequence (Figure 42) starts in the same way as the single WRITE to random location (Figure 41). Instead of generating a no-acknowledge bit after the first byte of data Previous Reg Address, N S Slave Address 0 A Reg Address[15:8] M+1 Read Data A Reg Address[7:0] M+2 A Read Data Reg Address, M M+3 A Sr Slave Address M+L-2 A Read Data 1 A M+L-1 A Read Data Figure 39. Sequential READ, Start from Random Location www.onsemi.com 38 M+1 Read Data M+L A P A AR0331 Sequential READ, Start From Current Location has been transferred, the master generates an acknowledge bit and continues to perform byte READs until "L" bytes have been read. This sequence (Figure 40) starts in the same way as the single READ from current location (Figure 38). Instead of generating a no-acknowledge bit after the first byte of data Previous Reg Address, N S Slave Address 1 A N+1 Read Data A N+2 Read Data A N+L-1 Read Data A Read Data N+L A P Figure 40. Sequential READ, Start from Current Location Single WRITE to Random Location then LOW bytes of the register address that is to be written. The master follows this with the byte of write data. The WRITE is terminated by the master generating a stop condition. This sequence (Figure 41) begins with the master generating a start condition. The slave address/data direction byte signals a WRITE and is followed by the HIGH Previous Reg Address, N S Slave Address 0 A Reg Address[15:8] A Reg Address, M Reg Address[7:0] A Write Data M+1 A P A Figure 41. Single WRITE to Random Location Sequential WRITE, Start at Random Location has been transferred, the master generates an acknowledge bit and continues to perform byte WRITEs until "L" bytes have been written. The WRITE is terminated by the master generating a stop condition. This sequence (Figure 42) starts in the same way as the single WRITE to random location (Figure 41). Instead of generating a no-acknowledge bit after the first byte of data Previous Reg Address, N S Slave Address 0 A M+1 Write Data Reg Address[15:8] A M+2 A Write Data Reg Address, M Reg Address[7:0] M+3 A Write Data M+L-2 A Write Data 39 A M+L-1 A Figure 42. Sequential WRITE, Start at Random Location www.onsemi.com M+1 Write Data M+L A A P AR0331 SPECTRAL CHARACTERISTICS 65 Red 60 G re e n 55 Blue 50 Quantum Efficiency (%) 45 40 35 30 25 20 15 10 5 0 350 450 550 650 750 850 Wavelength (nm) Figure 43. Quantum Efficiency www.onsemi.com 40 950 1050 1150 AR0331 ELECTRICAL SPECIFICATIONS Unless otherwise stated, the following specifications apply under the following conditions: * VDD = 1.8 V - 0.10/+0.15; VDD_IO = VDD_PLL = VAA = VAA_PIX = 2.8 V 0.3 V; * VDD_SLVS = 0.4 V - 0.1/+0.2; TA = -30C to +85C; output load = 10 pF; * frequency = 74.25 MHz; HiSPi off. Two-Wire Serial Register Interface The electrical characteristics of the two-wire serial register interface (SCLK, SDATA) are shown in Figure 44 and Table 21. SDATA tLOW tf tSU;DAT tr tf tHD;STA tr tBUF SCLK S tHD;STA tHD;DAT tHIGH tSU;STA tSU;STO Sr P S Note: Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register address are issued. Figure 44. Two-Wire Serial Bus Timing Parameters Table 21. TWO-WIRE SERIAL BUS CHARACTERISTICS (fEXTCLK = 27 MHz; VDD = 1.8 V; VDD_IO = 2.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V; VDD_PLL = 2.8 V; VDD_DAC = 2.8 V; TA = 25C) Standard Mode Fast Mode Symbol Min Max Min Max Unit fSCL 0 100 0 400 KHz tHD;STA 4.0 - 0.6 - S LOW Period of the SCLK Clock tLOW 4.7 - 1.3 - S HIGH Period of the SCLK Clock tHIGH 4.0 - 0.6 - S Set up Time for a Repeated START Condition tSU;STA 4.7 - 0.6 - S Data Hold Time tHD;DAT 0 (Note 4) 3.45 (Note 5) 0 (Note 6) 0.9 (Note 5) S Data Set-up Time tSU;DAT 250 - 100 (Note 6) - nS Rise Time of Both SDATA and SCLK Signals tr - 1000 20 + 0.1Cb (Note 7) 300 nS Fall Time of Both SDATA and SCLK Signals tf - 300 20 + 0.1Cb (Note 7) 300 nS tSU;STO 4.0 - 0.6 - S tBUF 4.7 - 1.3 - S Parameter SCLK Clock Frequency Hold Time (Repeated) START Condition After this period, the first clock pulse is generated Set-up Time for STOP Condition Bus Free Time between a STOP and START Condition Capacitive Load for Each bus Line Serial Interface Input pin Capacitance SDATA Max Load Capacitance SDATA Pull-up Resistor 1. 2. 3. 4. Cb - 400 - 400 pF CIN_SI - 3.3 - 3.3 pF CLOAD_SD - 30 - 30 pF RSD 1.5 4.7 1.5 4.7 K I2C This table is based on standard (v2.1 January 2000). Philips Semiconductor. Two-wire control is I2C-compatible. All values referred to VIHmin = 0.9 VDD and VILmax = 0.1 VDD levels. Sensor EXCLK = 27 MHz. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling edge of SCLK. www.onsemi.com 41 AR0331 5. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal. 6. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLK signal. If such a device does stretch the LOW period of the SCLK signal, it must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCLK line is released. 7. Cb = total capacitance of one bus line in pF. I/O Timing See Figure 45 below and Table 22 for I/O timing (AC) characteristics. By default, the AR0331 launches pixel data, FV, and LV with the rising edge of PIXCLK. The expectation is that the user captures DOUT[11:0], FV, and LV using the falling edge of PIXCLK. tR tF tRP tFP 90 % 90 % 10 % 10 % tEXTCLK EXTCLK tCP PIXCLK tPD tPD Pxl_0 Data[11:0] FRAME_VALID/ Pxl_1 Pxl_2 Pxl_n tPFH tPFL tPLH tPLL FRAME_VALID leads LINE_VALID by 6 PIXCLKs. LINE_VALID FRAME_VALID trails LINE_VALID by 6 PIXCLKs. *PLL disabled for tCP Figure 45. I/O Timing Diagram Table 22. I/O TIMING CHARACTERISTICS Symbol Definition fEXTCLK1 Input Clock Frequency tEXTCLK1 Input Clock Period t(PIX Condition Min Typ Max Unit 6 - 48 MHz 20.8 - 166 ns tR Input Clock Rise Time - 3 - ns tF Input Clock Fall Time - 3 - ns tRP Pixclk Rise Time - 4 - ns tFP Pixclk Fall Time - 4 - ns Clock Duty Cycle 40 50 60 % JITTER) tCP fPIXCLK tPD Jitter on PIXCLK - 1 EXTCLK to PIXCLK Propagation Delay Nominal voltages, PLL Disabled - 11.3 PIXCLK Frequency Default, Nominal Voltages 6 PIXCLK to Data Valid Default, Nominal Voltages - www.onsemi.com 42 2.3 ns - ns 74.25 MHz - ns AR0331 Table 22. I/O TIMING CHARACTERISTICS (continued) Symbol tPFH tPLH tPFL tPLL CLOAD CIN Definition Condition Min Typ Max Unit PIXCLK to FV HIGH Default, Nominal Voltages - 1.5 - ns PIXCLK to LV HIGH Default, Nominal Voltages - 2.3 - ns PIXCLK to FV LOW Default, Nominal Voltages - 1.5 - ns PIXCLK to LV LOW Default, Nominal Voltages - 2 - ns Output Load Capacitance - <10 - pF Input Pin Capacitance - 2.5 - pF 1. I/O timing characteristics are measured under the following conditions: - Temperature is 25C ambient - 10 pF load DC Electrical Characteristics The DC electrical characteristics are shown in the tables below. Table 23. DC ELECTRICAL CHARACTERISTICS Symbol VDD VDD_IO Definition Condition Core Digital Voltage Typ Max Unit 1.7 1.8 1.95 V 1.7/2.5 1.8/2.8 1.9/3.1 V Analog Voltage 2.5 2.8 3.1 V VAA_PIX Pixel Supply Voltage 2.5 2.8 3.1 V VDD_PLL PLL Supply Voltage 2.5 2.8 3.1 V HiSPi Supply Voltage 0.3 0.4 0.6 V VAA VDD_SLVS I/O Digital Voltage Min VIH Input HIGH Voltage VDD_IO*0.7 - - V VIL Input LOW Voltage - - VDD_IO*0.3 V IIN Input Leakage Current 20 - - A VOH Output HIGH Voltage VDD_IO-0.3 - - V VOL Output LOW Voltage - - 0.4 V IOH Output HIGH Current At Specified VOH -22 - - mA IOL Output LOW Current At Specified VOL - - 22 mA No Pull-up Resistor; VIN = VDD_IO or DGND Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. CAUTION: Stresses greater than those listed in Table 14 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied www.onsemi.com 43 AR0331 Table 24. ABSOLUTE MAXIMUM RATINGS Symbol Definition Min Max Unit VDD_MAX Core digital voltage -0.3 2.4 V VDD_IO_MAX I/O digital voltage -0.3 4 V VAA_MAX Analog voltage -0.3 4 V VAA_PIX Pixel supply voltage -0.3 4 V VDD_PLL PLL supply voltage -0.3 4 V VDD_SLVS_MAX HiSPi I/O digital voltage -0.3 2.4 V tST Storage temperature -40 85 C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Table 25. OPERATING CURRENT CONSUMPTION IN PARALLEL OUTPUT AND LINEAR MODE Definition Condition Symbol Min Typ Max Unit Digital Operating Current Streaming, 2048x1536 20 fps IDD1 - 122 137 mA I/O Digital Operating Current Streaming, 2048x1536 20 fps IDD_IO - 25 30 mA Analog Operating Current Streaming, 2048x1536 20 fps IAA - 32 38 mA Pixel Supply Current Streaming, 2048x1536 20 fps IAA_PIX - 7 12 mA PLL Supply Current Streaming, 2048x1536 20 fps IDD_PLL - 8 12 mA Digital Operating Current Streaming, 1080p30 IDD1 - 122 137 mA I/O Digital Operating Current Streaming, 1080p30 IDD_IO - 25 30 mA Analog Operating Current Streaming, 1080p30 IAA - 35 40 mA Pixel Supply Current Streaming, 1080p30 IAA_PIX - 7 12 mA PLL Supply Current Streaming, 1080p30 IDD_PLL - 8 12 mA 1. Operating currents are measured at the following conditions: VAA = VAA_PIX = VDD_PLL = 2.8 V VDD = VDD_IO = 1.8 V PLL Enabled and PIXCLK = 74.25 MHz TA = 25C Table 26. OPERATING CURRENT CONSUMPTION IN PARALLEL OUTPUT AND HDR MODE Definition Condition Symbol Min Typ Max Unit Digital Operating Current Streaming, 2048x1536 20 fps IDD - 156 173 mA I/O Digital Operating Current Streaming, 2048x1536 20 fps IDD_IO - 30 35 mA Analog Operating Current Streaming, 2048x1536 20 fps IAA - 50 65 mA Pixel Supply Current Streaming, 2048x1536 20 fps IAA_PIX - 9 14 mA PLL Supply Current Streaming, 2048x1536 20 fps IDD_PLL - 8 12 mA Digital Operating Current Streaming, 1080p30 IDD - 161 184 mA I/O Digital Operating Current Streaming, 1080p30 IDD_IO - 30 35 mA Analog Operating Current Streaming, 1080p30 IAA - 54 70 mA Pixel Supply Current Streaming, 1080p30 IAA_PIX - 9 14 mA PLL Supply Current Streaming, 1080p30 IDD_PLL - 8 12 mA 1. Operating currents are measured at the following conditions: VAA = VAA_PIX = VDD_PLL = 2.8 V VDD = VDD_IO = 1.8 V PLL Enabled and PIXCLK = 74.25 MHz PLL Enabled and PIXCLK = 74.25 MHz TA = 25C www.onsemi.com 44 AR0331 Table 27. OPERATING CURRENT IN HiSPi (HIVCM) OUTPUT AND LINEAR MODE Definition Condition Symbol Min Typ Max Unit Digital Operating Current Streaming, 2048x1536 30fps IDD - 252 278 mA Analog Operating Current Streaming, 2048x1536 30fps IAA - 27 35 mA Pixel Supply Current Streaming, 2048x1536 30fps IAA_PIX - 5 10 mA PLL Supply Current Streaming, 2048x1536 30fps IDD_PLL - 8 12 mA SLVS Supply Current Streaming, 2048x1536 30fps IDD_SLVS - 22 26 mA Digital Operating Current Streaming, 1080p60 IDD - 276 302 mA Analog Operating Current Streaming, 1080p60 IAA - 37 45 mA Pixel Supply Current Streaming, 1080p60 IAA_PIX - 7 12 mA PLL Supply Current Streaming, 1080p60 IDD_PLL - 8 12 mA SLVS Supply Current Streaming, 1080p60 IDD_SLVS - 22 26 mA 1. Operating currents are measured at the following conditions: VAA = VAA_PIX = VDD_PLL=2.8 V VDD = VDD_IO= 1.8 V VDD_SLVS = 1.8 V PLL Enabled and PIXCLK=74.25 Mhz TA = 25C Table 28. OPERATING CURRENT IN HiSPi (HIVCM) OUTPUT AND HDR MODE Definition Condition Symbol Min Typ Max Unit Digital Operating Current Streaming, 2048x1536 30fps IDD - 317 358 mA Analog Operating Current Streaming, 2048x1536 30fps IAA - 45 55 mA Pixel Supply Current Streaming, 2048x1536 30fps IAA_PIX - 8 13 mA PLL Supply Current Streaming, 2048x1536 30fps IDD_PLL - 8 12 mA SLVS Supply Current Streaming, 2048x1536 30fps IDD_SLVS - 22 26 mA Digital Operating Current Streaming, 1080p60 IDD - 323 358 mA Analog Operating Current Streaming, 1080p60 IAA - 55 70 mA Pixel Supply Current Streaming, 1080p60 IAA_PIX - 9 14 mA PLL Supply Current Streaming, 1080p60 IDD_PLL - 8 12 mA SLVS Supply Current Streaming, 1080p60 IDD_SLVS - 24 28 mA 1. Operating currents are measured at the following conditions: VAA = VAA_PIX = VDD_PLL=2.8 V VDD = VDD_IO= 1.8 V VDD_SLVS = 1.8 V PLL Enabled and PIXCLK = 74.25 MHz TA = 25C Table 29. OPERATING CURRENT IN HiSPi (SLVS) OUTPUT AND LINEAR MODE Definition Condition Symbol Min Typ Max Unit Digital Operating Current Streaming, 2048x1536 30fps IDD - 252 278 mA Analog Operating Current Streaming, 2048x1536 30fps IAA - 27 35 mA Pixel Supply Current Streaming, 2048x1536 30fps IAA_PIX - 5 10 mA PLL Supply Current Streaming, 2048x1536 30fps IDD_PLL - 8 12 mA SLVS Supply Current Streaming, 2048x1536 30fps IDD_SLVS - 9 13 mA Digital Operating Current Streaming, 1080p60 IDD - 276 302 mA Analog Operating Current Streaming, 1080p60 IAA - 37 45 mA Pixel Supply Current Streaming, 1080p60 IAA_PIX - 7 12 mA www.onsemi.com 45 AR0331 Table 29. OPERATING CURRENT IN HiSPi (SLVS) OUTPUT AND LINEAR MODE (continued) Definition Condition Symbol Min Typ Max Unit PLL Supply Current Streaming, 1080p60 IDD_PLL - 8 12 mA SLVS Supply Current Streaming, 1080p60 IDD_SLVS - 9 13 mA 1. Operating currents are measured at the following conditions: VAA = VAA_PIX= VDD_PLL=2.8 V VDD =VDD_IO= 1.8 V VDD_SLVS = 0.4 V PLL Enabled and PIXCLK=74.25 MHz TA = 25C Table 30. OPERATING CURRENT IN HiSPi (SLVS) OUTPUT AND HDR MODE Definition Condition Symbol Min Typ Max Unit Digital Operating Current Streaming, 2048x1536 30fps IDD - 317 358 mA Analog Operating Current Streaming, 2048x1536 30fps IAA - 45 55 mA Pixel Supply Current Streaming, 2048x1536 30fps IAA_PIX - 8 13 mA PLL Supply Current Streaming, 2048x1536 30fps IDD_PLL - 8 12 mA SLVS Supply Current Streaming, 2048x1536 30fps IDD_SLVS - 9 13 mA Digital Operating Current Streaming, 1080p60 IDD - 323 358 mA Analog Operating Current Streaming, 1080p60 IAA - 55 70 mA Pixel Supply Current Streaming, 1080p60 IAA_PIX - 9 14 mA PLL Supply Current Streaming, 1080p60 IDD_PLL - 8 12 mA SLVS Supply Current Streaming, 1080p60 IDD_SLVS - 9 13 mA 1. Operating currents are measured at the following conditions: VAA=VAA_PIX= VDD_PLL=2.8 V VDD = VDD_IO= 1.8 V VDD_SLVS = 0.4 V PLL Enabled and PIXCLK=74.25 MHz TA = 25C HiSPi Electrical Specifications supply in this datasheet corresponds to VDD_TX in the HiSPi Physical Layer Specification. Similarly, VDD is equivalent to VDD_HiSPi as referenced in the specification. The DLL as implemented on AR0331 is limited in the number of available delay steps and differs from the HiSPi specification as described in this section. The ON Semiconductor AR0331 sensor supports both SLVS and HiVCM HiSPi modes. Please refer to the High-Speed Serial Pixel (HiSPi) Interface Physical Layer Specification v2.00.00 for electrical definitions, specifications, and timing information. The VDD_SLVS Table 31. CHANNEL SKEW (Measurement Conditions: VDD_HiSPi = 1.8 V; VDD_HiSPi_TX = 0.8 V; Data Rate = 480 Mbps; DLL set to 0) Data Lane Skew in Reference to Clock tCHSKEW1PHY -150 ps Table 32. CLOCK DLL STEPS (Measurement Conditions: VDD_HiSPi = 1.8 V; VDD_HiSPi_TX = 0.8 V; Data DLL set to 0) Clock DLL Step 1 2 3 4 5 6 Delay at 660 Mbps 0.25 0.375 0.5 0.625 0.75 UI Eye_opening at 660 Mbps 0.85 0.78 0.71 0.71 0.69 UI 1. The Clock DLL Steps 6 and 7 are not recommended by ON Semiconductor for the AR0331. www.onsemi.com 46 AR0331 Table 33. DATA DLL STEPS (Measurement Conditions: VDD_HiSPi = 1.8 V;VDD_HiSPi_TX = 0.8 V; Data DLL set to 0) Clock DLL Step 1 2 4 6 Step Delay at 660 Mbps 0.25 0.375 0.625 0.875 UI Eye opening at 660 Mbps 0.79 0.84 0.71 0.61 UI Eye opening at 360 MHz 0.85 0.83 0.82 0.77 UI 1. The Data DLL Steps 3, 5, and 7 are not recommended by ON Semiconductor for the AR0331. POWER-ON RESET AND STANDBY TIMING Power-Up Sequence 6. After the last power supply is stable, enable EXTCLK 7. Assert RESET_BAR for at least 1 ms. The parallel interface will be tri-stated during this time 8. Wait 150000 EXTCLKs (for internal initialization into software standby 9. Configure PLL, output, and image settings to desired values 10. Wait 1ms for the PLL to lock 11. Set streaming mode (R0x301a[2] = 1) The recommended power-up sequence for the AR0331 is shown in Figure 46. The available power supplies (VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA, VAA_PIX) must have the separation specified below. 1. Turn on VDD_PLL power supply 2. After 100 s, turn on VAA and VAA_PIX power supply 3. After 100 s, turn on VDD_IO power supply 4. After 100 s, turn on VDD power supply 5. After 100 s, turn on VDD_SLVS power supply V DD _PLL (2.8) t0 V AA _PIX V AA (2.8) V DD _IO (1.8/2.8) V DD(1.8) t1 t2 t3 VDD _SLVS (0.4) EXTCLK t4 RESET_BAR tx t5 Hard Reset Internal Initialization Figure 46. Power Up www.onsemi.com 47 t6 Software Standby PLL Lock Streaming AR0331 Table 34. POWER UP SEQUENCE Definition Symbol Minimum Typical Maximum Unit VDD_PLL to VAA/VAA_PIX (Note 3) t0 0 100 - S VAA/VAA_PIX to VDD_IO t1 0 100 - S VDD_IO to VDD t2 0 100 - S VDD to VDD_SLVS t3 0 100 - S Xtal Settle Time tx - 30 (Note 1) - mS Hard Reset t4 1 (Note 2) - - mS Internal Initialization t5 150000 - - EXTCLKS PLL Lock Time t6 1 - - mS 1. Xtal settling time is component-dependent, usually taking about 10 - 100 mS. 2. Hard reset time is the minimum time required after power rails are settled. In a circuit where Hard reset is held down by RC circuit, then the RC time must include the all power rail settle time and Xtal settle time. 3. It is critical that VDD_PLL is not powered up after the other power supplies. It must be powered before or at least at the same time as the others. If the case happens that VDD_PLL is powered after other supplies then sensor may have functionality issues and will experience high current draw on this supply. Power-Down Sequence 2. The soft standby state is reached after the current row or frame, depending on configuration, has ended 3. Turn off VDD_SLVS 4. Turn off VDD 5. Turn off VDD_IO 6. Turn off VAA/VAA_PIX 7. Turn off VDD_PLL The recommended power-down sequence for the AR0331 is shown in Figure 47. The available power supplies (VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA, VAA_PIX) must have the separation specified below. 1. Disable streaming if output is active by setting standby R0x301a[2] = 0 VDD_SLVS (0.4) t0 VDD (1.8) t1 VDD_IO (1.8/2.8) t2 VAA _PIX VAA(2.8) t3 VDD _PLL (2.8) EXTCLK t4 Power Down until next Power up cycle Figure 47. Power Down www.onsemi.com 48 AR0331 Table 35. POWER DOWN SEQUENCE Definition Symbol Minimum Typical Maximum Unit VDD_SLVS to VDD t0 0 - - s VDD to VDD_IO t1 0 - - s VDD_IO to VAA/VAA_PIX t2 0 - - s VAA/VAA_PIX to VDD_PLL t3 0 - - s PwrDn until Next PwrUp Time t4 100 - - ms 1. t4 is required between power down and next power up time; all decoupling caps from regulators must be completely discharged. www.onsemi.com 49 AR0331 ILCC48 10 x 10 CASE 847AG ISSUE O www.onsemi.com 50 AR0331 IBGA63 9.5 x 9.5 CASE 503AM ISSUE O www.onsemi.com 51 AR0331 A-Pix is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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