LTC4233CWHH#PBF - LINEAR TECHNOLOGY

LTC4233

4233f

For more information www.linear.com/LTC4233

TYPICAL APPLICATION

FEATURES DESCRIPTION

10A Guaranteed SOA

Hot Swap Controller

The LT C

4233 is an integrated solution for Hot Swap™

applications that allows a board to be safely inserted and

removed from a live backplane. The part integrates a Hot

Swap controller, power MOSFET and current sense resis-

tor in a single package for small form factor applications.

The MOSFET Safe Operating Area is production tested

and guaranteed for the stresses in Hot Swap applications.

The LTC4233 provides separate inrush current control

and an 11% accurate 11.2A current limit with output

dependent foldback. The current limit threshold can be

adjusted dynamically using the ISET pin. Additional features

include a current monitor output that amplifies the sense

resistor voltage for ground referenced current sensing

and a MOSFET temperature monitor output. Thermal limit,

overvoltage, undervoltage and power good monitoring

are also provided. For a 20A pin compatible version see

LTC4234.

12V, 10A Card Resident Application with Auto-Retry

APPLICATIONS

n Allows Safe Board Insertion into a Live Backplane

n Small Footprint

n 10mΩ MOSFET Including RSENSE

n Safe Operating Area Guaranteed at 41W, 30ms

n Wide Operating Voltage Range: 2.9V to 15V

n Adjustable, 11% Accurate Current Limit

n Current and Temperature Monitor Outputs

n Overtemperature Protection

n Adjustable Current Limit Timer Before Fault

n Power Good and Fault Outputs

n Adjustable Inrush Current Control

n 2.5% Accurate Undervoltage and Overvoltage

Protection

n Available in 38-Lead (5mm × 9mm) QFN Package

n Pin Compatible with LTC4234

n High Availability Servers

n Solid State Drives

n Industrial

n Network Routers and Switches

L, LT , LT C , LT M , Linear Technology and the Linear logo are registered trademarks and Hot

Swap and PowerPath are trademarks of Linear Technology Corporation. All other trademarks are

the property of their respective owners.

Power-Up Waveforms

LTC4233

*TVS: DIODES INC. SMAJ17A

GND

VDD

F LT

SENSE–

SENSE

TIMER

INTVCC

OUT

IMON

ISET

GATE

150k

20k

107k

5.23k

10k

1µF

680µF

VOUT

12V

10A

20k

4233 TA01a

10k

ADC

12V

20ms/DIV

CONTACT

BOUNCE

VIN

10V/DIV

IIN

0.2A/DIV

VOUT

10V/DIV

4233 TA01b

LTC4233

4233f

For more information www.linear.com/LTC4233

PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS

Supply Voltage (VDD) ................................. –0.3V to 28V

Input Voltages

FB, OV, UV ..............................................–0.3V to 12V

TIMER ................................................... –0.3V to 3.5V

SENSE–, SENSE .....VDD − 10V or –0.3V to VDD + 0.3V

Output Voltages

ISET, IMON ................................................. –0.3V to 3V

PG, FLT ................................................. –0.3V to 35V

OUT ............................................ –0.3V to VDD + 0.3V

INTVCC .................................................. –0.3V to 3.5V

GATE (Note 3) ........................................ –0.3V to 33V

Operating Ambient Temperature Range

LTC4234C ................................................ 0°C to 70°C

LTC4234I .............................................–40°C to 85°C

LTC4234H .......................................... –40°C to 125°C

Junction Temperature (Note 4, 5) ......................... 150°C

Storage Temperature Range .................. –65°C to 150°C

(Notes 1, 2)

TOP VIEW

VDD

SENSE

WHH PACKAGE

38-LEAD PLASTIC QFN (5mm × 9mm)

IMON

TIMER

INTVCC

VDD (DNC)

GND

SENSE (DNC)

OUT

ISET

F LT

SENSE–

VDD (DNC)

GATE

SENSE

OUT

TJMAX = 150°C, θJA = 15°C/W

EXPOSED PAD (PINS 39 AND 40) ARE VDD AND SENSE,

θJA = 15°C/W SOLDERED, OTHERWISE θJA = 50°C/W

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC4233CWHH#PBF LTC4233CWHH#TRPBF 4233 38-Lead (5mm × 9mm) Plastic QFN 0°C to 70°C

LTC4233IWHH#PBF LTC4233IWHH#TRPBF 4233 38-Lead (5mm × 9mm) Plastic QFN –40°C to 85°C

LTC4233HWHH#PBF LTC4233HWHH#TRPBF 4233 38-Lead (5mm × 9mm) Plastic QFN –40°C to 125°C

Consult LTC Marketing for parts specified with wider operating temperature ranges.

Consult LTC Marketing for information on nonstandard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

LTC4233

4233f

For more information www.linear.com/LTC4233

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

DC Characteristics

VDD Input Supply Range l2.9 15 V

IDD Input Supply Current MOSFET On, No Load l1.6 3 mA

VDD(UVL) Input Supply Undervoltage Lockout VDD Rising l2.63 2.73 2.85 V

IOUT OUT Leakage Current VOUT = VGATE = 0V, VDD = 15V

VOUT = VGATE = 12V

±300

µA

dVGATE/dt OUT Turn-on Ramp Rate Gate Open l0.15 0.3 0.6 V/ms

RON MOSFET + Sense Resistor

On-Resistance

C-Grade, I-Grade

H-Grade

4.5

14.5

16.5

mΩ

ILIM(TH) Current Limit Threshold VFB = 1.35V, ISET Open

VFB = 0V, ISET Open

VFB = 1.35V, RSET = 20k

2.0

4.7

11.2

2.8

5.6

12.4

3.7

6.4

SOA MOSFET Safe Operating Area VDS = 13.5V, 3A Folded Back, 50W2s (Note 6)

VDS = 7.5V, 11A Onset of Foldback, 50W2s (Note 7)

Inputs

IIN OV, UV, FB Input Current V = 1.2V l0 ±1 µA

ISENSE−(IN) SENSE− Input Current VSENSE– = 12V l4 ±10 µA

VTH OV, UV, FB Threshold Voltage VPIN Rising l1.205 1.235 1.265 V

ΔVOV(HYST) OV Hysteresis l10 20 30 mV

ΔVUV(HYST) UV Hysteresis l50 80 110 mV

VUV(RTH)UV Reset Threshold Voltage VUV Falling l0.55 0.62 0.7 V

ΔVFB(HYST) FB Power Good Hysteresis l10 20 30 mV

RISET ISET Internal Resistor l19 20 21 kΩ

Outputs

VINTVCC INTVCC Output Voltage VDD = 5V,15V, ISINK = 0mA, –10mA l2.8 3.1 3.3

VOL PG, F LT Pin Output Low Voltage ISINK = 2mA l0.4 0.8 V

IOH PG , F LT Pin Input Leakage Current V = 30V l0 ±10 µA

VTIMER(H) TIMER High Threshold VTIMER Rising l1.2 1.235 1.28 V

VTIMER(L) TIMER Low Threshold VTIMER falling l0.1 0.21 0.3 V

ITIMER(UP) TIMER Pull Up Current VTIMER = 0V l–80 –100 –120 µA

ITIMER(DN) TIMER Pull Down Current VTIMER = 1.2V l1.4 2 2.6 µA

ITIMER(RATIO) TIMER Current Ratio

ITIMER(DN)/ITIMER(UP)

l1.6 2 2.7 %

AIMON IMON Current Gain l9 10 10.5 µA/A

BWIMON IMON Bandwidth 250 kHz

IOFF(IMON) IMON Offset Current IOUT = 300mA l0 ±9 µA

IGATE(UP) Gate Pull-Up Current Gate Drive On, VGATE = VOUT = 12V l–18 –24 –29 µA

IGATE(DN) Gate Pull-Down Current Gate Drive Off, VGATE = 18V, VOUT = 12V l180 250 500 µA

IGATE(FST) Gate Fast Pull-Down Current Fast Turn Off, VGATE = 18V, VOUT = 12V 140 mA

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted.

LTC4233

4233f

For more information www.linear.com/LTC4233

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted.

ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All currents into pins are positive; all voltages are referenced to

GND unless otherwise specified.

Note 3: An internal clamp limits the GATE pin to a maximum of 6.5V

above OUT. Driving this pin to voltages beyond the clamp may damage the

device.

Note 4: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 150°C when overtemperature protection is active.

Continuous operation above the specified maximum operating junction

temperature may impair device reliability.

Note 5: TJ is calculated from the ambient temperature, TA, and power

dissipation, PD, according to the formula:

TJ = TA + (PD • 15°C/W)

Note 6: SOA tested at room temperature, SOA (i.e. P2t) is reduced at

elevated temperatures according to the following formula:

P2t(TJ)=50 W2s





•150°C−TJ

150°C−25°C











Note 7: Guaranteed by design and extrapolated from P2t limit of 50W2s.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

AC Characteristics

tPHL(GATE) Input High (OV), Input Low (UV) to

GATE Low Propagation Delay

VGATE < 17.8V Falling l8 20 µs

tPHL(ILIM) Short Circuit to GATE Low VFB = 0, Step VDD − SENSE− to 50mV,

VGATE < 15V Falling

l1 5 µs

tD(ON) Turn-On Delay Step VUV to 2V, VGATE > 13V l24 48 72 ms

tD(FAULT) UV Low to Clear Fault Latch Delay 1 µs

tD(CB) Circuit Breaker Filter Delay Time

(Internal)

VFB = 0, Step VDD − SENSE– to 50mV l1.2 2 2.7 ms

tD(COOL-DOWN) Cool Down Delay (Internal) l600 900 1200 ms

LTC4233

4233f

For more information www.linear.com/LTC4233

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, VDD = 12V unless otherwise noted.

IDD vs VDD INTVCC Load Regulation

UV Low-High Threshold

vs Temperature

UV Hysteresis vs Temperature

Timer Pull-Up Current

vs Temperature

Current Limit Delay

(tPHL(ILIM) vs Overdrive)

Current Limit Threshold Foldback

Current Limit Adjustment

(IOUT vs RSET)RISET Resistor vs Temperature

VDD (V)

1.0

IDD (mA)

1.4

1.8

2.2

5 10 15 20

4233 G01

25 30

–40°C

25°C

125°C

ILOAD (mA)

0.5

1.5

1.0

INTVCC (V)

3.5

2.0

2.5

3.0

4233 G02

–14–12–10–8–6–4–2

VDD = 5V

VDD = 3.3V

TEMPERATURE (°C)

–50

UV LOW-HIGH THRESHOLD (V)

1.240

1.236

1.232

1.228

1.224

–25 0 25

4233 G03

50 75 150100 125

TEMPERATURE (°C)

–50

TIMER PULL-UP CURRENT (µA)

–110

–105

–100

–95

–90

–25 0 25

4233 G05

50 75 150100 125

OUTPUT CURRENT (A)

CURRENT PROPAGATION DELAY (µs)

1000

100

0.1

10 20 30

4233 G06

40 50 60

FB VOLTAGE (V)

CURRENT LIMIT VALUE (A)

0.2

4233 G07

0.4 0.6 1.20.8 1

>30ms SOA GUARANTEED

RSET (Ω)

CURRENT LIMIT VALUE (A)

10k

4233 G08

100k 1M 10M

TEMPERATURE (°C)

–50

ISET RESISTOR (kΩ)

–25 0 25

4233 G09

50 75 150100 125

TEMPERATURE (°C)

–50

UV HYSTERESIS (V)

0.10

0.08

0.06

0.04

–25 0 25

4233 G04

50 75 150100 125

LTC4233

4233f

For more information www.linear.com/LTC4233

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, VDD = 12V unless otherwise noted.

RON vs Temperature Guaranteed MOSFET SOA Curve

IMON vs Temperature

Gate Drive vs Gate Pull-Up

Current

PG, F LT Output Low vs ISINK

GATE Pull-Up Current

vs Temperature

Gate Drive vs VDD VISET vs Temperature

TEMPERATURE (°C)

–50

RON (mΩ)

–25 0 25

4233 G10

50 75 150100 125

VDD = 3.3V TO 12V

VDS (V)

0.1

ID (A)

100

0.1

1 10

4233 G12

100

>30ms SOA

GUARANTEED

TA = 25°C

SINGLE PULSE

3ms

30ms

CURRENT (mA)

PG, FLT VOL (V)

246

4233 G12

8 10 12

TEMPERATURE (°C)

–50

IMON (µA)

105

100

–25 0 25

4233 G13

50 75 150100 125

VDD = 3.3V, 12V

ILOAD = 10A

TEMPERATURE (°C)

–50

IGATE PULL-UP (µA)

–25.0

–24.5

–24.0

–23.5

–23.0

–25 0 25

4233 G14

50 75 150100 125

IGATE (µA)

∆VGATE (VGATE – VOUT) (V)

–5 –10 –15 –20

4233 G15

–25 –30

VDD = 12V

VDD = 3.3V

VDD (V)

6.2

6.0

5.8

5.6

5.4

5.2

5 10 15

4233 G16

20 25 30

∆VGATE (VGATE – VOUT) (V)

TEMPERATURE (°C)

–50

0.9

0.8

0.7

0.6

0.5

0.3

0.4

–25 0 25

4233 G18

50 75 150100 125

VISET (V)

JUNCTION TEMPERATURE (°C)

NORMALIZED P2t

1.0

0.4

0.2

0.8

0.6

4233 G11

75 150100 125

SOA Constant vs Junction

Temperature

LTC4233

4233f

For more information www.linear.com/LTC4233

PIN FUNCTIONS

DNC: Do Not Connect. Leave open.

FB: Foldback and Power Good Input. Connect this pin to

an external resistive divider from OUT. If the voltage falls

below 0.6V, the current limit is reduced using a foldback

profile (see the Typical Performance Characteristics sec-

tion). If the voltage falls below 1.21V, the PG pin will pull

low to indicate the power is bad

F LT : Overcurrent fault indicator. Open-drain output pulls

low when an overcurrent fault has occurred and the circuit

breaker trips. For overcurrent auto-retry tie to UV pin (see

Applications Information section for details).

GATE: Gate Drive for internal N-Channel MOSFET. An

internal 24µA current source charges the gate of the

N-channel MOSFET. At start-up the GATE pin ramps up at

a 0.35V/ms rate determined by internal circuitry. During an

undervoltage or overvoltage condition a 250µA pull-down

current turns the MOSFET off. During a short circuit or

undervoltage lockout condition, a 140mA pull-down cur-

rent source between GATE and OUT is activated.

GND: Device Ground.

IMON: Current Monitor Output. The current in the internal

MOSFET switch is divided by 100,000 and sourced from

this pin. Placing a 20k resistor on this pin allows a 0 to

2V voltage swing when current ranges from 0A to 10A.

INTVCC: Internal 3.1V Supply Decoupling Output. This pin

must have a 1µF or larger bypass capacitor. Overloading

this pin can disrupt internal operation.

ISET: Current Limit Adjustment Pin. For 11.2A current limit

value open this pin. This pin is driven by a 20k resistor

in series with a voltage source. The pin voltage is used

to generate the current limit threshold. The internal 20k

resistor (RISET) and an external resistor (RSET) between

ISET and ground create an attenuator that lowers the

current limit value. Due to circuit tolerance RSET should

not be less than 2k. In order to match the temperature

variation of the sense resistor, the voltage on this pin is

made proportional to temperature of the MOSFET switch.

OUT: Output of internal MOSFET switch. Connect this pin

directly to the load.

OV: Overvoltage Comparator Input. Connect this pin to an

external resistive divider from VDD. If the voltage at this

pin rises above 1.235V, an overvoltage is detected and

the switch turns off. Tie to GND if unused.

PG: Power good indicator. Open drain output pulls low

when the FB pin drops below 1.21V indicating the power is

bad. If the voltage at FB rises above 1.235V and the GATE

to OUT voltage exceeds 4.2V, the open-drain pull-down

releases the PG pin to go high.

SENSE: Current Sense Node and MOSFET Drain. One

exposed pad on the UH package is connected to SENSE

and should be soldered to an electrically isolated printed

circuit board trace to properly transfer the heat out of the

package. Connect the SENSE Pin 31 to the SENSE– Pin 34.

SENSE–: Current Limit and Current Monitor Amplifier

Input. The current limit circuit controls the GATE pin to

limit the voltage between the VDD and SENSE– pins to

15mV (11.2A) or less depending on the voltage at the FB

pin. This pin must be connected to SENSE pin on the right

side (connect pin 34 to pin 31).

TIMER: Current Limit Timer Input. Connect a capacitor

between this pin and ground to set a 12 ms/µF duration

for current limit before the switch is turned off. If the UV

pin is toggled low while the MOSFET switch is off, the

switch will turn on again following cool-down time of

4.14s/µF duration. Tie this pin to INTVCC for a fixed 2ms

overcurrent delay and 900ms cool-down time.

UV: Undervoltage Comparator Input. Tie high to INTVCC

if unused. Connect this pin to an external resistive divider

from VDD. If the UV pin voltage falls below 1.15V, an un-

dervoltage is detected and the switch turns off. Pulling this

pin below 0.62V resets the overcurrent fault and allows

the switch to turn back on (see Application Information

section for details). If overcurrent auto-retry is desired

then tie this pin to the FLT pin.

VDD: Supply Voltage and Current Sense Input. This ex-

posed pad must be soldered to input power. VDD has an

undervoltage lockout threshold of 2.73V.

LTC4233

4233f

For more information www.linear.com/LTC4233

FUNCTIONAL BLOCK DIAGRAM

4233 BD

VDD

(EXPOSED PAD)

OUT

GND

IMON

INTVCC

100µA

TIMER

F LT

–ISET

RISET

20k

GATESENSE

(EXPOSED PAD)

SENSE–

CLAMP

0.6V POSITIVE

TEMPERATURE

COEFFICIENT

REFERENCE

8.6mΩ

MOSFET

1.4mΩ SENSE

RESISTOR

CHARGE

PUMP

AND GATE

DRIVER

f = 2MHz

3.1V

GEN

LOGIC

INRUSHCS

0.35V/ms

6.1V

FOLDBACK

0.6V

2.65V

1.235V

+–

–

1.235V

–

0.21V

–

TM1

1.235V –

TM2

0.62V

–

RST

VDD

2.73V +

–

UVLO1

1.235V –

2µA

–

UVLO2

LTC4233

4233f

For more information www.linear.com/LTC4233

OPERATION

The Functional Block Diagram displays the main circuits

of the device. The LTC4233 is designed to turn a board’s

supply voltage on and off in a controlled manner allowing

the board to be safely inserted and removed from a live

backplane. The LTC4233 includes a 8.6mΩ MOSFET and

a 1.4mΩ current sense resistor. During normal opera-

tion, the charge pump and gate driver turn on the pass

MOSFET’s gate to provide power to the load. The inrush

current control is accomplished by the INRUSH circuit. This

circuit limits the GATE ramp rate to 0.35V/ms and hence

controls the voltage ramp rate of the output capacitor.

The current sense (CS) amplifier monitors the load current

using the voltage sensed across the current sense resistor.

The CS amplifier limits the current in the load by reduc-

ing the GATE-to-OUT voltage in an active control loop. It

is simple to adjust the current limit threshold using the

current limit adjustment (ISET) pin. This allows a different

threshold during other times such as startup. Note there

must be a connection between SENSE to SENSE− (Pin 34

to Pin 31) in order to monitor current.

A short circuit on the output to ground causes significant

power dissipation during active current limiting. To limit

this power, the foldback amplifier reduces the current

limit value from 11.2A to 2.8A in a linear manner as the

FB pin drops below 0.6V (see the Typical Performance

Characteristics).

If an overcurrent condition persists, the TIMER pin ramps

up with a 100µA current source until the pin voltage

exceeds 1.235V (comparator TM2). This indicates to the

logic that it is time to turn off the pass MOSFET to prevent

overheating. At this point the TIMER pin ramps down us-

ing the 2µA current source until the voltage drops below

0.21V (Comparator TM1) which completes one timer cycle.

After eight TIMER pin cycles (ramping to 1.235V and then

below 0.21V) the logic starts the internal 48ms timer. At

this point, the pass transistor has cooled and it is safe

to turn it on again. It is suitable in many applications to

use an internal 2ms overcurrent timer with a 900ms cool

down period. Tying the TIMER pin to INTVCC sets this

default timing. Latchoff is the normal operating condition

following overcurrent turnoff. Retry is initiated by pulling

the UV pin low for a minimum of 1µs then high. Auto-retry

is implemented by tying the F LT to the UV pin.

The output voltage is monitored using the FB pin and the

PG comparator to determine if the power is available for

the load. The power good condition is signaled by the PG

pin using an open-drain pull-down transistor.

The Functional Block Diagram shows the monitoring blocks

of the LTC4233. The two comparators on the left side

include the UV and OV comparators. These comparators

are used to determine if the external conditions are valid

prior to turning on the MOSFET. But first the undervolt-

age lockout circuits UVLO1 and UVLO2 must validate the

input supply and the internally generated 3.1V supply

(INTVCC) and generate the power up initialization to the

logic circuits. If the external conditions remain valid for

48ms the MOSFET is allowed to turn on.

Other monitoring features include MOSFET current and

temperature monitoring. The current monitor (CM) outputs

a current proportional to the sense resistor current. This

current can drive an external resistor or other circuits for

monitoring purposes. A voltage proportional to the MOS-

FET temperature is output to the ISET pin. The MOSFET is

protected by a thermal shutdown circuit.

LTC4233

4233f

For more information www.linear.com/LTC4233

The typical LTC4233 application is in a high availability

system that uses a positive voltage supply to distribute

power to individual cards. The complete application circuit

is shown in Figure 1. External component selection is

discussed in detail in the following sections.

Turn-On Sequence

Several conditions must be present before the internal

pass MOSFET can be turned on. First the supply VDD must

exceed its undervoltage lockout level. Next the internally

generated supply INTVCC must cross its 2.65V undervolt-

age threshold. This generates a 25µs power-on-reset pulse

which clears the fault register and initializes internal latches.

After the power-on-reset pulse, the UV and OV pins must

indicate that the input voltage is within the acceptable

range. All of these conditions must be satisfied for a du-

ration of 48ms to ensure that any contact bounce during

the insertion has ended.

The MOSFET is turned on by charging up the GATE with a

charge pump generated 24µA current source whose value

is adjusted by shunting a portion of the pull-up current to

ground. The charging current is controlled by the INRUSH

circuit that maintains a constant slope of GATE voltage

APPLICATIONS INFORMATION

versus time (Figure 2). The voltage at the GATE pin rises

with a slope of 0.35[V/ms] and the supply inrush current

is set at:

IINRUSH = CL • 0.35[V/ms]

This gate slope is designed to charge up a 1000µF capaci-

tor to 12V in 34ms, with an inrush current of 350mA. This

allows the inrush current to stay under the folded back

current limit threshold (2.8A) for capacitors less than 5mF.

Included in the Typical Performance Characteristics section

is a graph of the Safe Operating Area for the MOSFET. It

is evident from this graph that the power dissipation at

12V, 350mA for 34ms is in the safe region.

Figure 2. Supply Turn-On

LTC4233

GND

VDD

F LT

SENSE–

SENSE

TIMER

INTVCC

OUT

GATE

ISET

IMON

150k

20k

RGATE

100k

CGATE

0.1µF

226k

20k

140k

Z1*

*TVS Z1: DIODES INC. SMAJ17A

20k

0.1µF

330µF

VOUT

12V

RMON

20k

RSET

20k

4233 F01

10k

ADC

1µF

12V

CCOMP

3.3nF

UV = 9.88V

OV = 15.2V

PG = 10.5V

t1 t2

SLOPE = 0.35[V/ms]

GATE

OUT

VDD + 6.15V

VDD

4233 F02

Figure 1. 5A, 12V Card Resident Application

LTC4233

4233f

For more information www.linear.com/LTC4233

APPLICATIONS INFORMATION

Adding a capacitor and a 100k series resistor from GATE to

ground will lower the inrush current below the default value

set by the INRUSH circuit. The 3.3nF capacitor, CCOMP, is

necessary to compensate the current limit regulation loop

when the RGATE and CGATE network is on the GATE pin.

The GATE is charged with a 24µA current source (when

INRUSH circuit is not driving the GATE). The voltage at

the GATE pin rises with a slope equal to 24µA/CGATE and

the supply inrush current is set at:

IINRUSH=

CGATE

• 24µA

When the GATE voltage reaches the MOSFET threshold

voltage, the switch begins to turn on and the OUT volt-

age follows the GATE voltage as it increases. Once OUT

reaches VDD, the GATE will ramp up until clamped by the

6.1V Zener between GATE and OUT.

As the OUT voltage rises, so will the FB pin which is moni-

toring it. Once the FB pin crosses its 1.235V threshold

and the GATE to OUT voltage exceeds 4.2V, the PG pin

will cease to pull low and indicate that the power is good.

Parasitic MOSFET Oscillation

When the N-channel MOSFET ramps up the output during

power-up it operates as a source follower. The source fol-

lower configuration may self-oscillate in the range of 25kHz

to 300kHz when the load capacitance is less than 10µF,

especially if the wiring inductance from the supply to VDD

pin is greater than 3µH. The possibility of oscillations will

increase as the load current (during power-up) increases.

There are two ways to prevent this type of oscillation. The

simplest way is to avoid load capacitances below 10µF.

For wiring inductances larger than 20µH, the minimum

load capacitance may extend to 100µF. A second choice

is to connect an external gate capacitor CP > 1.5nF as

shown in Figure 3.

Turn-Off Sequence

The switch can be turned off by a variety of conditions. A

normal turn-off is initiated by the UV pin going below its

1.235V threshold. Additionally, several fault conditions

will turn off the switch. These include an input overvolt-

age (OV pin), overcurrent circuit breaker (SENSE pin) or

overtemperature. Normally the switch is turned off with a

250µA current pulling down the GATE pin to ground. With

the switch turned off, the OUT voltage drops which pulls

the FB pin below its threshold. The PG then pulls low to

indicate output power is no longer good.

If VDD drops below 2.65V for greater than 5µs or INTVCC

drops below 2.5V for greater than 1µs, a fast shutdown

of the switch is initiated. The GATE is pulled down with a

140mA current to the OUT pin.

Overcurrent Fault

The LTC4233 features an adjustable current limit with

foldback that protects against short-circuits and exces-

sive load current. To protect against excessive power

dissipation in the switch during active current limit, the

available current is reduced as a function of the output

voltage sensed by the FB pin. A graph in the Typical Per-

formance Characteristics curves shows the current limit

threshold foldback.

Figure 3. Compensation for Small CLOAD

4233 F03

LTC4233

OPTIONAL

RC TO LOWER

INRUSH CURRENT

GATE

2.2nF

LTC4233

4233f

For more information www.linear.com/LTC4233

APPLICATIONS INFORMATION

Figure 4. Short-Circuit Waveform

An overcurrent fault occurs when the current limit circuitry

has been engaged for longer than the timeout delay set

by the TIMER. Current limiting begins when the MOSFET

current reaches 2.8A to 11.2A (depending on the foldback).

The GATE pin is then brought down with a 140mA GATE-

to-OUT current. The voltage on the GATE is regulated in

order to limit the current to 11.2A. At this point, a circuit

breaker time delay starts by charging the external timing

capacitor with a 100µA pull-up current from the TIMER

pin. If the TIMER pin reaches its 1.235V threshold, the

internal switch turns off (with a 250µA current from

GATE to ground). Included in the Typical Performance

Characteristics curves is a graph of the Safe Operating

Area for the MOSFET. From this graph one can determine

the MOSFET’s maximum time in current limit for a given

output power.

Tying the TIMER pin to INTVCC will force the part to use

the internally generated (circuit breaker) delay of 2ms.

In either case the FLT pin is pulled low to indicate an

overcurrent fault has turned off the pass MOSFET. For a

given circuit breaker time delay, the equation for setting

the timing capacitor’s value is as follows:

CT = tCB • 0.083[µF/ms]

After the switch is turned off, the TIMER pin begins dis-

charging the timing capacitor with a 2µA pull-down cur-

rent. When the TIMER pin reaches its 0.21V threshold, it

completes one timer cycle. After eight TIMER pin cycles

(ramping to 1.235V and then below 0.21V) plus the 48ms

debounce time the switch is allowed to turn on again if the

overcurrent fault latch has been cleared. Bringing the UV

pin below 0.6V for a minimum of 1µs and then high will

clear the fault latch. If the TIMER pin is tied to INTVCC then

the switch is allowed to turn on again (after an internal

900ms cool down time plus the 48ms debounce time), if

the overcurrent fault latch is cleared.

Tying the F LT pin to the UV pin allows the part to self-clear

the fault and turn the MOSFET on as soon as TIMER pin

has ramped below 0.21V for the eighth time followed by

the 48ms debounce time. In this auto-retry mode the

LTC4233 repeatedly tries to turn on after an overcurrent

at a period determined by the capacitor on the TIMER pin.

The auto retry mode also functions when the TIMER pin

is tied to INTVCC.

The waveform in Figure 4 shows how the output latches

off following a short circuit. The current in the MOSFET

is 2.8A as the TIMER ramps up.

1ms/DIV

VOUT

10V/DIV

IOUT

2A/DIV

∆VGATE

10V/DIV

TIMER

2V/DIV

4233 F04

Current Limit Adjustment

The default value of the active current limit is 11.2A. The

current limit threshold can be adjusted lower by placing

a resistor between the ISET pin and ground. As shown in

the Functional Block Diagram the voltage at the ISET pin

(via the clamp circuit) sets the CS amplifier’s built-in offset

voltage. This offset voltage directly determines the active

current limit value. With the ISET pin open, the voltage

at the ISET pin is determined by a positive temperature

coefficient reference. This voltage is set to 0.618V which

corresponds to a 11.2A current limit at room temperature.

LTC4233

4233f

For more information www.linear.com/LTC4233

APPLICATIONS INFORMATION

An external resistor RSET placed between the ISET pin and

ground forms a resistive divider with the internal 20k RISET

sourcing resistor. The divider acts to lower the voltage at

the ISET pin and therefore lower the current limit threshold.

The overall current limit threshold precision is reduced to

±15% when using a 20k resistor to halve the threshold.

Using a switch (connected to ground) in series with RSET

allows the active current limit to change only when the

switch is closed. This feature can be used to program a

reduced running current while the maximum available

current limit is used at startup.

Monitor MOSFET Temperature

The voltage at the ISET pin increases linearly with increas-

ing temperature. The temperature profile of the ISET pin is

shown in the Typical Performance Characteristics section.

Using a comparator or ADC to measure the ISET voltage

provides an accurate indication of the MOSFET temperature.

The ISET voltage follows the formula:

ISET =

SET

RSET +RISET

• T +273°C

( )

• 2.093 mV/°C

[ ]

The MOSFET temperature is calculated using RISET of 20k.

T=RSET +20k

( )

• V

ISET

SET

• 2.093[mV/°C] −273°C

When RSET is not present, T becomes:

ISET

2.093[mV/°C] −273°C

There is an overtemperature circuit in the LTC4233 that

monitors an internal voltage similar to the ISET pin voltage.

When the die temperature exceeds 155°C the circuit turns

off the MOSFET until the temperature drops to 135°C.

Monitor MOSFET Current

The current in the MOSFET passes through an internal

1.4mΩ sense resistor. The voltage on the sense resistor is

converted to a current that is sourced out of the IMON pin.

The gain of ISENSE amplifier is 10µA/A referenced from the

MOSFET current. This output current can be converted to

a voltage using an external resistor to drive a comparator

or ADC. The voltage compliance for the IMON pin is from

0V to INTVCC − 0.7V.

A microcontroller with a built-in comparator can build a

simple integrating single-slope ADC by resetting a capaci-

tor that is charged with this current. When the capacitor

voltage trips the comparator and the capacitor is reset, a

timer is started. The time between resets will indicate the

MOSFET current.

Monitor OV and UV Faults

Protecting the load from an overvoltage condition is the

main function of the OV pin. In Figure 1 an external resis-

tive divider (driving the OV pin) connects to a comparator

to turn off the MOSFET when the VDD voltage exceeds

15.2V. If the VDD pin subsequently falls back below 14.9V,

the switch will be allowed to turn on immediately. In the

LTC4233 the OV pin threshold is 1.235V when rising, and

1.215V when falling out of overvoltage.

The UV pin functions as an undervoltage protection pin or

as an ON pin. In the Figure 1 application the MOSFET turns

off when VDD falls below 9.23V. If the VDD pin subsequently

rises above 9.88V for 48ms, the switch will be allowed to

turn on again. The LTC4233 UV turn-on/off threshold are

1.235V (rising) and 1.155V (falling).

In the case of an undervoltage or overvoltage the MOSFET

turns off and there is indication on the PG status pin. When

the overvoltage is removed, the MOSFET’s gate ramps up

immediately at the rate determined by the INRUSH circuit.

LTC4233

4233f

For more information www.linear.com/LTC4233

APPLICATIONS INFORMATION

The inrush current is defined by the current required to

charge the output capacitor using the fixed 0.35V/ms GATE

charge up rate. The inrush current is defined as:

INRUSH

• 0.35[V/ms] =

680µF • 0.35[V/ms] =240mA

As mentioned previously the charge-up time is the output

voltage (12V) divided by the output rate of 0.35V/ms

resulting in 34ms. The peak power dissipation of 12V

at 240mA (or 2.9W) must not exceed the SOA of the

pass MOSFET for 34ms (see MOSFET SOA graph in the

Typical Performance Characteristics section). On the SOA

graph the 30ms line crosses the 10V VDS vertical line at

4A. This verifies that the 40W for 30ms is safe at room

temperature. Each single point on the 3ms and 30ms lines

represent a power (voltage times current) and time that

follow a constant P2t relationship of 50W2s. If the MOSFET

junction temperature is elevated then the P2t constant

must be derated. At TJ = 60° the new constant becomes:

P2t (TJ=60°C) =

50 W2s





•150°C−60°C

150°C−25°C











=26 W2s







Power Good Indication

In addition to setting the foldback current limit threshold,

the FB pin is used to determine a power good condition.

The Figure 1 application uses an external resistive divider

on the OUT pin to drive the FB pin. On the LTC4233 the

PG comparator drives high when the FB pin rises above

1.235V and low when it falls below 1.215V.

Once the PG comparator is high the GATE pin voltage is

monitored with respect to the OUT pin. Once the GATE

minus OUT voltage exceeds 4.2V the PG pin goes high.

This indicates to the system that it is safe to load the OUT

pin while the MOSFET is completely turned on. The PG

pin goes low when the GATE is commanded off (using

the UV, OV or SENSE– pins) or when the PG comparator

drives low.

Design Example

Consider the following design example (Figure 5):

TA = 60°C, VIN = 12V, IMAX = 10A. IINRUSH = 240mA, CL =

680µF, VUVON = 9.88V, VOVOFF = 15.2V, VPGTHRESHOLD =

10.5V. A current limit fault triggers an automatic restart

of the power up sequence.

Figure 5. 10A, 12V Card Resident Application

LTC4233

GND

VDD

F LT

SENSE–

SENSE

TIMER

INTVCC

OUT

150k

20k

140k

20k

*TVS Z1: DIODES INC. SMAJ17A

226k

20k

1µF

680µF

VOUT

12V

10A

RMON

20k

4233 F05

10k

ADC

12V

Z1*

UV = 9.88V

OV = 15.2V

PG = 10.5V

ISET

IMON

GATE

LTC4233

4233f

For more information www.linear.com/LTC4233

APPLICATIONS INFORMATION

The maximum power for 34ms can be calculated from

the derated constant:

MAX =P2t(TJ=60°C)

t=26 W2s







34ms =28W

Therefore, the power dissipation at charge-up is within

the MOSFET SOA.

Next the power dissipated in the MOSFET during overcur-

rent must be limited. The active current limit uses a timer

to prevent excessive energy dissipation in the MOSFET.

The worst-case power dissipation occurs when the volt-

age versus current profile of the foldback current limit is

at the maximum. This occurs when the current is 12.4A

and the voltage is half of VIN or 6V. See the Current Limit

Threshold Foldback in the Typical Performance Charac-

teristics section to view this profile. In order to survive

74W, the MOSFET SOA dictates a maximum current limit

timeout. If the MOSFET operating temperature is elevated

prior to current limit the SOA constant must be derated

according to the formula:

P2t(TJ)=P2t(25°C) • 150°C−TJ

150°C−25°C











TJ is calculated from the ambient temperature, package

thermal impedance (θJA) and the I2R heating.

TJ = (θJA • I2 • RON) + TA = 15°C/W • (10A)2 •

14.5mΩ + 60°C = 82˚C

Using the SOA derating formula:

P2t(TJ=82°C) =50 W2s





•150°C−82°C

150°C−25°C











15 W2s









So the SOA constant is derated to 15W2s. The maximum

current limit timeout is calculated from the revised constant

and the 74W dissipated in current limit.

tMAX =P2t TJ=82°C

( )

P2=15 W2s







74W

( )

2=2.7ms

Invoke the internal 2ms timer by tying the TIMER pin to

INTVCC. To configure the LTC4233 for auto-retry after

overcurrent fault, connect the F LT to the UV pin. After the

2ms timeout the F LT pin pulls down on the UV pin restart

the power-up sequence.

The values for overvoltage, undervoltage and power good

thresholds using the resistive dividers on the UV, OV and

FB pins match the requirements of turn-on at 9.88V and

turn-off at 15.2V.

The final schematic in Figure 5 results in very few external

components. The pull-up resistor, R7, connects to the PG

pin while the 20k (RMON) converts the IMON current to a

voltage at a ratio:

VIMON = 10[µA/A] • 20k • IOUT = 0.2[V/A] • IOUT

In addition there is a 1µF bypass (C1) on the INTVCC pin

and note the connection between SENSE to SENSE− (Pin

34 to Pin 31).

LTC4233

4233f

For more information www.linear.com/LTC4233

APPLICATIONS INFORMATION

Figure 6. Recommended Layout

4233 F06

OUT

GND

VDD

VDD SENSE

Layout Considerations

In Hot Swap applications where load currents can be 10A,

narrow PCB tracks exhibit more resistance than wider tracks

and operate at elevated temperatures. The minimum trace

width requirement for 1oz copper foil is 0.02" per amp to

make sure the trace stays at a reasonable temperature.

Using 0.03" per amp or wider is recommended. Note that

1oz copper exhibits a sheet resistance of about 0.5mΩ/

square. Small resistances add up quickly in high current

applications.

The input supply should be tied to the VDD exposed pad

through a PCB trace that enters between Pin 1 and Pin 38.

The VDD pad connects to the sense resistor and MOSFET.

Globally, there are three DNC pins that are unconnected

and left open (Pins 6, 8, 33). Connect the SENSE– pin (Pin

34) to the SENSE pin (Pin 31). Figure 6 shows a recom-

mended layout for the LTC4233.

During normal operation the power dissipated in the

MOSFET could be as high as 1.5W. To remove this heat,

solder the SENSE exposed pad to a copper trace that

contains vias underneath the pad. The OUT pins also

conduct substantial heat from the MOSFET. Connect all

the OUT pins to a plane of 1oz copper. Since the trace that

connects OUT pins must accommodate high current, this

area of copper is usually present. It is also important to

put C1, the bypass capacitor for the INTVCC pin as close

as possible between INTVCC and GND.

LTC4233

4233f

For more information www.linear.com/LTC4233

Thermal Considerations

The LTC4233 junction to board temperature rise in still

air when the load current is 5A, 7.5A and 10A is shown in

curves of Figures 7 and 8. The junction temperature was

measured at the package and the board temperature was

measured at the board edge. This temperature rise falls as

the board area is increases from 6.45 cm2 to 103 cm2. Two

different SENSE pad areas are shown as separate figures.

This thermal test board uses 2oz copper on the top layer

divided equally between VDD and OUT traces similar to

Figure 6. The second layer is 1oz copper connected to

the vias to the SENSE pad on the top layer. Two versions

of the second layer are considered. One uses a minimum

APPLICATIONS INFORMATION

∆TJB (°C)

AB (cm2)

120

100

5 10 15

4233 F07

20 25 3530

5A 7.5A 10A

SMALL SENSE PAD (2ND LAYER)

∆TJB (°C)

AB (cm2)

120

100

5 10 15 20 25 3530

5A 7.5A 10A

4233 F08

LARGE SENSE PAD (2ND LAYER)

Figure 7. Temperature Rise for Small SENSE Pad Figure 8. Temperature Rise for Large SENSE Pad

sized SENSE pad that only covers the vias for the top

layer while the remainder of the second layer is empty

(see Figure 7). The other version fills the second layer

with SENSE connected copper (see Figure 8). The third

layer is 1oz copper tied to ground while the bottom layer

is 2oz copper tied to ground except for a few signal traces.

The curves demonstrate that the heat from the MOSFET

can be effectively transferred out of the package through

the OUT pins and only requires a minimum sized SENSE

pad under the package. However for small boards the

larger SENSE area does reduce the junction temperature

when sourcing higher currents.

LTC4233

4233f

For more information www.linear.com/LTC4233

APPLICATIONS INFORMATION

Additional Applications

The LTC4233 has a wide operating range from 2.9V to 15V.

The UV, OV and PG thresholds are set with few resistors.

All other functions are independent of supply voltage.

In addition to Hot Swap applications, the LTC4233 also

functions as a backplane resident switch for removable

load cards (see Figure 9).

Figure 10 shows a 3.3V application with a UV threshold

of 2.87V, an OV threshold of 3.77V and a PG threshold

of 3.05V.

The last page shows a 20A parallel application where the

two LTC4233 parts each provide 10A to the load. The

PNPs prevent one LTC4233 from faulting off in current

limit until both parts hit the 11.2A limit. The PNPs are

disconnected when power good is false via the series

MOSFETs M1 and M2.

Figure 9. 12V, 10A Backplane Resident Application with Insertion Activated Turn-On

LTC4233

GND

VDD

SENSE–

SENSE

TIMER

INTVCC

OUT

F LT

150k

20k

10k

226k

12V

20k

1µF

VOUT

12V

10A

RMON

20k

*TVS Z1: DIODES INC. SMAJ17A 4233 F09

20k R3

140k

ADC

12V

LOAD

Z1* UV = 9.88V

OV = 15.2V

PG = 10.5V

ISET

IMON

GATE

LTC4233

GND

VDD

F LT

SENSE–

SENSE

TIMER

INTVCC

OUT

14.7k

10k

3.16k

17.4k

10k

680µF

VOUT

3.3V

10A

RMON

20k

4233 F10

10k

ADC

1µF

3.3V

Z1*

*TVS Z1: DIODES INC. SMAJ17A

UV = 2.87V

OV = 3.77V

PG = 3.05V

ISET

IMON

GATE

Figure 10. 3.3V, 10A Card Resident Application with Auto-Retry

LTC4233

4233f

For more information www.linear.com/LTC4233

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

PACKAGE DESCRIPTION

WHH Package

Variation: WHH38MA

38-Lead Plastic QFN (5mm × 9mm)

(Reference LTC DWG # 05-08-1934 Rev Ø)

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

5.00 ±0.10

(2 SIDES)

PIN 1

TOP MARK

(SEE NOTE 6) 1

BOTTOM VIEW—EXPOSED PAD

3.59 ±0.10

3.59 ±0.05

4.14 ±0.10

2.93 ±0.10

4.14 ±0.05

2.93 ±0.05

9.00 ±0.10

(2 SIDES)

3.59 ±0.05

5.5 ±0.05

4.1 ±0.05

2.7 ±0.05

3.59 ±0.10

(WHH36MA) QFN 1212 REV Ø

7.50

REF

0.40 ±0.10

0.5 BSC

0.25 ±0.05

0.50 REF

1.22

REF

0.72

REF

0.203 REF

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.350 REF

0.00 – 0.05

SEATING PLANE

0.90 ±0.10

0.70 ±0.05

0.35 REF

0.5 BSC

0.7

BSC

0.9 ±0.10

7.5 REF (2 SIDES)

0.25 ±0.05

PACKAGE

OUTLINE

PIN 1 NOTCH

R = 0.30

WHH Package

Variation: WHH38MA

38-Lead Plastic QFN (5mm × 9mm)

(Reference LTC DWG # 05-08-1934 Rev Ø)

0.7 BSC

2.7 REF

NOTE:

1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

0.5 REF

1.22 REF

0.72 REF

LTC4233

4233f

For more information www.linear.com/LTC4233

 LINEAR TECHNOLOGY CORPORATION 2015

LT 0715 • PRINTED IN USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC4233

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12V, 20A Parallel Application

LTC4233

0.1µF

12V VOUT

12V

20A

TIMER

OUT

GND

ISET

IMON

GATE

*TVS Z1: DIODES INC. SMAJ17A

F LT

SENSE–

SENSE

INTVCC

107k

5.23k

10k

150k

20k

150k

20k

1000µF

100k

1µF

107k

5.23k

10k

1µF

VN2222LLG

2N5087

VN2222LLG

LTC4233

0.1µF

TIMER

OUT

VDD

ISET

IMON

GATE

4233 TA02

Z1*

GND

F LT

SENSE–

SENSE

INTVCC