This is information on a product in full production.
May 2018 DocID030396 Rev 3 1/49
A6984
36 V, 400 mA automotive synchronous step-down
switching regulator
Datasheet - production data
Features
AEC-Q100 qualified
400 mA DC output current
4.5 V to 36 V operating input voltage
Synchronous rectification
Low consumption mode or low noise mode
75 µA IQ at light load (LCM VOUT = 3.3 V)
13 µA IQ-SHTDWN
Adjustable fSW (250 kHz - 600 kHz)
Output voltage a djustable from 0.9 V
No resistor divider required for 3.3 V VOUT
VBIAS maximizes efficiency at light load
350 mA valley current limit
Constant on-time control scheme
PGOOD open collector
Thermal shutdown
Applications
Car body and ADAS applications (LCM)
Car audio and low noise applications (LNM)
Description
The A6984 is a step-down monolithic switching
regulator able to deliver up to 400 mA DC. The
output voltage adjustability ranges from 0.9 V. The
fixed 3.3 V VOUT requires no external resistor
divider. The “low consumption mode” (LCM) is
designed for applications active during car
parking, so it maximizes the ef ficiency at light load
with controlled output voltage ripple. The “low
noise mode” (L NM ) ma kes the switching
frequency almost constant over the load current
range, serving low noise application
specifications such as car audio/sensors. The
PGOOD open collector output can implement
output voltage sequencing during the power-up
phase. The synchronous rectification, designed
for high efficiency at me diu m-heavy loa d, and the
high switching frequency capability make the size
of the application compact. Pulse-by-pulse
current sensing on the low-side power elem ent
implements effective constant current protection.
The package lead finishing guarantees side
solderability, thus allowing visual inspection
during manufacturing.
Figure 1. Application schematic
VFDFPN10 4 x 4 x 1.0 mm
73
(1
73
(1
& Q) 9& Q) 9
73
*1'
73
*1'
&
Q)
&
Q)
73 9287
73 9287
5
N
5
N / X+/ X+
& X) 9& X) 9
5 05 0
8 /
3*22'
(1
9,1
9&&
)%
*1'
/;
721
9%,$6
/10
(3
73 3*22'
73 3*22'
73
9,1
73
9,1
5 0HJ5 0HJ
& X& X
$09
A6984
www.st.com
Contents A6984
2/49 DocID030396 Rev 3
Contents
1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.5 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Datasheet parameters over the temperature range . . . . . . . . . . . . . . . 10
4 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 Output voltage adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1.1 Maximum output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1.2 Leading network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2 Control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3 Optional virtual ESR network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Output voltage accuracy and optimized resistor divider. . . . . . . . . . . . . . . . . . . . . 23
4.4 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.5 Light load operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.5.1 Low noise mode (LNM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.5.2 Low consumption mode (LCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.6 Switchover feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.6.1 LCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.6.2 LNM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.7 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.8 PGOOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.9 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.10 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5 Design of the power components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.2 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
DocID030396 Rev 3 3/49
A6984 Contents
49
5.3 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.3.1 Output voltage ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.3.2 COUT specification and loop stability . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6 Application board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7 Efficiency curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.1 VFDFPN10 4 x 4 x 1.0 mm package information . . . . . . . . . . . . . . . . . . . 43
9 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Pin settings A6984
4/49 DocID030396 Rev 3
1 Pin settings
1.1 Pin connection
Figure 2. Pin connection (top view)
1.2 Pin description
3*22'
)%
721
(1
*1'
/10
9%,$6
9&&
9,1
/;
$0
Table 1. Pin description
N° Pin Description
1 PGOOD The open collector output is driven low when the FB voltage is below the VPGD L threshold
(see Table 5).
2 FB Inverting input of the error amplifier
3 TON A resistor connected between this pin and VIN sets the switching frequency.
4 EN Enable pin. A logical active high signal enables the device. Connect this pin to VIN if not used.
5 GND Power GND
6 LX Switching node
7 VIN DC input voltage
8VCC
Embedded regulator output that supp lies the main switching controller.
Connect an external 1 F capacitor for proper operation.
An integrated LDO regulates VCC = 3.3 V if VBIAS voltage is < 2.4 V.
VCC is connected to VBIAS through a MOSFET switch if VBIAS > 3.2 V and the embedded
LDO is disabled to increase the light load efficiency.
9 VBIAS Ty pically connected to the regulated output voltage. An external voltage reference can be
used to supply the analog circuitry to increase the efficiency at light load. Connect to GND if
not used.
10 LNM Connect to VCC for low noise mode (LNM) / to GND for low consumption mo de (LCM)
operation.
DocID030396 Rev 3 5/49
A6984 Pin settings
49
1.3 Maximum ratings
Stressing the device above the rating listed in Table 2: Absolute maximum ratings may
cause permanent damage to the device.
These are stress ratings only and operation of the device at these or any other conditions
above those indicated in Table 5 of this specification is not implied.
Exposure to absolute maximum rating conditions may affect device reliability.
Table 2. Absolute maximum ratings
1.4 Thermal data
Table 3. Thermal data
Symbol Description Min. Max. Unit
dVIN/dt (1)
1. Maximum slew rate should be limited as detailed in Section 5.1.
Input slew rate - 0.1 V/µs
VIN -
-0.3
38
V
LX device ON VIN + 0.3
device OFF 25
EN
see Table 1
VIN + 0.3
TON
VCC 6
VBIAS
PGOOD
VCC + 0.3FB
LNM
TJOperating temperature range -40 150
°CTSTG Storage temperature range - -55 to 150
TLEAD Lead temperature (soldering 10 sec.) - 260
IHS, ILS High-side / low-side RMS switch current - 400 mA
Symbol Parameter Value Unit
Rth JA Thermal resistance junction ambient
(device soldered on STMicroelectronics evaluation board) 50 C/W
Pin settings A6984
6/49 DocID030396 Rev 3
1.5 ESD protection
Table 4. ESD protection
Symbol Test condition Va lue Unit
ESD
HBM 2 KV
MM 200 V
CDM 500 V
DocID030396 Rev 3 7/49
A6984 Electrical characteristics
49
2 Electrical characteristics
TJ = -40 to 125 °C, VIN = VEN = 12 V, VBIAS = 3.3 V unless otherwise specified.
Table 5. Electrical characteristics
Symbol Parameter Test condition Min. Typ. Max. Unit
VIN Operating input voltage range - 4.5 36
V
VIN_UVLO UVLO thresholds
Rising edge VCC regulator
VBIAS = GND -3.1 3.8 4.5
Falling edge VCC regulator
VBIAS = GND -2.9 3.6 4.3
VOUT Fixed output voltage valley
regulation FB = VCC, no load - 3.23 3.3 3.37
VFB Adjustable output voltage
valley regulation No load - 0.88 0.9 0.92
RDSON HS High-side RDSON ISW = 0.1 A - 0.6 1 .3 2.2
RDSON LS Low-side RDSON ISW = 0.1 A - 0.4 1.0 1.9
TOFF Minimum Low-side conduction
time VIN = VEN = 4.5 V - 100 200 400 ns
Current limit and zero crossing comparator
IVY Valley current limit - -350 400 470 mA
IZCD Zero crossing current threshold - (1) 12 27 46
VCC regulator
VCC VCC voltage VFB = 1 V, VBIAS = GND - 3 3.8 4.6
V
VBIAS VBIAS falling threshold - - 2.4 2.6 2.8
VBIAS rising threshold - - 2.6 2.9 3.2
Power consumption
ISHTDWN Shutdown current from VIN EN = GND -31322A
Electrical characteristics A6984
8/49 DocID030396 Rev 3
IQ OPVIN Quiescent current from VIN
LCM - SWO
VREF < VFB < VOVP (SLEEP)
VBIAS = 3.3 V
(2) 11 26 41
A
LCM - NO SWO
VREF < VFB < VOVP (SLEEP)
VBIAS = GND
(2) 90 160 230
LNM - SWO
VREF < VFB < VOVP
VBIAS = 3.3 V -11 26 42
LNM - NO SWO
VREF < VFB < VOVP
VBIAS = GND - 200 320 440
IQ OPVBIAS Quiescent current from VBIAS
LCM - SWO
VREF < VFB < VOVP (SLEEP)
VBIAS = 3.3 V
(2) 80 150 200
LNM - SWO
VREF < VFB < VOVP
VBIAS = 3.3 V
-180 300 390
Enable
EN EN thresholds Device inhibited - 1.1 - - V
Device enabled - - - 2.6
EN hysteresis - (3) -650 - mV
Overvoltage protection
VOVP Overvoltage trip (VOVP/VREF) Rising edge 18 23 28 %
PGOOD
VPGD L Power good LOW threshold
VFB rising edge
(PGOOD high impedance) (3) -90-
%
VFB falling edge
(PGOOD low impedance) -84 88 92
VPGD H Power good HIGH threshold
Internal FB rising edge
(PGOOD low impedance)
VFB = VCC
- 118 123 128
Internal FB falling edge
(PGOOD high impedance)
VFB = VCC
(3) - 100 -
VPGOOD PGOOD open collector output
VIN > VIN_UVLO_H,
VFB=GND
4 mA sinking load -- - 0.6V
2.9 < VIN < VIN_UVLO_H
100 A sinking load -- - 0.6V
Table 5. Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
DocID030396 Rev 3 9/49
A6984 Electrical characteristics
49
Thermal shutdown
TSHDWN Thermal shutdown temperature - (3) - 150 - C
THYS Thermal shutdown hysteresis - (3) -20-C
1. Parameter tested in static condition during testing phase. Parameter value may change over dynamic application condition.
2. LCM enables SLEEP mode (part of the internal circuitry is disabled) at light load.
3. Not tested in production.
Table 5. Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
Datasheet parameters over the temperature range A6984
10/49 DocID030396 Rev 3
3 Datasheet parameters over the temperature range
100% of the population in the production flow is tested at three different ambient
temperatures (-40 °C; 25 °C, 125 °C) to guarant ee datasheet p arameters within the junction
temperature rang e (-40 °C to 125 °C).
Device operation is gua ranteed when the junction temperature is within the -4 0 °C to 150 °C
temperature range. The designer can estimate the silicon temperature increase with respect
to the ambient temperature evaluating the internal power losses generated during the
device operation.
However, the embedded thermal protection disables the switching activity to protect the
device in case the junction temperature reaches the TSHTDWN (+150 °C min) temperature.
All the datasheet parameters can be guaranteed to a maximum junction temperature of
+125 °C to avoid trigg ering the thermal shutdown pro tection duri ng the testing phase due to
self-heating.
DocID030396 Rev 3 11/49
A6984 Device description
49
4 Device description
The A6984 device is based on a “Constant On-Time” (COT) control scheme with frequency
feed-forward correction over the VIN range. As a consequen ce th e device fea tures fast load
transient response, almost constant switching frequency ope ration over the input voltage
range and simple stability control.
The switching frequency can be adjusted in the 250 kHz - 600 kHz range.
The LNM (low noise mode) impleme nts const ant PWM control to minimize the voltage ri pple
over the load range, th e LCM (low consumption mode ) pulse skipping technique to increase
the efficiency at the light load.
No external resistor divider is required to r egulate fixed 3.3 V output volt age , connecting FB
to the VCC pin and VBIAS to the re gu la te d ou tp ut voltage (see Figure 1 on page 1). An
external voltage divider implements the output voltage adjustability.
The switchover capability of the internal regulator derives a portion of the quiescent current
from an extern al voltage sour ce (VBIAS pin is typically connected to the regulated output
voltage) to maximize the efficiency at the light load.
The device main internal blocks are shown in the block diagram in Figure 6 on page 15:
The bandgap reference voltage
The on-time controller
A “pulse width modulation ” (PWM) comparator and the dr ivin g circu itr y of th e
embedded power elements
The SMPS controller block
The soft-start block to ramp the current limitation
The switchover capability of the internal regulator to supply a portion of the quiescent
current when the VBIAS pin is connected to an external output voltage
The current limitation circuit to implement the constant current protection, sensing
pulse-by-p uls e low- si de switch current.
A circuit to implement the thermal protection function
LNM pin strapping sets the LNM/LCM mode
The PG (“Power Good”) open collector output
The thermal protection circuitry
Device description A6984
12/49 DocID030396 Rev 3
Figure 3. A6984 block diagram
-("5& -084 *%&
.04
7$$
-9
50/
(&/&3"503
50/
'#
4.14
$0/530--&3
7*/
-&7&-
4)*'5&3
7#*"4
-/.
-08 4
.04
(/%
1(00%
7$$
)("5&
18.@$0.1@065
(/%
)*() 4*%&
.04
'#
4&-&$503
7#*"4
-08 4*%&
.04
7$$
7*/
7#*"4
SJTJOH UISFTIPME
45"3561 70-5"(&
7$$ (&/&3"503
7$$ JOUFSOBM SFHVMBUPS PVUQVU
7$$@&/"#-&
&/
$0.1"3"503
48*5$)
7$$
IS
45"3561 70-5"(&
"/%
7$$ (&/&3"503
MS SP QV
7$$@&/"#-&
&/
$0.1"3"503
48*5$)
&/
$0
7#*"4
DocID030396 Rev 3 13/49
A6984 Device description
49
4.1 Output voltage adjustment
No external resistor divider is required to r egulate fixed 3.3 V output volt age , connecting FB
to the VCC pin and VBIAS to the re gu la te d ou tp ut voltage (see Figure 1 on page 1). An
external voltage divider otherwise implements the output voltage adjustability.
Figure 4. Intern al vol tage divider for 3. 3 V ou tp u t voltage
The error amplifier reference voltage is 0.9 V typical.
The output voltage is adjusted accordingly with the following formula (see Figure 6):
Equation 1
4.1.1 Maximum output voltage
The constant on-time control scheme naturally requires a minimum cycle-b y-cycle off time
to sense the feedback voltage and properly driving the switching activity.
The A6984 minim u m off time, as rep or te d in Table 2 on page 5, is 300 nsec typical and
400 nsec max.
The control loop generates the pro per PWM signal to regulate the programmed output
voltage over the application condition s. Since the power losses are proportional to the
delivered output power, the duty cycle increases with the load current request.
The fixed minimum off time limit s the maximu m duty cycle, so the ma ximum output volt age,
depending on the selected switching frequency (see Section 4.2).
Figure 5 shows the worst case scenario for maximum output voltage lim itation over the input
voltage range, that happens at the maximum cur rent request and considering the upper
datasheet limit time for the minimum off time parameter.
73
(1
73
(1
& Q) 9& Q) 9
73
*1'
73
*1'
&
Q)
&
Q)
73 9287
73 9287
5
N
5
N / X+/ X+
& X) 9& X) 9
5 05 0
8 /
8 /
3*22'
(1
9,1
9&&
)%
*1'
/;
721
9%,$6
/10
(3
73 3*22'
73 3*22'
73
9,1
73
9,1
5 0HJ5 0HJ
& X
& X
$0
A6984
VOUT 0.9 1 R3
R2
-------+
=
Device description A6984
14/49 DocID030396 Rev 3
Figure 5. Maximum output voltage vs. input voltage range at ILOAD = 400 mA
4.1.2 Leading network
The small signal contribution of a simple voltage divider is:
Equation 2
A small signal capacitor in parallel to the upper resistor (see C3 in Figure 6) of the voltage
divider implements a leading network (fzero < fpole) that can improve the dynamic regulatio n
for boundary app lication conditions (high fSW / high duty cycle conve rsion) and improves the
SNR for the feedback compa rator operation, entirely coupling the high frequency output
voltage ripple without the resistive divider atte nuation.
GDIV s R2
R2R3
+
--------------------=
DocID030396 Rev 3 15/49
A6984 Device description
49
Figure 6. A6984 application circuit
Laplace transformer of the leading network:
Equation 3
where:
Equation 4
The R2, R3 compose the voltage divider. CR3 is calculated as (see Section 5.3.2: COUT
specification and loop stability on page 39 for COUT selection):
Equation 5
--
5 105 10
--
5 105 10
& 10& 10
& X)& X)
--
73
(1
73
(1
& Q) 9& Q) 9
73
*1'
73
*1'
&
Q)
&
Q)
73 9287
73 9287
5
N
5
N / X+/ X+
5
5
&
10
&
10
& X) 9& X) 9
5 05 0
5
10
5
10
--
8 /
8 /
3*22'
(1
9,1
9&&
)%
*1'
/;
721
9%,$6
/10
(3
73 9%,$6
73 9%,$6
73 3*22'
73 3*22'
73
9,1
73
9,1
5 0HJ5 0HJ
5
10
5
10
& 10
10
$0
A6984
GDIV s R2
R2R3
+
-------------------- 1sR
3CR3
+
1sR2R3
R2R3
+
-------------------- CR3
+
-----------------------------------------------------------=
fZ1
2R3CR3
-------------------------------------- =
fP1
2R2R3
R2R3
+
-------------------- CR3
---------------------------------------------------=
fZfP
CR3 28 10 3–VOUT COUT
R3
----------------------------------=
Device description A6984
16/49 DocID030396 Rev 3
4.2 Control loop
The A6984 device is based on a constant on-time control loop with frequency feed-forward
correction over the input voltage range. As a consequence the on-time generato r
compensates the input volta ge variations in order to adapt the duty cycle and so keeping the
switching frequency almost constant over the input voltage range.
The general constraint for converters based on the COT architecture is the selection of the
output capacitor with an ESR high enough to guarantee a proper output volta ge ripple for
the noiseless operation of the internal PWM comparator. The A6984 innovative control loop
otherwise supports the output ceramic capacitors with the negligible ESR.
The device generates a TON duration switching pulse as soon as the voltage ripple drops
below the valley voltage threshold.
The A6984 on-time is internally generated as shown in Figure 7.
Figure 7. TON generator
where RTON represents the e xternal resistor co nnected between the VIN and T ON pins, CINT
is the integrated capacitor, CPAR the pin parasitic capacitor of the board trace at the pin 3.
The overall contribution of the CPAR and CINT for the A6984 device soldered on the
STMicroelectronics evaluation board is 7.5 pF typical but the precise value depends on the
parasitic capacitance connected at the pin 3 (TON) that may depend on the implemented
board layouts.
As a consequence, a further fine tune of the RTON value with the direct scope measurement
is required for precise fSW adjustment accordingly with the desig ned board layout.
The ON time can be calculated as:
Equation 6
The natural feed fo rwa r d of th e ge ne r ato r in Figure 7 corrects the fixed TON time with the
input voltage to achieve almost constant switching frequency over the input voltage range.
On the other hand, the PWM comparator (see Figure 3 on page 12) in the closed loop
operation modulates the TOFF time, given the programme d TON, to compensate conversion
losses (i.e. conduction, switching, inductor losses, etc.) that are proportional to the output
current.
TON 0.9 RTON CTON
VIN
----------------------------------------------- 0.9 RTON CINT CPAR
+
VIN
-----------------------------------------------------------------------= 0.9 RTON 7.5pF
VIN
------------------------------------------------=
DocID030396 Rev 3 17/49
A6984 Device description
49
As a consequence the switching frequency slightly depends on the conversion losses:
Equation 7
where DREAL is the real du ty cycle ac co un tin g co nd uc tio n loss es:
Equation 8
RON_HS and RON_LS represent the RDSON value of the embedded power elements (see
Table 5 on page 7) and DCR the equivalent series resistor of the selected inductor.
Finally from Equation 7 and Equation 8:
Equation 9
where fSW is the desired switching frequency at a certain IOUT load current level.
Figure 8 shows the estimated fSW variation over th e load range assuming the typical
RDSON of the power element s, DCR = 420 m (see Section 6 on page 40 for details on the
selected inductor for the reference application board.) and RTON = 1 M.
fSW IOUT
DREAL IOUT
TON
----------------------------------=
DREAL IOUT
VOUT RON_LS DCR+IOUT
+
VIN RON_LS RON_HS
–IOUT
+
------------------------------------------------------------------------------------=
RTON 1
0.9
--------VIN DREAL IOUT
fSW CTON
------------------------------------------------=
Device description A6984
18/49 DocID030396 Rev 3
Figure 8. fSW variation over the load range
A general requirement for applications compatible with humid environments, is to limit the
maximum resistor value to minimize the resistor variation determined by the leakage path.
An optional extern al capacitor CTON >> (CINT + CPAR) connected as shown in Figure 9 helps
to limit the RTON value and also minimizes the fSW variation with the p.c.b. parasitic
components CPAR.
Figure 9. TON generator with optional capacitor
Figure 10, Figure 11, Figure 12, and Figure 13 show the numeric example to program the
switching frequency accordingly with the RTON, CTON pair selection.
[
[
[
[
[
[
[
[
[
[
[
I6:
721 $0
DocID030396 Rev 3 19/49
A6984 Device description
49
The eDesignSuite online tool supports the A6984 and RTON, CTON dimensioning for proper
switching frequency selection, see
http://www.st.com/content/st_com/en/support/resources/edesign.html).
Figure 10. Example to select RTON, CTON for VOUT = 1.8 V
Figure 11. Example to select RTON, CTON for VOUT = 3.3 V
Device description A6984
20/49 DocID030396 Rev 3
Figure 12. Example to select RTON, CTON for VOUT = 5 V
Figure 13. Example to select RTON, CTON for VOUT = 12 V
4.3 Optional virtual ESR network
A standard COT loop requires a high ESR output capacitor to gene rate a proper PWM
signal.
The A6984 architecture naturally supports output ceramic capacitors with the negligible
ESR generating an internal voltage ramp proportional to the inductor current to emulate
a high ESR output capacitor for the proper PWM comparator operation.
The control scheme is designed to guarante e the minimum signal for the PWM comparator
cycle-by-cycle operation with controlled duty cycle jitter, that is a natural duty cycle dithering
that helps to reduce the switching noise emission for EMC.
If required, an optional external virtual ESR network (see Figure 14 can be designed to
generate a higher signal for the PWM comparator operation and remove the duty cycle
dithering. This netw o rk requ ir es th e ext er n al voltage divider to set the output voltage and
supports the LNM and LCM device operation.
DocID030396 Rev 3 21/49
A6984 Device description
49
Figure 14. Virtual ESR network
The CDC capacitor deco uples the feedba ck DC path th rough the R COT so the output volta ge
is adjusted accordingly with Section 4.1 on page 13.
Basically the network RCOT, CCOT generates a voltage signal proportional to the inductor
current ripple and superimposed with the real partitioned output voltage that incre ases the
SNR at the input of the PWM comparator. As a consequence the PWM converter
commutation is clean, removing the duty cycle dithering.
For the purpose of the signal generated by the RCOT and CCOT the output capacitor
represents a virtual ground so the equivalent small signal circuit of the output of the virtual
ESR network is shown in Figure 15.
Figure 15. Virtual ESR equivalent circuit
9/V L/VV/'&5
)%
9/;
/
5
5
5&27
'&5
&'&
&&27
Device description A6984
22/49 DocID030396 Rev 3
The switching activity drives the inductor voltage so the small signal tran sfer function can be
calculated as:
Equation 10
Equation 10 can be simplified as follows:
Equation 11
The pole splitting is guaranteed by the condition:
Equation 12
In case:
Equation 13
Equation 10 can be simplified as:
H(s) vFB(s)
iL(s)
-------------------s L DCR+
RCOT 1
sC
COT
1
1
sC
DC
---------------------1
1
R2
------- 1
R3
-------+
----------------------+
--------------------------------------------------+
-----------------------------------------------------------------------------------+
----------------------------------------------------------------------------------------------------------- 1
sC
COT
1
1
sC
DC
---------------------1
1
R2
------- 1
R3
-------+
----------------------+
--------------------------------------------------+
-----------------------------------------------------------------------------------
1
1
R2
------- 1
R3
-------+
----------------------
1
sC
DC
---------------------1
1
R2
------- 1
R3
-------+
----------------------+
--------------------------------------------------==
H(s) vFB(s)
iL(s)
------------------ s L DCR+s
1sR
COT 1
1
R2
-------1
R3
-------+
---------------------+
CDC
+1s 1
1
R2
-------1
R3
-------1
RCOT
---------------++
------------------------------------------
CCOT
+
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CDC
1
R2
-------1
R3
-------+
---------------------==
CDC 10 CCOT
RCOT 10 R2xR3
R2R3
+
--------------------
fz1
2
-----------L
DCR
-------------=fsw«
fPL 1
2RCOT 1
1
R2
-------1
R3
-------+
---------------------+ CDC
--------------------------------------------------------------------------=fsw«
fPH 1
21
1
R2
-------1
R3
-------1
RCOT
---------------++
------------------------------------------
CCOT
----------------------------------------------------------------------------------- fsw«=
Device description A6984
24/49 DocID030396 Rev 3
As a consequence, the injected triangular volta ge ripple in the FB is:
Equation 15
that does not depend on the R2, R3, CDC, L and DCR.
A virtual ESR network able to guarantee a peak-to-peak signal higher than 20 mV at the FB
pin removes any duty cycle dithering at the switching node.
Output voltage accuracy and optimized resistor divider
The constant on-time control scheme implements valley output voltage regulation: the
internal comp arator monitors the FB volt age cycle-by-cycle a nd generates a fixed T ON pulse
if the sensed voltage drops below the internal voltag e reference (VEAFB = 0.9 V typical).
The virtual ESR network generates a signal proportional to the inductor current that is AC
coupled to the FB pin thro ugh the CDC capacitor (refer to Section 4.3 for dimensioning rules)
and superimposed on the voltage divider contri bution as shown in Figure 16.
VFBRIPPLE VIN
ILRIPPLE ESRVRT
VIN VOUT
–
RCOT CCOT
---------------------------------- VOUT
VIN
--------------1
fsw
---------==
DocID030396 Rev 3 25/49
A6984 Device description
49
Figure 16. Virtual ESR signal generation in CCM operation
!
!
!
Device description A6984
26/49 DocID030396 Rev 3
In the CCM operation, the average value for the triang ular signal in Equation 15 is:
Equation 16
so the output voltag e is calculated as:
Equation 17
that shows the average injected ripp le entered in the divider calculation.
In addition, since the virtual FB ripple dep ends on the input volt age (the switching frequency
is almost constant, see Section 4.2 on page 16) its contribution affects the average output
voltage regulation.
In the low noise mode (for LNM operation refer to Section 4.6.2 on page 32) the regulator
operates in the forced PWM over the load range so:
Equation 18
and the accuracy can be estimated as:
Equation 19
In the low consumption mode (for LCM operation refer to Section 4.6.1 on page 32) the
regulator skips pulses at light load to increase the efficiency.
VFBAVG VIN
1
2
---VIN VOUT
–
RCOT CCOT
---------------------------------- VOUT
VIN
--------------1
fsw
---------=
VOUT 0.9 VFBAVG VIN
+1R3
R2
-------+
=
VOUTMIN 0.9 VFBAVG VINMIN
+1R3
R2
-------+
=
VOUTMAX 0.9 VFBAVG VINMAX
+1R3
R2
-------+
=
VOUT LNM–1
2
---VOUT
fsw RCOT CCOT
------------------------------------------------
VINMAX VOUT
–
VINMAX
---------------------------------------VINMIN VOUT
–
VINMIN
-------------------------------------–
1R3
R2
-------+
=
DocID030396 Rev 3 27/49
A6984 Device description
49
Figure 17. Virtua l ESR signal generation in LCM operat ion at light load
In LCM operation the virtual ripple contributes to the regulated output voltage as follows:
Equation 20
since TPULSE << TBURST at zero loading cond itio n.
So the accuracy can be calculated as:
Equation 21
Equation 18, Equation 19 for the LNM and Equation 20, Equation 21 for the LCM allows
proper dimensioning of the FB voltage divider and virtual ESR contribution given the
acceptable output voltage accuracy over the application input voltage range.
& "
) & ##$
#'&$%'%%#&
($ !&
VOUTMIN 0.9 1
2
---VFBRIPPLE VIN
TPULSE
TBURST
---------------------+
1R3
R2
-------+
0.9 1 R3
R2
-------+
=
VOUTMAX 0.9 VFBAVG VINMAX
+1R3
R2
-------+
=
VOUT LCM–VFBAVG VINMAX
1R3
R2
-------+
=
Device description A6984
28/49 DocID030396 Rev 3
The eDesignSuite on-line simulation tool (see
http://www.st.com/content/st_com/en/support/resources/edesign.html) supports the design
based on the A6984 device by inserting the required electrical specifications of the final
application. The interface is based on a fully annotated and in teractive schematic and the
output provides a complete set of the analysis diagram to estimate the electrical, thermal
and efficiency per fo rmance.
Moreover, it is possible to design the optional virtual ESR network based on the output
voltage specification in terms of accuracy over the input voltage range.
4.4 Soft-start
The soft-start feature minimi ze s the inrush current and decreases the stress of the power
component s during the p ower-up phase. The A6 984 implement s the so ft-st art, clamping the
device current limitation in four different steps in 2 msec time.
During normal operation, a new soft-start cycle takes place in case of:
Thermal shutdown event
UVLO event
EN pin rising
Figure 18 shows the soft-start feature. The green trace represents the inductor current
which shows different current protection thresholds.
Figure 18. Soft-start feature with resistive load
4.5 Light load operation
The LNM pinstrapping during the power-up phase determines the light load operation.
DocID030396 Rev 3 29/49
A6984 Device description
49
4.5.1 Low noise mode (LNM)
Low noise mode implements a forced PWM operation over the different loading conditions.
The LNM features a constant switching frequency to minimize the noise in the final
application and a constant voltage ripple at fixed VIN. The regulator in steady loading
condition never skips pulses and it operates in continuous conduction mode (CCM) over the
different loading co nditions.
Figure 19. Low noise mode operation
Typical applications for LNM operation are car audio and sensors.
4.5.2 Low consumption mode (LCM)
The low consumption mode maximize s the efficiency at the light load. As soon as the output
voltage drops, the regulator generates a pulse to have the FB back in regulation. In order to
minimize the current consumption in the LCM part of the internal circuitry is disabled in the
time between bu rsts.
Device description A6984
30/49 DocID030396 Rev 3
Figure 20. LCM operation at zero load
Figure 21. LCM operation over loading condition (1 of 2)
Given the energy stored in the inductor during a burst, the voltage ripple depends on the
capacitor value:
Equation 22
VOUT RIPPLE QIL
COUT
--------------iLt dt
0
TBURST
COUT
--------------------------------------------==
DocID030396 Rev 3 31/49
A6984 Device description
49
Figure 22. LCM operation over loading condition (2 of 2)
When the load current is higher, the IRIPPLE/2 the regulator works in CCM.
Figure 23. The regulator working in CCM
Device description A6984
32/49 DocID030396 Rev 3
4.6 Switchover feature
The switchover maximizes the efficiency at the light load that is crucial for LCM applications.
The main switching controller is supplied by the VCC pin regulator
An integrated LDO regu la te s VCC = 3.3 V if VBIAS voltage is < 2.4 V.
VCC is connected to VBIAS through a MOSFET switch if VBIAS > 3.2 V and the embedded
LDO is disabled to increase the light load efficiency.
4.6.1 LCM
LCM operation satisfie s the requir ement s o f battery-powered applications where it is crucial
to increase efficiency at the light load.
In order to minimize the regulator quiescent current request from the input voltage, the
VBIAS pin can be connected to an external voltage source in the range 3 V < VBIAS < 5.5 V.
In case the VBIAS pin is connected to the regulated output voltage (VOUT), the total current
drawn from the input voltage can be calculated as:
Equation 23
where IQ OP VIN, IQ OP VBIAS are defined in Table 5: Electrical characteristics on page 7 and
A6984 is the efficiency of the conversion in the working point.
4.6.2 LNM
Equation 23 is also valid when the device works in LNM and it can boost the efficiency at
medium load since the regulator always operates in continuous conduction mode.
4.7 Overcurrent protection
The current pro tec tio n circ uit ry fe atu r es a co nstant current protection, so the device limits
the maximum cu rr en t (se e Table 5: Electrical char act er istic s on page 7) in overcu rr en t
condition.
The low-side switch pulse-b y-pulse current sensing, called “valley”, implement s the constant
current prote ct ion . In overcurrent con d itio n the internal logic keeps the low-side switch
conducting as long as the switch current is higher than the valley current threshold.
As a consequence, the maximum DC output curren t is:
Equation 24
IQ VIN IQ OP VIN 1
A6984
----------------- VBIAS
VIN
-------------- IQ OP VBIAS
+=
IMAX IVALLEY_TH IRIPPLE
2
--------------------+ IVALLEY_TH VIN VOUT
–L
------------------------------TON
+==
DocID030396 Rev 3 33/49
A6984 Device description
49
Figure 24. Constant current operation in dynamic short-circuit
Figure 25. Valley current sense implements constant current protection
Device description A6984
34/49 DocID030396 Rev 3
4.8 PGOOD
The internal circuitry monitors the regulated output voltage and keeps the PGOOD open
collector output in low impedance as long as the feedback voltage is below the VPGD L
threshold (see Table 5 on page 7).
Figure 26. PGOOD behavior during soft-start time with electronic load
The PGOOD is driven low impedance if VFB = V CC (internal voltage divid er, see Section 4.1
on page 13) and VBIAS > VPGD H threshold (see Table 5).
The VPGD H thresho ld has no effe ct on PGOOD behavior in case the exter nal voltage divid er
is being used.
4.9 Overvoltage protection
The overvoltage protection monitors the FB pin and enables the low-side MOSFET to
discharge the output capa citor if the output voltage is 20% over the nominal value. A new
soft-start takes place after the OVP event ends.
DocID030396 Rev 3 35/49
A6984 Device description
49
Figure 27. Overvoltage operation
The OVP feature is a second level pr ot ection and should neve r be trig ge re d in norma l
operating conditions if the system is properly dimensioned. In other words, the selection of
the external po w e r com p on e nts and the dy na m i c per fo rm a nc e sho u l d gu ar a nt ee an ou tp ut
voltage regulation within the overvoltage threshold even during the worst case scenario in
term of load transitions.
The protection is reliable and a lso able to operate even during normal load transitions for
a system whose dynamic performance is not in line with the load dynamic request. As
a consequence the output voltage regulation would be affected.
In Figure 27 the PGOOD output is driven in low impedance (refer to Section 4.8) as long as
the OVP event is present (V FB = VCC, that is an internal resistor divider for VOUT = 3.3 V).
4.10 Thermal shutdown
The shutdo wn block disabl es the switching activity if the junction temp erat ure is higher than
a fixed internal threshold (150 °C typical). The thermal sensing element is close to the
power elemen ts, ensuring fast an d accu ra te temperature detection. A hysteresis of
approximately 20 °C prevents the device from turning ON and OFF continuously. When the
thermal protection runs away a new soft-start cycle will take place.
Design of the power components A6984
36/49 DocID030396 Rev 3
5 Design of the power components
5.1 Input capacitor selection
The input cap acitor vo ltage r ating must be higher than the maximum input operating volt age
of the application. During the switching activity a pulsed current flows into the input capacitor
and so its RMS current capability must be selected accordingly with the application
conditions. Internal losses of the input filter depend on the ESR value, so usually low ESR
capacitors (like multilayer ceramic cap acitors) have a higher RMS current cap ability. On the
other hand, given the RMS current value, lower ESR input filter has lower losses and so
contributes to higher conversion efficiency.
The maximum RMS input current flowing through the capa citor can be calculated as:
Equation 25
Where IO is the maximum DC output current, D is the duty cycles,
is the efficiency. This
function has a maximum at D = 0.5 and, considering = 1, it is equal to IO/2.
In a specific application the range of possible du ty cycles has to be considered in order to
find out the maximum RMS input current. The maximum and minimum duty cycles can be
calculated as:
Equation 26
and
Equation 27
Where
VHIGH_SIDE and
VLOW_SIDE are the voltage drop s across the em bedded switches.
The input filter value must be dimensioned to safely handle the input RMS current and to
limit the VIN ramp-up slew-rate to 0.1 V/µs maximum.
The peak-to-peak voltage across the input filter can be calculated as:
Equation 28
In case of negligible ESR (MLCC capacitor) the equation of CIN as a function of the target
VPP can be written as follows:
IRMS IOD2D
2
---------------– D2
2
-------+=
DMAX VOUT VLOW_SIDE
+
VINMIN VLOW_SIDE VHIGH_SIDE
–+
--------------------------------------------------------------------------------------------------=
DMIN VOUT VLOW_SIDE
+
VINMAX VLOW_SIDE VHIGH_SIDE
–+
----------------------------------------------------------------------------------------------------=
VPP IO
CIN fSW
----------------------- 1D
----–
DD
----1D–+ESR IO
+=
DocID030396 Rev 3 37/49
A6984 Design of the power components
49
Equation 29
Considering this function has its maximum in D = 0.5:
Equation 30
Typically CIN is dimensioned to keep the maximum peak-to-peak volt age across the input
filter in the order of 5% VIN_MAX.
5.2 Inductor selection
The inductor current ripple flowing into the output capacitor determines the output voltage
ripple (please refer to Section 5.3: Output capacitor selection). Usually the inductor value is
selected in order to keep the cu rren t r ipple lower than 20% - 40 % of the output cu rren t ove r
the input voltage range. The inductance value can be calculated by the following equation:
Equation 31
Where TON and TOFF are the on and off time of the internal power switch. The maximum
current ripple, at fixed VOUT, is obtained at maximum TOFF that is at minimum duty cycle
(see Section 5.1 to calculate minimum duty). So fixing IL = 20% to 40% of the maximum
output current, the minimum inductanc e value can be calculated:
Equation 32
where FSW is the switching frequency 1/(TON + TOFF).
For example for VOUT = 3.3 V, VIN = 12 V, IO = 0.4 A and FSW = 600 kHz the minimum
inductance value to have IL = 30% of IO is about 33 µH.
The peak current through the inductor is given by:
Table 6. Input capacitors
Manufacture Series Size Cap value (F) Rated voltage (V)
TDK C3225X7S1H106M 1210
10 50C3216X5R1H106M 1206
Taiyo Yuden UMK325BJ106MM-T 1210
CIN IO
VPP fSW
-------------------------1D
----–
DD
----1D–+=
CIN_MIN IO
2VPP_MAX fSW
----------------------------------------------=
ILVIN VOUT
–L
------------------------------TON
VOUT
L
-------------- TOFF
==
LMIN VOUT
IMAX
---------------- 1D
MIN
–
FSW
-----------------------=
Design of the power components A6984
38/49 DocID030396 Rev 3
Equation 33
So if the inductor value decreases, the peak current (that has to be lower than the current
limit of the device) increases. The higher is the inductor value, the higher is the average
output current that can be delivered, without reaching the current limit.
In Table 7 some inductor part numbers are listed.
5.3 Output capacitor selection
5.3.1 Output voltage ripple
The triangular shape current ripple (with zero aver age value) flowing into the output
capacitor gives the output voltage ripple, that depends on the capacitor value and the
equivalen t res istiv e com p on e nt (ES R). As a conse q ue n ce th e ou tp ut capacitor has to be
selected in order to have a voltage ripple compliant with the application requirements.
The voltage ripple equation can be ca lculated as:
Equation 34
Usually the resistive component of the ripple can be neglected if the selected output
capacitor is a multilayer ceramic capacitor (MLCC).
For example with VOUT = 3.3 V, VIN = 12 V, IL = 0.12 A, fSW = 600 kHz (resulting by the
inductor value) and COUT = 4.7 F MLCC:
Equation 35
The output capacitor value has a key role to sustain the output voltage during a steep load
transient. When the load transient slew rate exceeds the system bandwidth, the output
capacitor provides the current to the load. In case the final application specifies a high slew
rate load transient, the syst em bandwidth must be maximized and the output capacitor has
to sustain the output voltage for time response shorter than the loop response time.
Table 7. Inductors
Manufacturer Series Inductor value (H) Saturation current (A)
Coilcraft LPS6225 47 to 150 0.98 to 0.39
LPS5030 10 to 47 1.4 to 0.5
ILPKIOIL
2
--------+=
VOUT ESR IMAX
IMAX
8C
OUT fSW
-------------------------------------+=
VOUT
VOUT
------------------ 1
VOUT
-------------- IMAX
8C
OUT fSW
------------------------------------- 1
3.3
--------0.12
84.7F600kHz
-------------------------------------------------
5mV
3.3
-------------= 0.15%==
DocID030396 Rev 3 39/49
A6984 Design of the power components
49
In Table 8 some capacitor series are listed.
5.3.2 COUT specification and loop stability
Output capacitor value
A minimum output capacitor value is required for the COT loop stability:
Equation 36
Equivalent series resistor (ESR)
The maximum ESR of the ou tput capacitor is:
Equation 37
Table 8. Output capacitors
Manufacturer Series Cap value (F) Rated voltage (V) ESR (m)
MURATA GRM32 22 to 100 6.3 to 25 < 5
GRM31 10 to 47 6.3 to 25 < 5
PANASONIC ECJ 10 to 22 6.3 < 5
EEFCD 10 to 68 6.3 15 to 55
SANYO TPA/B/C 100 to 470 4 to 16 40 to 80
TDK C3225 22 to 100 6.3 < 5
COUT 35
VOUT fSW
-----------------------------
ESRMAX 2.8 10 3–VOUT
Application board A6984
40/49 DocID030396 Rev 3
6 Application board
The reference evaluation board schematic is shown in Figure 28.
Figure 28. Evaluation board schematic
Table 9. Bill of material
Reference Part number Description Manufacturer
C1 CGA5L3X5R1H106K160AB 10 F - 50 V - 1206 TDK
C2 - 100 nF - 50 V - 0805 -
C4 - 470 nF - 10 V - 0603 -
C6 CGA5L1X5R1C226M160AC 22 F - 16V - 1206 TDK
L1 MSS6132-683MLC 68 H Coilcraft
R1 - 1 M - 1% - 0603 -
R4 - 1 M - 5% - 0603 -
R6 - 100 k - 5% - 0603 V -
R8 - 0 - 0603 -
U1 A6984 - ST
J1 - JUMPER - CLOSED -
J2 - JUMPER - CLOSED -
J3 - JUMPER - OPEN -
J4 - JUMPER - OPEN -
R2, R3, R5, R7, R9, C3, C5, C7, C8, C9, C10 - NOT MOUNTED -
TP1, TP2, TP3, TP4, TP5, TP6, TP7 - VBIAS, PGOOD, VIN,
VOUT, EN, GND, GND -
DocID030396 Rev 3 41/49
A6984 Application board
49
Figure 29. Top layer 4 x 4 DFN evaluation board
Figure 30. Bottom layer 4 x 4 DFN evaluation board
Efficiency curves A6984
42/49 DocID030396 Rev 3
7 Efficiency curves
Figure 31. VIN 12 V - VOUT 5 V (linear scale) Figure 32. VIN 24 V - VOUT 5 V (linear scale)
Figure 33. VIN 12 V - VOUT 3.3 V (linear scale) Figure 34. VIN 12 V - VOUT 5 V (log scale)
Figure 35. VIN 24V - VOUT 5 V (log scale) Figure 36. VIN 12 V - VOUT 3.3 V (log scale)
DocID030396 Rev 3 43/49
A6984 Efficiency curves
49
Figure 37. VIN 24 V - VOUT 3.3 V (linear scale) Figure 38. VIN 12 V - VOUT 2.5 V (linear scale)
Figure 39. VIN 24V - VOUT 2.5 V (linear scale) Figure 40. VIN 24V - VOUT 3.3 V (log scale)
Figure 41. VIN 12 V - VOUT 2.5 V (log scale) Figure 42. VIN 24 V - VOUT 2.5 V (log scale)
Package information A6984
44/49 DocID030396 Rev 3
8 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
8.1 VFDFPN10 4 x 4 x 1.0 mm package information
Figure 43. VFDFPN10 4 x 4 x 1.0 mm package outline
DocID030396 Rev 3 45/49
A6984 Package information
49
Table 10. VFDFPN10 4 x 4 x 1.0 mm package mechanical data(1), (2), (3)
1. All dimensions are in mm, angles in degrees.
2. Coplanarity applies to the exposed pad as well as the terminals. Coplanarity shall not exceed 0.08 mm.
3. Warpage shall not exceed 0.10 mm.
Symbol Dimensions (mm)
Min. Nom. Max.
A 0.80 0.85 0.90
A1 0.0 -0.05
A3 0.20 REF.
b 0.20 0.25 0.30
D 3.90 4.00 4.10
D2 3.00 3.10 3.20
e0.50 BSC
E 3.90 4.00 4.10
E2 2.15 2.25 2.35
F0.55 REF.
G 0.50 BSC
H0.25 REF.
L 0.30 0.40 0.50
L1 0.45 REF.
K 0.475 REF.
N 10
Package information A6984
46/49 DocID030396 Rev 3
Figure 44. VFDFPN10 4 x 4 x 1.0 mm package detail A
Figure 45. VFDFPN10 4 x 4 x 1.0 mm suggested package footprint
DocID030396 Rev 3 47/49
A6984 Ordering information
49
9 Ordering information
Table 11. Order codes
Part number Package Packaging
A6984 VFDFPN10 4 x 4 Tube
A6984TR VFDFPN10 4 x 4 Tape and reel
Revision history A6984
48/49 DocID030396 Rev 3
10 Revision history
Table 12. Document revision history
Date Revision Changes
02-Mar-2017 1 Initial release
19-Dec-2017 2 Added sentence between Equatio n 27 and Equatio n 28.
11-May-2018 3 Updated: Features on the cover page, Figure 15, Equation 12 and
sentence between Equation 27 and Equation 28.
Added: new item dVIN/dt and footnote on Table 2.
DocID030396 Rev 3 49/49
A6984
49
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelec tronics NV and its subsidiaries (“ST ”) reserve the right to make changes, corrections, enhance m ents, modifications, and
improvement s to ST pro ducts and/o r to this document at any time withou t notice. Purcha sers should obtain the lat est relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provis ions different from the informati on set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces informati on previously supplied in any prior vers ions of this document.
© 2018 STMicroelectronics – All rights reserved
