DS88LS120 - National Semiconductor

DS78LS120/DS88LS120

Dual Differential Line Receiver (Noise Filtering and

Fail-Safe)

General Description

The DS78LS120 and DS88LS120 are high performance,

dual differential, TTL compatible line receivers for both bal-

anced and unbalanced digital data transmission. The inputs

are compatible with EIA, Federal and MIL standards.

The line receiver will discriminate a ±200 mV input signal

over a common-mode range of ±10V and a ±300 mV signal

over a range of ±15V.

Circuit features include hysteresis and response control for

applications where controlled rise and fall times and/or high

frequency noise rejection are desirable. Threshold offset

control is provided for fail-safe detection, should the input be

open or short. Each receiver includes an optional 180Ωter-

minating resistor and the output gate contains a logic strobe

for time discrimination. The DS78LS120 is specified over a

−55˚C to +125˚C temperature range and the DS88LS120

from 0˚C to +70˚C.

Input specifications meet or exceed those of the popular

DS7820/DS8820 line receiver.

Features

nMeets EIA standards RS232-C, RS422 and RS423,

Federal Standards 1020, 1030 and MIL-188-114

nInput voltage range of ±15V (differential or

common-mode)

nSeparate strobe input for each receiver

n5k typical input impedance

nOptional 180Ωtermination resistor

n50 mV input hysteresis

n200 mV input threshold

nSeparate fail-safe mode

Connection Diagram

Dual-In-Line-Package

DS007499-1

Top View

Order Number DS88LS120N or DS88LS120M

See NS Package Number M16A or N16A

For Complete Military 883 Specifications,

see RETS Data Sheet.

Order Number DS78LS120J/883 or DS78LS120W/883

See NS Package Number J16A or W16A

February 1996

DS78LS120/DS88LS120 Dual Differential Line Receiver (Noise Filtering and Fail-Safe)

Absolute Maximum Ratings (Note 2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage 7V

Input Voltage ±25V

Strobe Voltage 7V

Output Sink Current 50 mA

Storage Temperature Range −65˚C to +150˚C

Maximum Power Dissipation (Note 1) at 25˚C

Cavity Package 1433 mV

Molded Package 1362 mW

Lead Temperature (Soldering, 4 sec) 260˚C

Operating Conditions

Min Max Units

Supply Voltage (V

) 4.5 5.5 V

Temperature (T

)

DS78LS120 −55 +125 ˚C

DS88LS120 0 +70 ˚C

Common-Mode Voltage (V

) −15 +15 V

Note 1: Derate cavity package 9.6 mW/˚C above 25˚C; derate molded pack-

age 10.9 mW/˚C above 25˚C.

Electrical Characteristics (Notes 3, 4)

Symbol Parameter Conditions Min Typ Max Units

Differential Threshold Voltage I

OUT

=−400 µA, V

OUT

≥2.5V −7V ≤V

≤7V 0.06 0.2 V

−15 ≤V

≤15V 0.06 0.3 V

Differential Threshold Voltage I

OUT

=4 mA, V

OUT

≤0.5V −7V ≤V

≤7V −0.08 −0.2 V

−15V ≤V

≤

15V −0.08 −0.3 V

Differential Threshold Voltage I

OUT

=−400 µA, V

OUT

≥2.5V −7V ≤V

≤7V 0.47 0.7 V

with Fail-Safe Offset =5V I

OUT

=4 mA, V

OUT

≤0.5V −7V ≤V

≤7V −0.2 −0.42 V

Input Resistance −15V ≤V

≤15V, 0V ≤V

≤7V 4 5 kΩ

Line Termination Resistance T

=25˚C 100 180 300 Ω

Offset Control Resistance T

=25˚C 42 56 70 kΩ

IND

Data Input Current (Unterminated) V

=10V 2 3.1 mA

=0V 0V ≤V

≤7V 0 −0.5 mA

=−10V −2 −3.1 mA

THB

Input Balance I

OUT

=−400 µA, V

OUT

≥2.5V, −7V ≤V

7V 0.1 0.4 V

(Note 6) R

=500Ω

OUT

=4 mA, V

OUT

≤0.5V, −7V ≤V

≤7V −0.1 −0.4 V

=500Ω

Logical “1” Output Voltage I

OUT

=−400 µA, V

DIFF

=1V, V

=4.5V 2.5 3 V

Logical “0” Output Voltage I

OUT

=4 mA, V

DIFF

=−1V, V

=4.5V 0.35 0.5 V

Power Supply Current V

=5.5V V

=15V 10 16 mA

DIFF

=−0.5V, (Both Receivers) V

=−15V 10 16 mA

IN (1)

Logical “1” Strobe Input Current V

STROBE

=5.5V, V

DIFF

=3V 1 100 µA

IN (0)

Logical “0” Strobe Input Current V

STROBE

=0V, V

DIFF

=−3V −290 −400 µA

Logical “1” Strobe Input Voltage V

≤0.5, I

OUT

=4mA 2.0 1.12 V

Logical “0” Strobe Input Voltage V

≥2.5V, I

OUT

,=−400 µA 1.12 0.8 V

Output Short-Circuit Current V

OUT

=0V, V

=5.5V, V

STROBE

=0V,(Note 5) −30 −100 −170 mA

Note 2: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “OperatingTemperature Range” they

are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation.

Note 3: Unless otherwise specified min/max limits apply across the −55˚C to +125˚C temperature range for the DS78LS120 and across the 0˚C to +70˚C for the

DS88LS120. All typical values are for TA=25˚C, VCC =5V and VCM =0V.

Note 4: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown

as max or min on absolute value basis.

Note 5: Only one output at a time should be shorted.

Note 6: Refer to EIA-RS422 for exact conditions.

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Switching Characteristics

=5V, T

=25˚C

Symbol Parameter Conditions Min Typ Max Units

pd0(D)

Differential Input to “0” Output 38 60 ns

pd1(D)

Differential Input to “1” Output Response Pin Open, C

=15 pF, R

=2kΩ38 60 ns

pd0(S)

Strobe Input to “0” Output 16 25 ns

pd1(S)

Strobe Input to “1” Output 12 25 ns

AC Test Circuit and Switching Time Waveforms

Application Hints

Differential and Strobe Input Signal

DS007499-3

Includes probe and test fixture capacitance

DS007499-4

Note: Optimum switching response is obtained by minimizing stray capacitance on Response Control pin (no external connection).

Balanced Data Transmission

DS007499-5

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Application Hints (Continued)

The DS78LS120/DS88LS120 may be used as a level trans-

lator to interface between ±12V MOS, ECL, TTLand CMOS.

To configure, bias either input to a voltage equal to

⁄

the

voltage of the input signal, and the other input to the driving

gate.

LINE DRIVERS

Line drivers which will interface with the DS78LS120/

DS88LS120 are listed below.

Balanced Drivers

DS26LS31: Quad RS-422 Line Driver, Dual CMOS

DS7830, DS8830: Dual TTL

DS7831, DS8831: Dual TRI-STATE TTL

DS7832, DS8832: Dual TRI-STATE TTL

DS1691A, DS3691: Quad RS-423/Dual RS-422 TTL

DS1692, DS3692: Quad RS-423/Dual TRI-STATE RS-422

TTL

DS3487: Quad TRI-STATE RS-422

Unbalanced Drivers

DS1488: Quad RS-232

DS75150: Dual RS-232

RESPONSE CONTROL AND HYSTERESIS

In unbalanced (RS-232/RS-423) applications it is recom-

mended that the rise time and fall time of the line driver be

controlled to reduce cross-talk. Elimination of switching

noise is accomplished in the DS78LS120/DS88LS120 by the

50 mV of hysteresis incorporated in the output gate. This

eliminates the oscillations which may appear in a line re-

ceiver due to the input signal slowly varying about the

threshold level for extended periods of time.

High frequency noise which is superimposed on the input

signal which may exceed 50 mV can be reduced in ampli-

tude by filtering the device input. On the DS78LS120/

DS88LS120, a high impedance response control pin in the

input amplifier is available to filter the input signal without af-

fecting the termination impedance of the transmission line.

Noise pulse width rejection vs the value of the response con-

trol capacitor is shown in

Figure 1

and

Figure 2

. This combi-

nation of filters followed by hysteresis will optimize perfor-

mance in a worse case noise environment.

Unbalanced Data Transmission

DS007499-6

DS007499-7

Logic Level Translator

DS007499-8

DS007499-9

FIGURE 1. Noise Pulse Width vs

Response Control Capacitor

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Application Hints (Continued)

TRANSMISSION LINE TERMINATION

On a transmission line which is electrically long, it is advis-

able to terminate the line in its characteristic impedance to

prevent signal reflection and its associated noise/cross-talk.

A 180Ωtermination resistor is provided in the DS78LS120/

DS88LS120 line receiver. To use the termination resistor,

connect pins 2 and 3 together and pins 13 and 14 together.

The 180Ωresistor provides a good compromise between

line reflections, power dissipation in the driver, and IR drop in

the transmission line. If power dissipation and IR drop are

still a concern, a capacitor may be connected in series with

the resistor to minimize power loss.

The value of the capacitor is recommended to be the line

length (time) divided by 3 times the resistor value. Example:

if the transmission line is 1,000 feet long, (approximately

1000 ns), and the termination resistor value is 180Ω, the ca-

pacitor value should be 1852 pF. For additional application

details, refer to application notes AN-22 and AN-108.

FAIL-SAFE OPERATION

Communication systems require elements of a system to de-

tect the presence of signals in the transmission lines, and it

is desirable to have the system shut-down in a fail-safe

mode if the transmission line is open or shorted. To facilitate

the detection of input opens or shorts, the DS78LS120/

DS88LS120 incorporates an input threshold voltage offset.

This feature will force the line receiver to a specific logic

state if presence of either fault is a condition.

Given that the receiver input threshold is ±200 mV, an input

signal greater than ±200 mV insures the receiver will be in a

specific logic state. When the offset control input (pins 1 and

15) is connected to V

=5V, the input thresholds are offset

from 200 mV to 700 mV, referred to the non-inverting input,

or −200 mV to −700 mV, referred to the inverting input.

Therefore, if the input is open or shorted, the input will be

greater than the input threshold and the receiver will remain

in a specified logic state.

The input circuit of the receiver consists of a 5k resistor ter-

minated to ground through 120Ωon both inputs. This net-

work acts as an attenuator, and permits operation with

common-mode input voltages greater than ±15V. The offset

control input is actually another input to the attenuator, but its

resistor value is 56k. The offset control input is connected to

the inverting input side of the attenuator, and the input volt-

age to the amplifier is the sum of the inverting input plus 0.09

times the voltage on the offset control input. When the offset

control input is connected to 5V the input amplifier will see

IN(INVERTING)

+0.45V or V

IN(INVERTING)

+0.9V when the con-

trol input is connected to 10V. The offset control input will not

significantly affect the differential performance of the re-

ceiver over its common-mode operating range, and will not

change the input impedance balance of the receiver.

It is recommended that the receiver be terminated (500Ωor

less) to insure it will detect an open circuit in the presence of

noise.

The offset control can be used to insure fail-safe operation

for unbalanced interface (RS-423) or for balanced interface

(RS-422) operation.

For unbalanced operation, the receiver would be in an inde-

terminate logic state if the offset control input was open.

Connecting the fail-safe offset pin to 5V, offsets the receiver

threshold to 0.45V. The output is forced to a logic zero state

if the input is open or shorted.

DS007499-10

FIGURE 2.

Unbalanced RS-423 and RS-232 Fail-Safe

DS007499-11

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Application Hints (Continued)

For balanced operation with inputs open or shorted, receiver

C will be in an indeterminate logic state. Receivers A and B

will be in a logic zero state allowing the NOR gate to detect

the open or short condition. The strobe will disable receivers

A and B and may therefore be used to sample the fail-safe

detector.Another method of fail-safe detection consists of fil-

tering the output of NOR gate D so it would not indicate a

fault condition when receiver inputs pass through the thresh-

old region, generating an output transient.

In a communications system, only the control signals are re-

quired to detect input fault conditions. Advantages of a bal-

anced data transmission system over an unbalanced trans-

mission system are:

1. High noise immunity

2. High data ratio

3. Long line lengths

DS007499-12

Balanced RS-422 Fail-Safe

DS007499-13

DS007499-14

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Application Hints (Continued)

(For Balanced Fail-Safe)

Input Strobe A-Out B-Out C-Out D-Out

0 1 0100

1 1 1010

X 1 00X1

0 0 1100

1 0 1100

X 0 1100

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Schematic Diagram

DS007499-2

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Physical Dimensions inches (millimeters) unless otherwise noted

Ceramic Dual-In-Line Package (J)

Order Number DS78LS120J

NS Package Number J16A

16-Lead Molded Package Small Outline (M)

Order Number DS88LS120M

NS Package Number M16A

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Molded Dual-In-Line Package (N)

Order Number DS88LS120N

NS Package Number N16A

Ceramic Dual-In-Line Package (W)

Order Number DS78LS120W/883

NS Package Number W16A

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Notes

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COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

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systems which, (a) are intended for surgical implant

into the body, or (b) support or sustain life, and

whose failure to perform when properly used in

accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a

significant injury to the user.

2. A critical component is any component of a life

support device or system whose failure to perform

can be reasonably expected to cause the failure of

the life support device or system, or to affect its

safety or effectiveness.

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www.national.com

DS78LS120/DS88LS120 Dual Differential Line Receiver (Noise Filtering and Fail-Safe)

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.