Fractional-N Frequency Synthesizer
Data Sheet
ADF4153A
Rev. A Document Feedback
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FEATURES
RF bandwidth to 4 GHz
2.7 V to 3.3 V power supply
Separate VP allows extended tuning voltage
Programmable fractional modulus
Programmable charge pump current
3-wire serial interface
Analog and digital lock detect
Power-down mode
Pin-compatible with ADF4106, ADF4110/ADF4111/
ADF4112/ADF4113, and ADF4153
Consistent RF output phase
Loop filter design possible with ADIsimPLL
APPLICATIONS
CATV equipment
Base stations for mobile radio (GSM, PCS, DCS, WiMAX,
SuperCell 3G, CDMA, W-CDMA)
Wireless handsets (GSM, PCS, DCS, CDMA, W-CDMA)
Wireless LANs, PMR
Communications test equipment
GENERAL DESCRIPTION
The ADF4153A is a fractional-N frequency synthesizer
that implements local oscillators in the upconversion and
downconversion sections of wireless receivers and transmit-
ters. It consists of a low noise digital phase frequency detector
(PFD), a precision charge pump, and a programmable reference
divider. A sigma-delta (Σ-Δ) based fractional interpolator
allows programmable fractional-N division. The INT, FRAC,
and MOD registers define an overall N divider (N = (INT +
(FRAC/MOD))). In addition, the 4-bit reference counter (R
counter) allows selectable REFIN frequencies at the PFD input.
A complete phase-locked loop (PLL) can be implemented if the
synthesizer is used with an external loop filter and a voltage
controlled oscillator (VCO).
A simple 3-wire interface controls all on-chip registers.
The device operates with a power supply ranging from
2.7 V to 3.3 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
LOCK
DETECT
N-COUNTER
CP
RFCP3 RFCP2 RFCP1
REFERENCE
DATA
LE
24-BIT
DATA
REGISTER
CLK
REF
IN
AV
DD
AGND
V
DD
V
DD
DGND
R
DIV
N
DIV
DGND CPGND
DV
DD
V
P
SDV
DD
R
SET
RF
IN
A
RF
IN
B
OUTPUT
MUX
+
HIGH-Z
PHASE
FREQUENCY
DETECTOR
ADF4153A
THIRD ORDE R
FRACTIONAL
INTERPOLATOR
MO DULUS
REG
FRACTION
REG INTEGER
REG
CURRENT
SETTING
×2
DOUBLER 4-BIT
R COUNTER
CHARGE
PUMP
MUXOUT
11047-001
Figure 1.
ADF4153A* PRODUCT PAGE QUICK LINKS
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EVALUATION KITS
ADF4153A Evaluation Board
DOCUMENTATION
Data Sheet
ADF4153A: Fractional-N Frequency Synthesizer Data
Sheet
User Guides
UG-485: Evaluation Board for the ADF4153A Fractional-N
PLL Frequency Synthesizer
REFERENCE MATERIALS
Press
Analog Devices’ 4-GHz PLL Synthesizer Offers Leading
Phase Noise Performance
Product Selection Guide
RF Source Booklet
DESIGN RESOURCES
ADF4153A Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
DISCUSSIONS
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ADF4153A Data Sheet
Rev. A | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 4
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Circuit Description ........................................................................... 8
Reference Input Section ............................................................... 8
RF Input Stage ............................................................................... 8
RF INT Divider ............................................................................. 8
INT, FRAC, MOD, and R Relationship ..................................... 8
RF R Counter ................................................................................ 8
Phase Frequency Detector (PFD) and Charge Pump .............. 9
MUXOUT and Lock Detect ........................................................ 9
Input Shift Registers ..................................................................... 9
Program Modes ............................................................................ 9
Register Maps .................................................................................. 10
N Divider Register, R0 ............................................................... 15
R Divider Register, R1................................................................ 15
Control Register, R2 ................................................................... 15
Noise and Spur Register, R3 ...................................................... 16
Reserved Bits ............................................................................... 16
Initialization Sequence .............................................................. 17
RF Synthesizer: A Worked Example ........................................ 17
Modulus ....................................................................................... 17
Reference Doubler and Reference Divider ............................. 17
12-Bit Programmable Modulus ................................................ 17
Fastlock with Spurious Optimization ...................................... 18
Spur Mechanisms ....................................................................... 18
Spur Consistency ........................................................................ 19
Phase Resync ............................................................................... 19
Filter DesignADIsimPLL....................................................... 19
Interfacing ................................................................................... 19
PCB Design Guidelines for Chip Scale Package .................... 20
Applications Information .............................................................. 21
Local Oscillator for a GSM Base Station Transmitter ........... 21
Outline Dimensions ....................................................................... 22
Ordering Guide .......................................................................... 22
REVISION HISTORY
1/13Rev. 0 to Rev. A
Added TSSOP Package ...................................................... Universal
Added Figure 3, Renumbered Sequentially ................................... 6
Updated Outline Dimensions ........................................................ 22
Changes to Ordering Guide ........................................................... 22
10/12Revision 0: Initial Version
Data Sheet ADF4153A
Rev. A | Page 3 of 24
SPECIFICATIONS
AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted;
dBm referred to 50 Ω.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
RF INPUT CHARACTERISTICS (3 V) See Figure 12 for an input circuit
RF Input Frequency (RFIN) 0.5 4 GHz 8 dBm minimum/0 dBm maximum
1 4 GHz 10 dBm minimum/0 dBm maximum
For lower frequencies, ensure slew rate
(SR) > 400 V/µs
REFIN CHARACTERISTICS See Figure 11 for an input circuit
REFIN Input Frequency 10 250 MHz For f < 10 MHz, use a dc-coupled,
CMOS-compatible square wave;
slew rate > 25 V/µs
REFIN Input Sensitivity 0.7 AVDD V p-p Biased at AVDD/21
REFIN Input Capacitance 10 pF
REFIN Input Current ±100 µA
PHASE DETECTOR
Phase Detector Frequency 32 MHz
CHARGE PUMP
ICP Sink/Source Programmable; see Figure 19
High Value 5 mA With RSET = 4.7 kΩ
Low Value
µA
With R
SET
= 4.7 kΩ
Absolute Accuracy 2.5 % With RSET = 4.7 kΩ
RSET Range 3.0 10 kΩ
ICP Three-State Leakage Current 1 nA Sink and source current
Sink and Source Matching 2 % 0.5 V ≤ VCP ≤ VP − 0.5 V
ICP vs. VCP 2 % 0.5 V ≤ VCP ≤ VP − 0.5 V
ICP vs. Temperature 2 % VCP = VP/2
LOGIC INPUTS
VINH, Input High Voltage 1.4 V
V
INL
, Input Low Voltage
0.6
V
IINH/IINL, Input Current ±1 µA
CIN, Input Capacitance 10 pF
LOGIC OUTPUTS
VOH, Output High Voltage 1.4 V Open-drain 1 kΩ pull-up to 1.8 V
VOL, Output Low Voltage 0.4 V IOL = 500 µA
POWER SUPPLIES
AVDD 2.7 3.3 V
DV
DD
, SD
VDD
DD
VP AVDD 5.5 V
IDD 20 24 mA
Low Power Sleep Mode 1 µA
NOISE CHARACTERISTICS
Normalized Phase Noise Floor (PNSYNTH)2 −223 dBc/Hz PLL loop BW = 500 kHz
Normalized 1/f Noise (PN1_f)3 −121 dBc/Hz Measured at 10 kHz offset, normalized to 1 GHz
Phase Noise Performance4 @ VCO output
1750 MHz Output5 107 dBc/Hz @ 5 kHz offset, 25 MHz PFD frequency
1 AC coupling ensures AVDD/2 bias.
2 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider
value) and 10 log(FPFD). PNSYNTH = PNTOT − 10 log(FPFD) − 20 log(N).
3 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, FRF,
and at an offset frequency, f, is given by PN = P1_f + 10 log(10 kHz/f) + 20 log(FRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
4 The phase noise is measured with the EV-ADF4153ASD1Z and the Rohde & Schwarz FSUP spectrum analyzer operating in phase noise mode.
5 fREFIN = 100 MHz; FPFD = 25 MHz; offset frequency = 5 kHz; RFOUT = 1750 MHz; N = 70; loop BW = 20 kHz; lowest noise mode.
ADF4153A Data Sheet
Rev. A | Page 4 of 24
TIMING SPECIFICATIONS
AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted;
dBm referred to 50 Ω.
Table 2.
Parameter Limit at TMIN to TMAX Unit Test Conditions/Comments
t1 20 ns min LE setup time
t2 10 ns min DATA to CLK setup time
t3 10 ns min DATA to CLK hold time
t4 25 ns min CLK high duration
t5 25 ns min CLK low duration
t6 10 ns min CLK to LE setup time
t7 20 ns min LE pulse width
CLK
DATA
LE
LE
DB23 (MS B) DB22 DB2 DB1
(CO NTROL BI T C2) DB0 (L S B)
(CO NTROL BI T C1)
t
1
t
2
t
3
t
7
t
6
t
4
t
5
11047-002
Figure 2. Timing Diagram
Data Sheet ADF4153A
Rev. A | Page 5 of 24
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, GND = AGND = DGND = 0 V,
VDD = AVDD = DVDD = SDVDD, unless otherwise noted.
Table 3.
Parameter Rating
V
DD
to GND
0.3 V to +4 V
DVDD to AVDD 0.3 V to +0.3 V
SDVDD to AVDD 0.3 V to +0.3 V
VP to GND 0.3 V to +5.8 V
VP to VDD 0.3 V to +5.8 V
Digital I/O Voltage to GND
0.3 V to V
DD
+ 0.3 V
Analog I/O Voltage to GND 0.3 V to VDD + 0.3 V
REFIN, RFIN to GND 0.3 V to VDD + 0.3 V
Operating Temperature Range 40°C to +85°C
Storage Temperature Range 65°C to +125°C
Maximum Junction Temperature 150°C
TSSOP θJA Thermal Impedance 112°C/W
LFCSP θJA Thermal Impedance 30.4°C/W
Reflow Soldering
Peak Temperature 260°C
Time at Peak Temperature 40 sec
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
This device is a high performance RF integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
ESD CAUTION
ADF4153A Data Sheet
Rev. A | Page 6 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CP
CPGND
AGND
AV
DD
RF
IN
A
RF
IN
B
R
SET
DV
DD
MUXOUT
LE
SDV
DD
REF
IN
DGND
CLK
DATA
V
P
ADF4153A
TOP VI EW
(No t t o Scal e)
11047-003
Figure 3. TSSOP Pin Configuration
11047-004
NOTES
1. THE EXPOSED PAD MUST BE
CONNE CTED T O G ND.
1
CPGND
2
AGND
3
AGND 4
RF
IN
B
5
RF
IN
A
13 DATA
14 LE
15 MUXOUT
12 CLK
11 SDV
DD
6AV
DD
7
AV
DD
8
REF
IN
10DGND
9
DGND
18 V
P
19 R
SET
20 CP
17 DV
DD
16 DV
DD
TOP VI EW
(No t t o Scal e)
ADF4153A
Figure 4. LFCSP Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
TSSOP
Pin No.
LFCSP Mnemonic Description
1 19 RSET Connecting a resistor between RSET and ground sets the maximum charge pump output current.
The relationship between ICP and RSET is
SET
CPMAX
R523
I.
=
where RSET = 4.7 kΩ and ICPMAX = 5 mA.
2 20 CP Charge Pump Output. When enabled, CP provides ±ICP to the external loop filter, which in turn
drives the external VCO.
3
1
CPGND
Charge Pump Ground. This is the ground return path for the charge pump.
4 2, 3 AGND Analog Ground. This is the ground return path of the prescaler.
5 4 RFINB Complementary Input to the RF Prescaler. This pin should be decoupled to the ground plane
with a small bypass capacitor, typically 100 pF (see Figure 12).
6 5 RFINA Input to the RF Prescaler. This small signal input is normally ac-coupled from the VCO.
7 6, 7 AVDD Positive Power Supply for the RF Section. Decoupling capacitors to the digital ground plane should
be placed as close as possible to this pin. AVDD has a value of 3 V ± 10%. AVDD must have the same
voltage as DVDD.
8 8 REFIN Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input
resistance of 100 kΩ (see Figure 11). This input can be driven from a TTL or CMOS crystal oscillator,
or it can be ac-coupled.
9
9, 10
DGND
Digital Ground.
10 11 SDVDD Σ-Δ Power. Decoupling capacitors to the digital ground plane should be placed as close as possible
to this pin. SDVDD has a value of 3 V ± 10%. SDVDD must have the same voltage as DVDD.
11 12 CLK Serial Clock Input. The serial clock is used to clock in the serial data to the registers. The data is
latched into the shift register on the CLK rising edge. This input is a high impedance CMOS input.
12 13 DATA Serial Data Input. The serial data is loaded MSB first; the two LSBs are the control bits. This input is
a high impedance CMOS input.
13 14 LE Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one
of four latches; the latch is selected using the control bits.
14 15 MUXOUT This multiplexer output allows either the RF lock detect, the scaled RF, or the scaled reference
frequency to be externally accessed.
15 16, 17 DVDD Positive Power Supply for the Digital Section. Decoupling capacitors to the digital ground plane
should be placed as close as possible to this pin. DVDD has a value of 3 V ± 10%. DVDD must have
the same voltage as AVDD.
16 18 VP Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V,
it can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.
N/A 21 EPAD Exposed Pad. The exposed pad must be connected to GND.
Data Sheet ADF4153A
Rev. A | Page 7 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
Settings for single-sideband plots and phase noise vs. temperature plot: loop bandwidth = 20 kHz, reference = 100 MHz, PFD = 25 MHz,
carrier frequency = 1720.2 MHz, N = 68, MOD = 125, FRAC = 101, ICP = 2.5 mA, VCO = Mini-Circuits ROS-1800+, evaluation board =
EV-ADF4153ASD1Z, measurements taken on the Agilent E5052 signal source analyzer operating in phase noise mode.
–30
–60
–40
–70
–50
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
100 1k 10k 100k 1M 10M 100M
PHASE NOISE (d Bc/Hz)
OFF SET (Hz)
11047-005
20kHz LOOP BW, LOWEST NOISE MODE,
RF = 1720.2M Hz , PFD = 25M Hz , N = 68
FRAC = 101, MOD = 125, ICP = 2.5mA
INTEG RATED P HAS E E RROR = 0.126°
MI NI-CI RCUIT S ROS- 1800+ V CO
Figure 5. Single-Sideband Phase Noise Plot (Lowest Noise Mode)
–30
–60
–40
–70
–50
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
100 1k 10k 100k 1M 10M 100M
PHASE NOISE (d Bc/Hz)
OFF SET (Hz)
11047-006
20kHz L OOP BW, LO W NO ISE AND S P UR M ODE,
RF = 1720.2M Hz , PFD = 25M Hz , N = 68
FRAC = 101, MOD = 125, ICP = 2.5mA
INTEG RATED P HAS E E RROR = 0.138°
MI NI-CI RCUIT S ROS- 1800+ V CO
Figure 6. Single-Sideband Phase Noise Plot (Low Noise and Spur Mode)
–30
–60
–40
–70
–50
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
100 1k 10k 100k 1M 10M 100M
PHASE NOISE (d Bc/Hz)
OFF SET (Hz)
11047-007
20kHz L OOP BW, LO W SP UR M ODE,
R
F
= 1720.2M Hz , PFD = 25M Hz , N = 68
FRAC = 101, MOD = 125, I
CP
= 2.5mA
INTEG RATED P HAS E E RROR = 0.188°
MI NI-CI RCUIT S ROS- 1800+ V CO
Figure 7. Single-Sideband Phase Noise Plot (Low Spur Mode)
5
0
–35
–30
–25
–20
–15
–10
–5
00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
AMPLITUDE ( dBm)
FRE QUENCY ( GHz)
11047-008
PRES CALER = 4/5
PRES CALER = 8/9
Figure 8. RF Input Sensitivity
6
–6
–5
–4
–3
–2
–1
0
1
2
3
4
5
00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
CHARGE P UM P CURRE NT (mA)
V
CP
(V)
11047-009
Figure 9. Charge Pump Output Characteristics
–60 100806040200–20–40
PHASE NOISE (d Bc/Hz)
TEMPERATURE (°C)
11047-010
–110
–108
–106
–104
–102
–100
–98
–96
Figure 10. Phase Noise vs. Temperature
ADF4153A Data Sheet
Rev. A | Page 8 of 24
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 11. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
BUFFER T O R CO UNTER
REF
IN
100k
NC
SW2
SW3
NC
NC
SW1
POWER-DOWN
CONTROL
11047-011
Figure 11. Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 12. It is followed by a
2-stage limiting amplifier to generate the current-mode logic
(CML) clock levels needed for the prescaler.
BIAS
GENERATOR 1.6V
AGND
AV
DD
2kΩ 2kΩ
RF
IN
B
RF
IN
A
11047-012
Figure 12. RF Input Stage
RF INT DIVIDER
The RF INT CMOS counter allows a division ratio in the PLL
feedback counter. Division ratios from 31 to 511 are allowed.
INT, FRAC, MOD, AND R RELATIONSHIP
The INT, FRAC, and MOD values, in conjunction with the
R counter, make it possible to generate output frequencies that
are spaced by fractions of the phase frequency detector (PFD).
See the RF Synthesizer: A Worked Example section for more
information. The RF VCO frequency (RFOUT) equation is
RFOUT = FPFD × (INT + (FRAC/MOD)) (1)
where:
RFOUT is the output frequency of the external voltage controlled
oscillator (VCO).
INT is the preset divide ratio of the binary 9-bit counter (31
to 511).
FRAC is the numerator of the fractional division (0 to MOD − 1).
MOD is the preset fractional modulus (2 to 4095).
The PFD frequency is given by:
FPFD = REFIN × (1 + D)/R (2)
where:
REFIN is the reference input frequency.
D is the REFIN doubler bit.
R is the preset divide ratio of the binary 4-bit programmable
reference counter (1 to 15).
RF R COUNTER
The 4-bit RF R counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock to
the PFD. Division ratios from 1 to 15 are allowed.
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
FRAC
VALUE
MOD
REG
INT
REG
RF N DIVI DE R
N = INT + FRAC/ M OD
FROM RF
INPUT STAGE TO PFD
N-COUNTER
11047-013
Figure 13. RF N Divider
Data Sheet ADF4153A
Rev. A | Page 9 of 24
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 14 is a simplified schematic
of the phase frequency detector. The PFD includes a fixed
delay element that sets the width of the antibacklash pulse,
which is typically 1.8 ns. This pulse ensures that there is no
dead zone in the PFD transfer function and gives a consistent
reference spur level.
U3
CLR2
Q2
D2 U2
DOWN
UP
HI
HI
CP
–IN
+IN
CHARGE
PUMP
DELAY
CLR1
Q1D1
U1
11047-014
Figure 14. PFD Simplified Schematic
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4153A lets the user access
various internal points on the chip. The state of MUXOUT is
controlled by M3, M2, and M1 (see Figure 18). Figure 15
shows the MUXOUT section in block diagram form.
DIGITAL LOCK DETECT
R COUNTER DI V IDER
LOGIC LOW
DGND
CONTROLMUX MUXOUT
DV
DD
THREE-STATE OUTPUT
N COUNTER DI V IDER
ANALOG LO CK DE TECT
LOGIC HIGH
11047-015
Figure 15. MUXOUT Schematic
INPUT SHIFT REGISTERS
The ADF4153A digital section includes a 4-bit RF R counter,
a 9-bit RF N counter, a 12-bit FRAC counter, and a 12-bit
modulus counter. Data is clocked into the 24-bit shift register
on each rising edge of CLK. The data is clocked in MSB first.
Data is transferred from the shift register to one of four latches
on the rising edge of LE. The destination latch is determined by
the state of the two control bits (C2 and C1) in the shift register.
These are the two LSBs, DB1 and DB0, as shown in Figure 2.
The truth table for these bits is shown in Table 5. Figure 16
shows a summary of how the registers are programmed.
Table 5. C2 and C1 Truth Table
Control Bits
C2 C1 Register
0 0 N divider register
0 1 R divider register
1 0 Control register
1 1 Noise and spur register
PROGRAM MODES
Figure 16 through Figure 20 show how to set up the program
modes in the ADF4153A.
The ADF4153A programmable modulus is double buffered.
This means that two events have to occur before the part uses
a new modulus value. First, the new modulus value is latched
into the device by writing to the R divider register. Second,
a new write must be performed on the N divider register.
Therefore, to ensure that the modulus value is loaded correctly,
the N divider register must be written to any time that the
modulus value is updated.
ADF4153A Data Sheet
Rev. A | Page 10 of 24
REGISTER MAPS
NOI S E AND S P UR RE G (R3)
DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB1 DB0
C2 (1) C1 (1)
T100
0T5T6
T7T8
NOI S E AND S P UR
MODE
DB2
0
NOISE
AND SPUR
MODE
RESERVED
N DIVIDER RE G (R0)
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (0) C1 ( 0)F1
F2F3F4F5F6F7F8F9F10F11F12N1
N3N4
N5N6
CONTROL
BITS
CONTROL
BITS
CONTROL
BITS
CONTROL
BITS
12-BIT F RACTI ONAL V ALUE ( FRAC)
DB23 DB22 DB21
N7N8N9
9-BIT INTEGER VALUE (INT)
N2
FASTLOCK
FL1
R DIVIDER RE G (R1)
DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (0) C1 (1)
M1
M2
M3M4M5M6M7M8M9M10M11M12R1R3R4
12-BIT I NTERP OL ATO R M ODUL US V ALUE ( M OD)
4-BIT
R COUNT E R
R2
MUXOUT
0
DB20 DB19
P1
M1
DB23 DB22 DB21
M2M3P3
LOAD
CONTROL
RESERVED
RESERVED
PRESCALER
CONT ROL RE G (R2)
REFERENCE
DOUBLER
DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (1) C1 (0)
U1U2
U3U4U5CP0CP1CP2U6
S1S2S3S4
CP CURRENT
SETTING
PD POLARITY
RESYNC
LDP
POWER-
DOWN
CP
THREE-STATE
COUNTER
RESET
DB15
CP3
CP/2
11047-016
Figure 16. Register Summary
Data Sheet ADF4153A
Rev. A | Page 11 of 24
F12 F11 F10 F3 F2 F1 FRACT IO NAL VALUE ( FRAC)
0.......... 0
0.......... 0
0.......... 0
0.......... 0
.
.......... .
........... .
........... .
1.......... 14092
1.......... 14093
1.......... 14094
1
0
0
0
0
.
.
.
1
1
1
1
0
0
0
0
.
.
.
1
1
1
1
0
0
1
1
.
.
.
0
0
1
1
0
1
0
1
.
.
.
0
1
2
3
.
.
.
0
1
0
1.......... 14095
N9 N8 N7 N6 N5 N4 N3 N2 N1 INTEGER VALUE (INT)
0 0 0 1 1 31
0 0 1 0 0 32
0 0 1 0 1 33
0 0 1 0 034
. . . . . .
. . . . . .
. . . . . .
1 1 1 1 1 509
1 1 1 1 0510
1
0
0
0
0
.
.
.
1
1
1 1 1
1
0
0
0
.
.
.
1
1
1
1
0
0
0
.
.
...
1
1
1 1
1
0
0
1
.
.
.
0
1
1 1 511
FL1 FASTLOCK
0NORMAL OPERATION
1FASTL OCK ENABLED
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (0) C1 (0)
F1F2F3
F4
F5F6
F7
F8
F9F10F11F12
N1N3N4N5N6
CONTROL
BITS
12-BIT F RACTI ONAL V ALUE ( FRAC)
DB23 DB22 DB21
N7
N8
N9
9-BIT INTEGER VALUE (INT)
N2
FASTLOCK
FL1
11047-017
Figure 17. N Divider Register Map (R0)
ADF4153A Data Sheet
Rev. A | Page 12 of 24
M12 INTERPOLATOR
MODULUS V ALUE ( M OD)
M11 M10 M3 M2 M1
00.......... 0 1 0 2
00.......... 011 3
00.......... 1 0 0 4
. . .......... ....
. . .......... . . . .
. . .......... .. . .
1 1 .......... 10 0 4092
1 1 .......... 1 0 1 4093
1 1 .......... 11 0 4094
1
0
0
0
.
.
.
1
1
1
1 1 .......... 1 1 1 4095
RF R CO UNTER
DIVIDE RATI O
R4 R3 R2 R1
0
0
0
0
.
.
.
112
113
114
1
0
0
0
1
.
.
.
1
1
1
1
0
1
1
0
.
.
.
0
0
1
1
1
0
1
0
.
.
.
1
2
3
4
.
.
.
0
1
0
115
P1 PRESCALER
04/5
18/9
DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (0) C1 (1)
M1
M2
M3
M4M5
M6
M7
M8
M9
M10M11M12R1R3R4
CONTROL
BITS
12-BIT I NTERP OL ATO R M ODUL US V ALUE ( M OD)
4-BIT R CO UNTER
R2
MUXOUT
0
DB20 DB19
P1M1
DB23 DB22 DB21
M2M3
P3
LOAD
CONTROL
RESERVED
PRESCALER
P3 L OAD CO NTRO L
0 NORMAL OPERATION
1 LOAD RESY NC
M3 M2 M1 MUXOUT
0THREE-STATE OUTPUT
DIGITAL LOCK DETECT
ANALO G L OCK DETECT
0
0N DIVIDER OUT P UT
LOGIC HIGH
LOGIC LOW
0
1R DIVIDER OUT P UT
1
1FASTLOCK SWITCH
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
11047-018
Figure 18. R Divider Register Map (R1)
Data Sheet ADF4153A
Rev. A | Page 13 of 24
U3 POWER-DOWN
0NORMAL OPERATION
1 POWER-DOWN
U4 LDP
0
124 PF D CY CLES
40 PF D CY CLES
U5 PD POLARITY
0NEGATIVE
1POSITIVE
U2 CP THREE-STATE
0DISABLED
1 THREE-STATE
U1 COUNTER RES E T
0DISABLED
ENABLED1
REFERENCE
DOUBLER
U6
0DISABLED
1ENABLED
REFERENCE
DOUBLER
DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (1) C1 ( 0)
U1U2U3U4U5CP0CP1CP2U6S1S2S3S4
CONTROL
BITS
CP CURRENT
SETTING
PD POLARITY
RESYNC
LDP
POWER-
DOWN
CP
THREE-STATE
COUNTER
RESET
DB15
CP3
CP/2
S4 S3 S2 S1 RESYNC
0 1 1
0 0 2
0 1 3
. . .
. . .
. . .
1 1 13
1 0 14
1
0
0
0
.
.
.
1
1
1
0
1
1
.
.
.
0
1
1 1 15
ICP (mA)
CP3 CP2 CP1 CP0 3.0kΩ 4.7kΩ 10kΩ
00.979 0.625 0.294
01.958 1.250 0.588
02.938 1.875 0.881
03.917 2.500 1.175
04.896 3.125 1.469
05.875 3.750 1.763
06.854 4.375 2.056
07.833 5.000 2.350
10.490 0.313 0.147
10.979 0.625 0.294
11.469 0.938 0.441
11.958 1.250 0.588
12.448 1.563 0.734
12.938 1.875 0.881
13.427 2.188 1.028
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
13.917 2.500 1.175
11047-019
Figure 19. Control Register Map (R2)
ADF4153A Data Sheet
Rev. A | Page 14 of 24
LOW S P UR M ODE00000 LOW NOI S E AND S P UR M ODE11100 LOWEST NOISE MODE11111
DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB1 DB0
C2 (1) C1 (1)
T1000T5T6T7T8
CONTROL
BITS
NOISE AND S P UR
MODE
DB2
0
NOISE
AND SPUR
MODE
RESERVED
RESERVED
RESERVEDDB10, DB5, DB4, DB3
NOISE AND S P UR S E TT INGDB9, DB8, DB7, DB6, DB2
RESERVED0
THESE BITS MUST BE SET TO 0
FOR NORMAL OPERATION.
11047-020
Figure 20. Noise and Spur Register (R3)
Data Sheet ADF4153A
Rev. A | Page 15 of 24
N DIVIDER REGISTER, R0
With R0[1, 0] set to [0, 0], the on-chip N divider register
is programmed. Figure 17 shows the input data format for
programming this register.
9-Bit INT Value
These nine bits control what is loaded as the INT value. This is
used to determine the overall feedback division factor. It is used
in Equation 1 (see the INT, FRAC, MOD, and R Relationship
section).
12-Bit FRAC Value
These 12 bits control what is loaded as the FRAC value into
the fractional interpolator. This is part of what determines the
overall feedback division factor. It is also used in Equation 1.
The FRAC value must be less than or equal to the value loaded
into the MOD register.
Fastlock
When set to logic high, fastlock is enabled. This sets the charge
pump current to its maximum value. When set to logic low, the
charge pump current is equal to the value programmed into the
function register. Also, if MUXOUT is programmed to setting
the fastlock switch, MUXOUT is shorted to ground when the
fastlock bit is 1 and is high impedance when this bit is 0.
R DIVIDER REGISTER, R1
With R1[1, 0] set to [0, 1], the on-chip R divider register is
programmed. Figure 18 shows the input data format for
programming this register.
Load Control
When set to logic high, the value being programmed in the
modulus is not loaded into the modulus. Instead, it sets the
resync delay of the Σ-Δ. This is done to ensure phase resync
when changing frequencies. See the Phase Resync section for
more information and a worked example.
MUXOUT
The on-chip multiplexer is controlled by DB22, DB21, and
DB20 on the ADF4153A. See Figure 18 for the truth table.
Digital Lock Detect
The digital lock detect output goes high if there are 24 succes-
sive PFD cycles with an input error of less than 15 ns (for LDP
is 0, see the Control Register, R2 section for a more thorough
explanation of the LDP bit). It stays high until a new channel is
programmed or until the error at the PFD input exceeds 30 ns
for one or more cycles. If the loop bandwidth is narrow compared
to the PFD frequency, the error at the PFD inputs may drop
below 15 ns for 24 cycles around a cycle slip. Therefore, the
digital lock detect may go falsely high for a short period until
the error again exceeds 30 ns. In this case, the digital lock detect
is reliable only as a loss-of-lock detector.
Prescaler (P/P + 1)
The dual-modulus prescaler (P/P + 1), along with the INT,
FRAC, and MOD counters, determines the overall division
ratio from the RFIN to the PFD input.
Operating at CML levels, it takes the clock from the RF input
stage and divides it down for the counters. It is based on a
synchronous 4/5 core. When set to 4/5, the maximum RF
frequency allowed is 2 GHz. Therefore, when operating the
ADF4153A above 2 GHz, this must be set to 8/9. The prescaler
limits the INT value.
With P = 4/5, NMIN = 31.
With P = 8/9, NMIN = 91.
4-Bit R Counter
The 4-bit R counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock
to the phase frequency detector (PFD). Division ratios from
1 to 15 are allowed.
12-Bit Interpolator MOD Value
These programmable bits set the fractional modulus. This is the
ratio of the PFD frequency to the channel step resolution on the
RF output. Refer to the RF Synthesizer: A Worked Example
section for more information.
The ADF4153A programmable modulus is double buffered.
This means that two events have to occur before the part uses
a new modulus value. First, the new modulus value is latched
into the device by writing to the R divider register. Second,
a new write must be performed on the N divider register.
Therefore, any time that the modulus value has been updated,
the N divider register must then be written to in order to ensure
that the modulus value is loaded correctly.
CONTROL REGISTER, R2
With R2[1, 0] set to [1, 0], the on-chip control register
is programmed. Figure 19 shows the input data format for
programming this register.
RF Counter Reset
DB2 is the RF counter reset bit for the ADF4153A. When this
is 1, the RF synthesizer counters are held in reset. For normal
operation, this bit should be 0.
RF Charge Pump Three-State
DB3 puts the charge pump into three-state mode when
programmed to 1. It should be set to 0 for normal operation.
ADF4153A Data Sheet
Rev. A | Page 16 of 24
RF Power-Down
DB4 on the ADF4153A provides the programmable power-
down mode. Setting this bit to 1 performs a power-down.
Setting this bit to 0 returns the synthesizer to normal operation.
While in software power-down mode, the part retains all
information in its registers. Only when supplies are removed
are the register contents lost.
When a power-down is activated, the following events occur:
1. All active dc current paths are removed.
2. The synthesizer counters are forced to their load state
conditions.
3. The charge pump is forced into three-state mode.
4. The digital lock detect circuitry is reset.
5. The RFIN input is debiased.
6. The input register remains active and capable of loading
and latching data.
Lock Detect Precision (LDP)
When DB5 is programmed to 0, 24 consecutive PFD cycles of
15 ns must occur before digital lock detect is set. When this bit
is programmed to 1, 40 consecutive reference cycles of 15 ns
must occur before digital lock detect is set.
Phase Detector Polarity
DB6 in the ADF4153A sets the phase detector polarity. When
the VCO characteristics are positive, this should be set to 1.
When they are negative, it should be set to 0.
Charge Pump Current Setting
DB7, DB8, DB9, and DB10 set the charge pump current setting.
This should be set to the charge pump current that the loop
filter is designed with (see Figure 19).
REFIN Doubler
Setting DB11 to 0 feeds the REFIN signal directly to the 4-bit RF
R counter, disabling the doubler. Setting this bit to 1 multiplies
the REFIN frequency by a factor of 2 before feeding into the 4-bit
R counter. When the doubler is disabled, the REFIN falling edge
is the active edge at the PFD input to the fractional synthesizer.
When the doubler is enabled, both the rising and falling edges
of REFIN become active edges at the PFD input.
When the doubler is enabled and the lowest spur mode is chosen,
the in-band phase noise performance is sensitive to the REFIN
duty cycle. The phase noise degradation can be as much as 5 dB
for the REFIN duty cycles outside a 45% to 55% range. The phase
noise is insensitive to the REFIN duty cycle in the lowest noise
mode and in the lowest noise and spur mode. The phase noise
is insensitive to REFIN duty cycle when the doubler is disabled.
The maximum allowed REFIN frequency when the doubler is
enabled is 30 MHz.
NOISE AND SPUR REGISTER, R3
With R3[1, 0] set to [1, 1], the on-chip noise and spur register
is programmed. Figure 20 shows the input data format for
programming this register.
Noise and Spur Mode
Noise and spur mode lets the user optimize a design either for
improved spurious performance or for improved phase noise
performance. When the low spur setting is chosen, dither is
enabled. This randomizes the fractional quantization noise so
that it resembles white noise rather than spurious noise. As a
result, the part is optimized for improved spurious perfor-
mance. This operation would normally be used when the PLL
closed-loop bandwidth is wide, for fast-locking applications.
(Wide-loop bandwidth is seen as a loop bandwidth greater than
1/10 of the RFOUT channel step resolution (fRES).) A wide-loop
filter does not attenuate the spurs to the same level as a narrow-
loop bandwidth.
When the low noise and spur setting is enabled, dither is disabled.
This optimizes the synthesizer to operate with improved noise
performance. However, the spurious performance is degraded
in this mode compared to the low spur setting.
To further improve noise performance, the lowest noise setting
option can be used, which reduces the phase noise. As well as
disabling the dither, it also ensures that the charge pump is
operating in an optimum region for noise performance. This
setting is extremely useful where a narrow-loop filter band-
width is available. The synthesizer ensures extremely low noise
and the filter attenuates the spurs. The typical performance
characteristics give the user an idea of the trade-off in a typical
W-CDMA setup for the different noise and spur settings.
RESERVED BITS
These bits should be set to 0 for normal operation.
Data Sheet ADF4153A
Rev. A | Page 17 of 24
INITIALIZATION SEQUENCE
The following initialization sequence should be followed upon
powering up the part:
1. Write all zeros to the noise and spur register. This ensures
that all test modes are cleared.
2. Write again to the noise and spur register, this time
selecting which noise and spur mode is required. For
example, writing Hexadecimal 0003C7 to the part selects
lowest noise mode.
3. Enable the counter reset in the control register by writing a
1 to DB2; also select the required settings in the control
register. If using the phase resync function, set the resync
bits to the required settings.
4. Load the R divider register (with load control DB23
set to 0).
5. Load the N divider register.
6. Disable the counter reset by writing a 0 to DB2 in the
control register.
The part now locks to the set frequency.
If using the phase resync function, an extra step is needed after
Step 3. This involves loading the R divider register with load
control = 1 and the required delay interval in place of the MOD
value. The previous sequence can then be followed, ensuring
that in Step 4 the value of MOD is written to the R divider
register with load control = 0.
See the Spur Consistency and Phase Resync sections for more
information on the phase resync feature.
RF SYNTHESIZER: A WORKED EXAMPLE
The following equation governs how the synthesizer is
programmed:
RFOUT = [INT + (FRAC/MOD)] × [FPFD] (3)
where:
RFOUT is the RF frequency output.
INT is the integer division factor.
FRAC is the fractionality.
MOD is the modulus.
The PFD frequency is given by:
FPFD = [REFIN × (1 + D)/R] (4)
where:
REFIN is the reference frequency input.
D is the RF REFIN doubler bit.
R is the RF reference division factor.
For example, in a GSM 1800 system, where 1.8 GHz RF
frequency output (RFOUT) is required, a 13 MHz reference
frequency input (REFIN) is available and a 200 kHz channel
resolution (fRES) is required on the RF output. With REFIN
doubler (D) set to 0 and reference division (R) set to 1, from
Equation 4:
FPFD = [13 MHz × (1 + 0)/1] = 13 MHz (5)
MOD = FPFD/fRES
MOD = 13 MHz/200 kHz = 65
1.8 G = 13 MHz × (INT + FRAC/65)
where INT = 138; FRAC = 30 (6)
MODULUS
The choice of modulus (MOD) depends on the PFD frequency
(which depends on the available reference signal REFIN) and
the channel resolution (fRES) required at the RF output. For
example, a GSM system with 13 MHz REFIN sets the modulus to
65. This means that the RF output resolution (fRES) is the 200 kHz
(13 MHz/65) necessary for GSM. With dither off, the fractional
spur interval depends on the modulus values chosen. See Table 6
for more information.
REFERENCE DOUBLER AND REFERENCE DIVIDER
The reference doubler on-chip allows the input reference signal
to be doubled. This is useful for increasing the PFD comparison
frequency. Making the PFD frequency higher improves the
noise performance of the system. Doubling the PFD frequency
usually improves noise performance by 3 dB. It is important to
note that the PFD cannot be operated above specified limits due
to a limitation in the speed of the Σcircuit of the N divider.
12-BIT PROGRAMMABLE MODULUS
Unlike most other fractional-N PLLs, the ADF4153A lets the
user program the modulus over a 12-bit range. This means that
the user can set up the part in many different configurations for
the application, when combined with the reference doubler and
the 4-bit R counter.
The following is an example of an application that requires
1.75 GHz RF and 200 kHz channel step resolution. The system
has a 13 MHz reference signal.
One possible setup is feeding the 13 MHz directly to the PFD
and programming the modulus to divide by 65. This results in
the required 200 kHz resolution.
Another possible setup is using the reference doubler to create
26 MHz from the 13 MHz input signal. This 26 MHz is then fed
into the PFD. The modulus is now programmed to divide by
130. This also results in 200 kHz resolution and offers superior
phase noise performance over the previous setup.
ADF4153A Data Sheet
Rev. A | Page 18 of 24
The programmable modulus is also very useful for multi-
standard applications. If a dual-mode phone requires PDC
and GSM 1800 standards, the programmable modulus is of
great benefit. PDC requires 25 kHz channel step resolution,
whereas GSM 1800 requires 200 kHz channel step resolution.
A 13 MHz reference signal can be fed directly to the PFD. The
modulus is programmed to 520 when in PDC mode (13 MHz/
520 = 25 kHz). The modulus is reprogrammed to 65 for GSM
1800 operation (13 MHz/65 = 200 kHz). It is important that the
PFD frequency remains constant (13 MHz). This lets the user
design one loop filter that can be used in both setups without
running into stability issues. It is the ratio of the RF frequency
to the PFD frequency that affects the loop design. By keeping
this relationship constant, the same loop filter can be used in
both applications.
FASTLOCK WITH SPURIOUS OPTIMIZATION
As mentioned in the Noise and Spur Mode section, the part
can be optimized for spurious performance. However, in fast-
locking applications, the loop bandwidth needs to be wide,
and therefore the filter does not provide much attenuation of
the spurs. The programmable charge pump can be used to get
around this issue. The filter is designed for a narrow-loop
bandwidth so that steady-state spurious specifications are met.
This is designed using the lowest charge pump current setting.
To implement fastlock during a frequency jump, the charge
pump current is set to the maximum setting for the duration of
the jump by asserting the fastlock bit in the N divider register.
This widens the loop bandwidth, which improves lock time. To
maintain loop stability while in wide bandwidth mode, the loop
filter needs to be modified. This is achieved by switching in a
resistor (R1A) in parallel with the damping resistor in the loop
filter (see Figure 21). MUXOUT needs to be set to the fastlock
switch to use the internal switch. For example, if the charge
pump current is increased by 16, the damping resistor, R1,
needs to be decreased by ¼ while in wide bandwidth mode.
ADF4153A
VCO
C2 C1
CP
FL
MUXOUT
R1
R1A
11047-021
Figure 21. ADF4153A with Fastlock
The value of R1A is then chosen so that the total parallel
resistance of R1 and R1A equals 1/4 of R1 alone. This gives
an overall 4× increase in loop bandwidth, while maintaining
stability in wide bandwidth mode.
When the PLL has locked to the new frequency, the charge
pump is again programmed to the lowest charge pump current
setting by setting the fastlock bit to 0. The internal switch opens
and the damping resistor reverts to its original value. This
narrows the loop bandwidth to its original cutoff frequency
to allow better attenuation of the spurs than the wide-loop
bandwidth.
SPUR MECHANISMS
The following section describes the three different spur mechan-
isms that arise with a fractional-N synthesizer and how to
minimize them in the ADF4153A.
Fractional Spurs
The fractional interpolator in the ADF4153A is a third-order
Σ-Δ modulator (SDM) with a modulus (MOD) that is program-
mable to any integer value from 2 to 4095. In low spur mode
(dither enabled), the minimum allowed value of MOD is 50.
The SDM is clocked at the PFD reference rate (FPFD) that allows
PLL output frequencies to be synthesized at a channel step
resolution of FPFD/MOD.
In lowest noise mode and low noise and spur mode (dither off),
the quantization noise from the Σ-Δ modulator appears as frac-
tional spurs. The interval between spurs is FPFD/L, where L is the
repeat length of the code sequence in the digital Σ-Δ modulator.
For the third-order modulator used in the ADF4153A, the repeat
length depends on the value of MOD, as shown in Table 6.
Table 6. Fractional Spurs with Dither Off
Condition (Dither Off)
Repeat
Length Spur Interval
If MOD is divisible by 2, but not 3 2 × MOD Channel step/2
If MOD is divisible by 3, but not 2 3 × MOD Channel step/3
If MOD is divisible by 6 6 × MOD Channel step/6
Otherwise MOD Channel step
In low spur mode (dither enabled), the repeat length is
extended to 221 cycles, regardless of the value of MOD, which
makes the quantization error spectrum look like broadband
noise. This can degrade the in-band phase noise at the PLL
output by as much as 10 dB. Therefore, for lowest noise, dither
off is a better choice, particularly when the final loop BW is low
enough to attenuate even the lowest frequency fractional spur.
Integer Boundary Spurs
Another mechanism for fractional spur creation is interactions
between the RF VCO frequency and the reference frequency.
When these frequencies are not integer related (which is the
point of a fractional-N synthesizer), spur sidebands appear on
the VCO output spectrum at an offset frequency that corresponds
to the beat note or difference frequency between an integer
multiple of the reference and the VCO frequency.
These spurs are attenuated by the loop filter and are more
noticeable on channels close to integer multiples of the
reference where the difference frequency can be inside the
loop bandwidth, therefore, the name integer boundary spurs.
Data Sheet ADF4153A
Rev. A | Page 19 of 24
Reference Spurs
Reference spurs are generally not a problem in fractional-N
synthesizers because the reference offset is far outside the
loop bandwidth. However, any reference feedthrough mechan-
ism that bypasses the loop can cause a problem. One such
mechanism is feedthrough of low levels of on-chip reference
switching noise out through the RFIN pin back to the VCO,
resulting in reference spur levels as high as 90 dBc. Ensure that
in the PCB layout that the VCO is well separated from the input
reference to avoid a possible feed-through path on the board.
SPUR CONSISTENCY
When jumping from Frequency A to Frequency B and then
back again using some fractional-N synthesizers, the spur levels
often differ each time Frequency A is programmed. However,
in the ADF4153A, the spur levels on any particular channel are
always consistent.
PHASE RESYNC
The output of a fractional-N PLL can settle to any one of MOD
phase offsets with respect to the input reference, where MOD
is the fractional modulus. The phase resync feature in the
ADF4153A can be used to produce a consistent output phase
offset with respect to the input reference. This is necessary
in applications where the output phase and frequency are
important, such as digital beam-forming.
When phase resync is enabled, an internal timer generates sync
signals at intervals of tSYNC given by the following formula:
tSYNC = RESYNC × RESYNC_DELAY × tPFD
where tPFD is the PFD reference period.
RESYNC is the decimal value programmed in Bits DB[1512]
of Register R2 and can be any integer in the range of 1 to 15. If
RESYNC is programmed to its default value of all zeros, then
the phase resync feature is disabled.
If phase resync is enabled, then RESYNC_DELAY must be
programmed to a value that is an integer multiple of the value
of MOD. RESYNC_DELAY is the decimal value programmed
into the MOD bits (DB[13…2] of Register R1 when load
control (Bit DB23 of Register R1) = 1.
When a new frequency is programmed, the second next sync
pulse after the LE rising edge is used to resynchronize the output
phase to the reference. The tSYNC time should be programmed to
a value that is at least as long as the worst-case lock time. Doing
so guarantees that the phase resync occurs after the last cycle
slip in the PLL settling transient.
In the example shown in Figure 22, the PFD reference is
25 MHz and MOD = 125 for a 200 kHz channel spacing.
tSYNC is set to 400 µs by programming RESYNC = 10 and
RESYNC_DELAY = 1000.
LE
PHASE
FREQUENCY
SYNC
(INTERNAL)
–100 0100 200 1000
300 400 500 600 700 800 900
TIME (µs)
PLL SETTLES TO
CORRE CT PHASE
AFTER RES Y NC
LAST CYCLE SLIP
PLL SETTLES TO
INCORRECT P HAS E
t
SYNC
11047-022
Figure 22. Phase Resync Example
FILTER DESIGNADIsimPLL
A filter design and analysis program is available to help the user
implement PLL design. Visit www.analog.com/pll for a free
download of the ADIsimPLLsoftware. The software designs,
simulates, and analyzes the entire PLL frequency domain and
time domain response. Various passive and active filter
architectures are allowed.
INTERFACING
The ADF4153A has a simple SPI®-compatible serial interface
for writing to the device. CLK, DATA, and LE control the data
transfer. When latch enable (LE) is high, the 22 bits that are
clocked into the input register on each rising edge of SCLK are
transferred to the appropriate latch. See Figure 2 for the timing
diagram and Table 5 for the register truth table.
The maximum allowable serial clock rate is 20 MHz.
ADF4153A Data Sheet
Rev. A | Page 20 of 24
ADuC812 Interface
Figure 23 shows the interface between the ADF4153A and the
ADuC812 MicroConverter®. Because the ADuC812 is based on
an 8051 core, this interface can be used with any 8051-based
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4153A needs a
24-bit word, which is accomplished by writing three 8-bit bytes
from the MicroConverter to the device. After the third byte is
written, the LE input should be brought high to complete the
transfer.
ADuC812
ADF4153A
SCLOCK CLK
DATA
LE
MUXOUT
(L OCK DET E CT)
MOSI
I/O PORTS
11047-023
Figure 23. ADuC812 to ADF4153A Interface
When operating in this mode, the maximum SCLOCK rate of
the ADuC812 is 4 MHz. This means that the maximum rate at
which the output frequency can be changed is 180 kHz.
ADSP-21xx Interface
Figure 24 shows the interface between the ADF4153A and the
ADSP-21xx digital signal processor. As discussed previously,
the ADF4153A needs a 24-bit serial word for each latch write.
The easiest way to accomplish this using the ADSP-21xx family
is to use the autobuffered transmit mode of operation with
alternate framing. This provides a means for transmitting an
entire block of serial data before an interrupt is generated.
Set up the word length for eight bits and use three memory
locations for each 24-bit word. To program each 24-bit latch,
store the three 8-bit bytes, enable the autobuffered mode, and
write to the transmit register of the DSP. This last operation
initiates the autobuffer transfer.
ADSP-21xx
ADF4153A
SCLK CLK
DATA
LE
MUXOUT
(L OCK DET E CT)
DT
TFS
I/O FLAGS
11047-024
Figure 24. ADSP-21xx to ADF4153A Interface
PCB DESIGN GUIDELINES FOR CHIP SCALE
PACKAGE
The lands on the chip scale package (CP-20) are rectangular.
The printed circuit board (PCB) pad for these should be 0.1 mm
longer than the package land length and 0.05 mm wider than
the package land width. The land should be centered on the
pad. This ensures that the solder joint size is maximized.
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the PCB should be at least as large as this
exposed pad. On the PCB, there should be a clearance of at least
0.25 mm between the thermal pad and the inner edges of the
pad pattern. This ensures that shorting is avoided.
Thermal vias can be used on the PCB thermal pad to improve
thermal performance of the package. If vias are used, they should
be incorporated in the thermal pad at 1.2 mm pitch grid. The
via diameter should be between 0.3 mm and 0.33 mm, and the
via barrel should be plated with one ounce of copper to plug the
via. The user should connect the PDB thermal pad to AGND.