BCM8703 PRODUCT Brief (R) SERIAL 10-G ETHERNET/FIBRE CHANNEL TRANSCEIVER WITH XAUI INTERFACE B C M 8 7 0 3 S U M M A R Y F E AT U R E S * IEEE 802.3ae compliant * Support for XENPAK and XPAK Standards TM B E N E F I T S * Automatic device configuration at power-up * Core power supply: 1.2V * Low-power CMOS solution: 1.5W typical * Low power consumption eliminates external heat * Xenpak support optimized for Xenpak/XPAK layout and thermal * Fully integrated CMU, CDR, and SerDes * Integrated limiting amplifier and EyeOpener O F sinks, fans for system airflow, and expensive high current power supplies. for interfacing to XFP modules * PMD interface with serial 10.3125/10.5188 Gbps CML * PSC 64B/66B scrambler/descrambler * XGXS 8B/10B error detection ENDEC * XAUI link synchronization/deskew * Four-lane XAUI interface (3.125/3.5188 Gbps) * Loss-of-signal detection * Digital Optical Monitoring (DOM) support * Loopback modes * 802.3 clause 45 management interface extended * Reduces design cycle and time to market. * Uses the most effective silicon economy of scale for CMOS-based devices. * Target applications: * XENPAK/XPAK fiber-optic modules * LAN/WAN switches * Switch/router backbones * Hubs and repeaters * Network Interface Cards (NICs) * Test equipment indirect address access * Built-In Self-Test (BIST) * Built-in jitter tests for XAUI and PMD * Built-in BERT test support * EEPROM interface support Application Block Diagram XAUI PCS/PMA MAC XGXS XGXS RS Media Access Controller Interface BCM8703 MDC MDIO Management Interface OTX 10.3125/10.5188 Gbps ORX Optical PMD EEPROM B C M 8 7 0 3 O V E R V I E W Block Diagram Receive Path PCDRLK PLOSB Limiting Amplifier and EyeOpener TM A XDOP XDON 8B/10B Encoder Serializer 64B/66B Synchronizer Descrambler Decoder E Gearbox XAON 3.125/3.188-Gbps Differential XAUI Randomizer 8B/10B Encoder Serializer Elastic FIFO I XAOP 322.26/328.72 MHz F CMU PDIP PDIN VCPCDR VCNCDR 312.5/318.76 MHz 2 MUX 156.25/159.38 MHz CDR & Deserializer C AC-coupled 10.3215/10.5188-Gbps Differential CML Serial Data Input XEXTCLKP XEXTCLKN XPDOUT Phase Detector AC-coupled Differential LVPECL 156.25/159.38 MHz Transmit Path MUX PEXTCLKP PEXTCLKN 156.25/159.38 MHz PPDOUT PVCOXP Phase Detector XAIP Sync Detect Lane Sync 8B/10B Decoder DLL & Deserializer XAIN Lane Alignment FIFO B XDIP DLL & Deserializer XDIN 312.5/318.76 MHz 322.26/328.72 MHz G Sync Detect Lane Sync 8B/10B Decoder Lane Alignment FIFO 10.3215/10.5188-Gbps Differential CML Serial Data Output 64B/66B Encoder Scrambler Gearbox 2 312.5/318.76 MHz Elastic FIFO AC-coupled 3.125/3.188-Gbps Differential XAUI MUX PVCOXN RSTB MDC MDIO PRTAD[4:0] REFCLKOUT LASI SYSRSTB PLOSB/A1 CONFIG[1:0] TXONOFF Management Resisters and Control Interface SDA SCL ZWENB 2-Wire Interface TRST JTCK TMS TDI TDO CMU & Serializer PDOP PDON PCOP H PCMULK D PCON 10.5188 GHz 10.3215/10.5188-Gbps Differential CML Serial Clock Output OPTXENB0/1 OPTXRST0/1 Loopback Mode: XAUI Independent Lane Loopback = B to A System Loopback = G to I Line Loopback = C to D XGXS Loopbacks = A to B PCS/PMA/PMD Loopback = D to C BIST: E - XAUI BIST Generator F - PMD BIST Checker G - XAUI BIST Checker H - PMD BIST Generator Optics Control and Status OPRXLOS OPBIASFLT OPTMPFLT OPPWFLT OPOUTLVL OPINLVL OPTXFLT OPRXFLT JTAG The BCM8703 Ethernet/Fibre Channel PHY is a fully integrated serialization/deserialization (10.3125/10.5188-Gbps) interface device performing the extension functions for a 10 Gigabit Serial Ethernet Reconciliation Sublayer (RS) interface. The XGMII Extender Sublayer (XGXS), Physical Codings Sublayer (PCS), and Physical Medium Attachment (PMA) functions include 8B/10B coding, 64B/66B coding, SerDes, Clock Multiplication Unit (CMU), and Clock and Data Recovery (CDR). performed on the device by synchronizing the on-chip VCOs directly to their respective incoming data streams. Elastic buffers allow the XAUI and PMD interfaces to operate in either a synchronous or asynchronous configuration. An external 156.25-MHz VCXO is required for synchronous mode operation or for asynchronous mode with clock cleanup. The BCM8703 is packaged in a 13 x 13 mm BGA package with a 0.8-mm ball pitch. On-chip clock synthesis is performed by the high-frequency, low-jitter, phase-locked loops for the PMD and XAUI output retimers. Individual PMD and XAUI clock recovery is Broadcom(R), the pulse logo, Connecting everything(R), and EyeOpenerTM are trademarks of Broadcom Corporation and/or its subsidiaries in the United States and certain other countries. All other trademarks are the property of their respective owners. (R) BROADCOM CORPORATION 16215 Alton Parkway, P.O. Box 57013 Irvine, California 92619-7013 (c) 2003 by BROADCOM CORPORATION. All rights reserved. 8703-PB03-R 06-13-03 Phone: 949-450-8700 FAX: 949-450-8710 Email: info@broadcom.com Web: www.broadcom.com