ICS332-33
MDS 332-33 D 1Revision 051310
Integrated Device Technology, Inc. ● www.idt.com
Dual Output Clock Synthesizer
Description
The ICS332-33 is a low-cost frequency generator that
is factory programmable. Using analog/digital
Phase-Locked-Loop (PLL) techniques, the device
accepts a 16.384 MHz clock input to produce output
clocks of 52 MHz and 120 MHz. In one selection the 52
MHz clock has center spread spectrum of ±1.0%.
The device also has a power down feature that
tri-states the clock outputs and turns off the PLLs when
the PDTS pin is taken low.
Features
•8 pin SOIC package – Pb-free, RoHS compliant
•Input clock frequency of 16.384 MHz
•Two output clocks of 52 MHz and 120 MHz
•Spread spectrum enabled at +1% (center)
•Duty cycle of 45/55
•Operating voltage of 3.3 V
•Advanced, low-power CMOS process
•For one output clock (lowest jitter), use the ICS331.
For three output clocks, see the ICS333. For more
than three outputs, see the ICS355 or ICS388.
Block Diagram
X1
X2
Crystal
Oscillator
PLL
Clock
Synthesis
and
Control
Circuitry
52M
120M
PDTS (both outputs and PLL)
16.384 MHz Crystal
OTP
ROM
with PLL
Divider
Values
Optional crystal capacitors
SEL
Dual Output Clock Synthesizer
MDS 332-33 D 2Revision 051310
Integrated Device Technology, Inc. ● www.idt.com
ICS332-33
Pin Assignment
8-pin (150 mil) SOIC
Output Clock Selection Table
Pin Descriptions
External Components
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω.
Decoupling Capacitor
As with any high-performance mixed-signal IC, the
ICS332-33 must be isolated from system power supply
noise to perform optimally.
A decoupling capacitor of 0.01µF must be connected
between VDD and the PCB ground plane.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal capacitors
must be connected from each of the pins X1 and X2 to
ground.
The value (in pF) of these crystal caps should equal
(CL -6 pF)*2. In this equation, CL= crystal load
capacitance in pF. Example: For a crystal with a 16 pF
X1
VDD
GND
PDTS
CLK1
SEL
CLK2
X21
2
3
4
8
7
6
5
SEL CLK1 (MHz) CLK2 (MHz) Spread on
CLK2
0 52 120 -
1 52 120 ± 1.0%
Pin Pin Pin Pin Description
1 X1 XI Connect this pin to a 16.384 MHz crystal input.
2 VDD Power Connect to +3.3V.
3 GND Power Connect to ground.
4 CLK1 Output 52 MHz clock output with ±1.0% spread spectrum. Weak internal
pull-down when tri-state.
5 CLK2 Output 120 MHz clock output. Weak internal pull-down when tri-state.
6 SEL Input Select pin for frequency selection on CLK1 and CLK2. Internal pull-up.
7 PDTS Input Powers down entire chip. Tri-states CLK outputs when low. Internal
pull-up.
8 X2 XO Float for clock input.
Dual Output Clock Synthesizer
MDS 332-33 D 3Revision 051310
Integrated Device Technology, Inc. ● www.idt.com
ICS332-33
load capacitance, each crystal capacitor would be 20
pF [(16-6) x 2 = 20].
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01µF decoupling capacitor should be mounted
on the component side of the board as close to the
VDD pin as possible. No vias should be used between
decoupling capacitor and VDD pin. The PCB trace to
VDD pin should be kept as short as possible, as should
the PCB trace to the ground via. Distance of the ferrite
bead and bulk decoupling from the device is less
critical.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
3) To minimize EMI, the 33Ω series termination resistor
(if needed) should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (the ferrite bead and bulk decoupling
capacitor can be mounted on the back). Other signal
traces should be routed away from the ICS332-33. This
includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the
device.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS332-33. These ratings,
which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Recommended Operation Conditions
Item Rating
Supply Voltage, VDD 7 V
All Inputs and Outputs -0.5 V to VDD+0.5 V
Ambient Operating Temperature 0 to +70°C
Storage Temperature -65 to +150°C
Junction Temperature 125°C
Soldering Temperature 260°C
Parameter Min. Typ. Max. Units
Ambient Operating Temperature 0 – +70 °C
Power Supply Voltage (measured in respect to GND) +3.15 +3.3 +3.45 V
Dual Output Clock Synthesizer
MDS 332-33 D 4Revision 051310
Integrated Device Technology, Inc. ● www.idt.com
ICS332-33
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature 0 to +70°C
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature 0 to +70° C
Parameter Symbol Conditions Min. Typ. Max. Units
Operating Voltage VDD 3.15 3.3 3.45 V
Supply Current IDD No load, PDTS=1 34 mA
No load, PDTS=0 21 µA
Input High Voltage, PDTS VIH – VDD-0.5 – – V
Input Low Voltage, PDTS VIL –––0.4V
Input High Voltage, SEL VIH 2--V
Input Low Voltage, SEL VIL --0.4V
Input High Voltage, ICLK VIH –VDD/2+1 ––V
Input Low Voltage, ICLK VIL –––
VDD/2-1 V
Output High Voltage (CMOS
High)
VOH IOH = -8 mA VDD-0.4 V
Output High Voltage VOH IOH = -12 mA 2.4 V
Output Low Voltage VOL IOL = 12 mA – – 0.4 V
Short Circuit Current IOS ±70 mA
Parameter Symbol Conditions Min. Typ. Max. Units
Output Rise Time tOR 0.8 to 2.0 V 1.0 ns
Output Fall Time tOF 2.0 to 0.8 V 1.0 ns
Duty Cycle 40 60 %
Cycle Jitter (short term jitter) tja Peak to peak, 52M no
spread and 120M CLKs
±100 ps
Input Frequency, clock input 16.384 MHz
Output Frequency Synthesis
Error
52M clock -155 ppm
Output Frequency Synthesis
Error
120M clock -94 ppm
Output Enable Time, PDTS
high to output on
250 µs
Output Disable Time, PDTS low
to tri-state
200 µs
Dual Output Clock Synthesizer
MDS 332-33 D 5Revision 051310
Integrated Device Technology, Inc. ● www.idt.com
ICS332-33
Package Outline and Package Dimensions (8 pin SOIC, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
Ordering Information
*NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01
“LF” denotes Pb (lead) free package.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any
circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or
critical medical instruments.
Part / Order Number Marking Shipping Packaging Package Temperature
332M-33LF 332M33L Tubes 8-pin SOIC 0 to +70° C
332M-33LFT Tape and Reel 8-pin SOIC 0 to +70° C
INDEX
AREA
1 2
8
D
E
SEATING
PLANE
A1
A
e
- C -
B
.10 (.004) C
C
L
H
h x 45
Millimeters Inches
Symbol Min Max Min Max
A 1.35 1.75 .0532 .0688
A1 0.10 0.25 .0040 .0098
B 0.33 0.51 .013 .020
C 0.19 0.25 .0075 .0098
D 4.80 5.00 .1890 .1968
E 3.80 4.00 .1497 .1574
e 1.27 BASIC 0.050 BASIC
H 5.80 6.20 .2284 .2440
h 0.25 0.50 .010 .020
L 0.40 1.27 .016 .050
α0°8°0°8°
