ICS332-33 Dual Output Clock Synthesizer Description Features The ICS332-33 is a low-cost frequency generator that is factory programmable. Using analog/digital Phase-Locked-Loop (PLL) techniques, the device accepts a 16.384 MHz clock input to produce output clocks of 52 MHz and 120 MHz. In one selection the 52 MHz clock has center spread spectrum of 1.0%. * * * * * * * * The device also has a power down feature that tri-states the clock outputs and turns off the PLLs when the PDTS pin is taken low. 8 pin SOIC package - Pb-free, RoHS compliant Input clock frequency of 16.384 MHz Two output clocks of 52 MHz and 120 MHz Spread spectrum enabled at +1% (center) Duty cycle of 45/55 Operating voltage of 3.3 V Advanced, low-power CMOS process For one output clock (lowest jitter), use the ICS331. For three output clocks, see the ICS333. For more than three outputs, see the ICS355 or ICS388. Block Diagram SEL OTP ROM w ith P L L D iv id e r V a lu e s 1 6 .3 8 4 M H z C ry s ta l PLL C lo c k S y n th e s is and C o n tro l C irc u itry 52M 120M X1 C ry s ta l O s c illa to r X2 O p tio n a l crysta l ca p a cito rs P D T S (b o th o u tp u ts a n d P L L ) MDS 332-33 D 1 Integrated Device Technology, Inc. Revision 051310 w w w. i d t . c o m ICS332-33 Dual Output Clock Synthesizer Pin Assignment Output Clock Selection Table X1 1 8 X2 VDD 2 7 PDTS GND 3 6 SEL CLK1 4 5 CLK2 SEL CLK1 (MHz) 0 1 CLK2 (MHz) 52 52 120 120 Spread on CLK2 1.0% 8-pin (150 mil) SOIC Pin Descriptions Pin 1 2 3 4 Pin X1 VDD GND CLK1 Pin XI Power Power Output 5 6 7 CLK2 SEL PDTS Output Input Input 8 X2 XO Pin Description Connect this pin to a 16.384 MHz crystal input. Connect to +3.3V. Connect to ground. 52 MHz clock output with 1.0% spread spectrum. Weak internal pull-down when tri-state. 120 MHz clock output. Weak internal pull-down when tri-state. Select pin for frequency selection on CLK1 and CLK2. Internal pull-up. Powers down entire chip. Tri-states CLK outputs when low. Internal pull-up. Float for clock input. External Components Series Termination Resistor Crystal Load Capacitors Clock output traces over one inch should use series termination. To series terminate a 50 trace (a commonly used trace impedance), place a 33 resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20. The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) between the crystal and device. Crystal capacitors must be connected from each of the pins X1 and X2 to ground. Decoupling Capacitor As with any high-performance mixed-signal IC, the ICS332-33 must be isolated from system power supply noise to perform optimally. A decoupling capacitor of 0.01F must be connected between VDD and the PCB ground plane. MDS 332-33 D The value (in pF) of these crystal caps should equal (CL -6 pF)*2. In this equation, CL= crystal load capacitance in pF. Example: For a crystal with a 16 pF 2 I n t e gra te d D ev i ce Technology, Inc. Revision 051310 w w w. i d t . c o m ICS332-33 Dual Output Clock Synthesizer load capacitance, each crystal capacitor would be 20 pF [(16-6) x 2 = 20]. PCB Layout Recommendations 2) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. For optimum device performance and lowest output phase noise, the following guidelines should be observed. 3) To minimize EMI, the 33 series termination resistor (if needed) should be placed close to the clock output. 1) The 0.01F decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 4) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). Other signal traces should be routed away from the ICS332-33. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS332-33. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature 0 to +70 C Storage Temperature -65 to +150 C Junction Temperature 125 C Soldering Temperature 260 C Recommended Operation Conditions Parameter Min. Typ. Max. Units 0 - +70 C +3.15 +3.3 +3.45 V Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) MDS 332-33 D 3 I n t e gra te d D ev i ce Technology, Inc. Revision 051310 w w w. i d t . c o m ICS332-33 Dual Output Clock Synthesizer DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature 0 to +70 C Parameter Symbol Operating Voltage VDD Supply Current IDD Conditions Min. Typ. Max. Units 3.15 3.3 3.45 V No load, PDTS=1 34 mA No load, PDTS=0 21 A Input High Voltage, PDTS VIH - VDD-0.5 - - V Input Low Voltage, PDTS VIL - - - 0.4 V Input High Voltage, SEL VIH 2 - - V Input Low Voltage, SEL VIL - - 0.4 V Input High Voltage, ICLK VIH - VDD/2+1 - - V Input Low Voltage, ICLK VIL - - - VDD/2-1 V Output High Voltage (CMOS High) VOH IOH = -8 mA VDD-0.4 V Output High Voltage VOH IOH = -12 mA 2.4 V Output Low Voltage VOL IOL = 12 mA - Short Circuit Current IOS - 0.4 70 V mA AC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature 0 to +70 C Parameter Symbol Conditions Min. Typ. Max. Units Output Rise Time tOR 0.8 to 2.0 V 1.0 ns Output Fall Time tOF 2.0 to 0.8 V 1.0 ns Duty Cycle 40 Cycle Jitter (short term jitter) Peak to peak, 52M no spread and 120M CLKs tja Input Frequency, clock input 60 % 100 ps 16.384 MHz Output Frequency Synthesis Error 52M clock -155 ppm Output Frequency Synthesis Error 120M clock -94 ppm Output Enable Time, PDTS high to output on 250 s Output Disable Time, PDTS low to tri-state 200 s MDS 332-33 D 4 I n t e gra te d D ev i ce Technology, Inc. Revision 051310 w w w. i d t . c o m ICS332-33 Dual Output Clock Synthesizer Package Outline and Package Dimensions (8 pin SOIC, 150 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters 8 E Inches Symbol Min Max Min Max A 1.35 1.75 .0532 .0688 A1 0.10 0.25 .0040 .0098 B 0.33 0.51 .013 .020 C 0.19 0.25 .0075 .0098 D 4.80 5.00 .1890 .1968 E 3.80 4.00 .1497 .1574 H INDEX AREA e 1 2 D 1.27 BASIC 0.050 BASIC H 5.80 6.20 .2284 .2440 h 0.25 0.50 .010 .020 L 0.40 1.27 .016 .050 0 8 0 8 A h x 45 A1 C -Ce SEATING PLANE B L .10 (.004) C Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature 332M-33LF 332M-33LFT 332M33L Tubes Tape and Reel 8-pin SOIC 8-pin SOIC 0 to +70 C 0 to +70 C *NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01 "LF" denotes Pb (lead) free package. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. MDS 332-33 D 5 I n t e gra te d D ev i ce Technology, Inc. Revision 051310 w w w. i d t . c o m