MCM6206BBEJ12 - Motorola / Freescale Semiconductor

MCM6206BB

MOTOROLA FAST SRAM

Product Preview

32K x 8 Bit Fast Static RAM

The MCM6206BB is a 262,144 bit static random access memory organized as

32,768 words of 8 bits. Static design eliminates the need for external clocks or

timing strobes, while CMOS circuitry reduces power consumption and provides

for greater reliability.

This device meets JEDEC standards for functionality and pinout, and is avail-

able in plastic small–outline J–leaded packages.

•Single 5 V ±10% Power Supply

•Fully Static — No Clock or Timing Strobes Necessary

•Fast Access Times: 12/15/20/25 ns

•Equal Address and Chip Enable Access Times

•Output Enable (G) Feature for Increased System Flexibility and to

Eliminate Bus Contention Problems

•Low Power Operation: 125 – 140 mA Maximum AC

•Fully TTL Compatible — Three State Output

BLOCK DIAGRAM

AAAAAA

MEMORY MATRIX

ROW

DECODER

INPUT

DATA

CONTROL

COLUMN I/O

COLUMN DECODER

VCC

VSS

CIRCUIT

CONTROL

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

Order this document

by MCM6206BB/D

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

PIN ASSIGNMENT

MCM6206BB

DQ DQ

A Address Input. . . . . . . . . . . . . . . . . . . .

DQ Data Input/Data Output. . . . . . . . . .

WWrite Enable. . . . . . . . . . . . . . . . . . . .

GOutput Enable. . . . . . . . . . . . . . . . . . .

EChip Enable. . . . . . . . . . . . . . . . . . . . . .

VCC Power Supply (+ 5 V). . . . . . . . . . .

VSS Ground. . . . . . . . . . . . . . . . . . . . . . .

J PACKAGE

300 MIL SOJ

CASE

810B–03

PIN NAMES

6/4/97

 Motorola, Inc. 1997

MCM6206BB

2MOTOROLA FAST SRAM

TRUTH TABLE (X = Don’t Care)

EG W Mode VCC Current Output Cycle

H X X Not Selected ISB1, ISB2 High–Z –

L H H Output Disabled ICCA High–Z –

L L H Read ICCA Dout Read Cycle

L X L Write ICCA High–Z Write Cycle

ABSOLUTE MAXIMUM RATINGS

Rating Symbol Value Unit

Power Supply Voltage VCC – 0.5 to + 7.0 V

Voltage Relative to VSS For Any Pin

Except VCC Vin, Vout – 0.5 to VCC + 0.5 V

Output Current Iout ±20 mA

Power Dissipation PD1.0 W

Temperature Under Bias Tbias – 10 to + 85 °C

Ambient Temperature TA0 to + 70 °C

Storage Temperature—Plastic Tstg – 55 to + 125 °C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are

exceeded. Functional operation should be restricted to RECOMMENDED OPER-

ATING CONDITIONS. Exposure to higher than recommended voltages for ex-

tended periods of time could af fect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ±10%, TA = 0 to 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Typ Max Unit

Supply V oltage (Operating Voltage Range) VCC 4.5 5.0 5.5 V

Input High Voltage VIH 2.2 — VCC + 0.3** V

Input Low Voltage VIL – 0.5*— 0.8 V

*VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns)

**VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 20 ns)

DC CHARACTERISTICS

Parameter Symbol Min Max Unit

Input Leakage Current (All Inputs, V in = 0 to VCC) Ilkg(I) —±1µA

Output Leakage Current (E = VIH or G = VIH, Vout = 0 to VCC) Ilkg(O) —±1µA

Output High Voltage (IOH = – 4.0 mA) VOH 2.4 — V

Output Low Voltage (IOL = 8.0 mA) VOL —0.4 V

POWER SUPPLY CURRENTS

Parameter Symbol –12 –15 –20 –25 Unit

AC Active Supply Current (Iout = 0 mA, VCC = Max, f = fmax) ICCA 140 135 130 125 mA

AC Standby Current (E = VIH, VCC = Max, f = fmax) ISB1 40 35 35 30 mA

CMOS Standby Current (VCC = Max, f = 0 MHz, E ≥VCC – 0.2 V

Vin ≤VSS + 0.2 V, or ≥VCC – 0.2 V) ISB2 10 10 10 10 mA

CAPACITANCE (f = 1 MHz, dV = 3 V, TA = 25°C, Periodically sampled rather than 100% tested)

Characteristic Symbol Max Unit

Address Input Capacitance Cin 6pF

Control Pin Input Capacitance (E, G, W) Cin 8pF

I/O Capacitance CI/O 8pF

This device contains circuitry to protect the

inputs against damage due to high static volt-

ages or electric fields; however, it is advised

that normal precautions be taken to avoid

application of any voltage higher than maxi-

mum rated voltages to this high–impedance

circuit.

This CMOS memory circuit has been de-

signed to meet the dc and ac specifications

shown in the tables, after thermal equilibrium

has been established. The circuit is in a test

socket or mounted on a printed circuit board

and transverse air flow of at least 500 linear

feet per minute is maintained.

MCM6206BB

MOTOROLA FAST SRAM

AC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ±10%, TA = 0 to + 70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .

Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time 5 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . .

Output Load Figure 1 Unless Otherwise Noted. . . . . . . . . . . . . . . . . .

READ CYCLE (See Note 1)

–12 –15 –20 –25

Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes

Read Cycle T ime tAVAV 12 — 15 — 20 — 25 — ns 2

Address Access Time tAVQV —12 — 15 — 20 — 25 ns

Enable Access T ime tELQV — 12 — 15 — 20 — 25 ns 3

Output Enable Access T ime tGLQV — 6 — 8 — 10 — 12 ns

Output Hold from Address Change tAXQX 3 — 3 — 3 — 3 — ns 4,5,6

Enable Low to Output Active tELQX 4 — 4 — 4 — 4 — ns 4,5,6

Enable High to Output High–Z tEHQZ — 7 — 8 — 9 — 10 ns 4,5,6

Output Enable Low to Output Active tGLQX 0 — 0 — 0 — 0 — ns 4,5,6

Output Enable High to Output High–Z tGHQZ — 6 — 7 — 8 — 10 ns 4,5,6

Power Up T ime tELICCH 0 — 0 — 0 — 0 — ns

Power Down T ime tEHICCL — 12 — 15 — 20 — 25 ns

NOTES:

1. W is high for read cycle.

2. All timings are referenced from the last valid address to the first transitioning address.

3. Addresses valid prior to or coincident with E going low.

4. At any given voltage and temperature, tEHQZ (max) is less than tELQX (min), and tGHQZ (max) is less than tGLQX (min), both for a given

device and from device to device.

5. T ransition is measured ±500 mV from steady–state voltage.

6. This parameter is sampled and not 100% tested.

7. Device is continuously selected (E = VIL, G = VIL).

OUTPUT

Z0 = 50

Ω

VL = 1.5 V

TIMING LIMITS

The table of timing values shows either a

minimum or a maximum limit for each param-

eter. Input requirements are specified from

the external system point of view. Thus, ad-

dress setup time is shown as a minimum

since the system must supply at least that

much time. On the other hand, responses

from the memory are specified from the de-

vice point of view. Thus, the access time is

shown as a maximum since the device never

provides data later than that time.

Figure 1. AC Test Loads

MCM6206BB

4MOTOROLA FAST SRAM

READ CYCLE 1 (See Note 7)

Q (DATA OUT)

A (ADDRESS)

DATA VALIDPREVIOUS DATA V ALID

tAVAV

tAXQX

tAVQV

READ CYCLE 2 (See Note 3)

ISB

ICC

tEHQZ

tEHICCL

DATA VALID

tGHQZ

tAVAV

tELQX

tELQV

E (CHIP ENABLE)

Q (DATA OUT)

A (ADDRESS)

tELICCH

tAVQV

tGLQX

tGLQV

G (OUTPUT ENABLE)

VCC

SUPPLY CURRENT

HIGH Z HIGH Z

MCM6206BB

MOTOROLA FAST SRAM

WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)

–12 –15 –20 –25

Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes

Write Cycle Time tAVAV 12 — 15 — 20 — 25 — ns 3

Address Setup T ime tAVWL 0 — 0 — 0 — 0 — ns

Address Valid to End of Write tAVWH 10 — 12 — 15 — 20 — ns

Write Pulse Width tWLWH,

tWLEH 10 — 12 — 15 — 20 — ns

Write Pulse Width,

G High tWLWH,

tWLEH 10 — 10 — 12 — 15 — ns 4

Data Valid to End of Write tDVWH 6 — 7 — 8 — 10 — ns

Data Hold T ime tWHDX 0 — 0 — 0 — 0 — ns

Write Low to Output High–Z tWLQZ — 6 — 7 — 8 — 10 ns 5,6,7

Write High to Output Active tWHQX 2 — 2 — 2 — 2 — ns 5,6,7

Write Recovery Time tWHAX 0 — 0 — 0 — 0 — ns

NOTES:

1. A write occurs during the overlap of E low and W low.

2. If G goes low coincident with or after W goes low, the output will remain in a high impedance state.

3. All timings are referenced from the last valid address to the first transitioning address.

4. If G ≥ VIH, the output will remain in a high impedance state.

5. At any given voltage and temperature, tWLQZ (max) is less than tWHQX (min), both for a given device and from device to device.

6. T ransition is measured ±500 mV from steady–state voltage.

7. This parameter is sampled and not 100% tested.

WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)

DATA VALID

tDVWH

tAVWL

tAVWH

tAVAV

tWHAX

tWLWH

tWHDX

tWLQZ tWHQX

HIGH Z HIGH Z

A (ADDRESS)

W (WRITE ENABLE)

E (CHIP ENABLE)

Q (DATA OUT)

D (DATA IN)

tWLEH

MCM6206BB

6MOTOROLA FAST SRAM

WRITE CYCLE 2 (E Controlled, See Note 1)

–12 –15 –20 –25

Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes

Write Cycle Time tAVAV 12 — 15 — 20 — 25 — ns

Address Setup T ime tAVEL 0 — 0 — 0 — 0 — ns

Address Valid to End of Write tAVEH 10 — 12 — 15 — 20 — ns

Enable to End of Write tELEH,

tELWH 9 — 10 — 12 — 15 — ns 3,4

Data Valid to End of Write tDVEH 6 — 7 — 8 — 10 — ns

Data Hold T ime tEHDX 0 — 0 — 0 — 0 — ns

Write Recovery Time tEHAX 0 — 0 — 0 — 0 — ns

NOTES:

1. A write occurs during the overlap of E low and W low.

2. All timings are referenced from the last valid address to the first transitioning address.

3. If E goes low coincident with or after W goes low, the output will remain in a high impedance state.

4. If E goes high coincident with or before W goes high, the output will remain in a high impedance state.

WRITE CYCLE 2 (E Controlled, See Note 1)

tWLEH

tEHDX

tDVEH

tEHAX

tELWH

tELEH

tAVEL

tAVEH

DATA VALID

tAVAV

HIGH Z

A (ADDRESS)

W (WRITE ENABLE)

E (CHIP ENABLE)

Q (DATA OUT)

D (DATA IN)

MCM6206BB

MOTOROLA FAST SRAM

ORDERING INFORMATION

(Order by Full Part Number)

Motorola Memory Prefix

Part Number

Package (J = 300 mil SOJ, E = Evolutionary Pinout)

Shipping Method (R = Tape and Reel, Blank = Rails)

Speed (12 = 12 ns, 15 = 15 ns, 20 = 20 ns,

25 = 25 ns)

MCM 6206BB EJ XX X

Full Part Numbers — MCM6206BBEJ12 MCM6206BBEJ12R

MCM6206BBEJ15 MCM6206BBEJ15R

MCM6206BBEJ20 MCM6206BBEJ20R

MCM6206BBEJ25 MCM6206BBEJ25R

MCM6206BB

8MOTOROLA FAST SRAM

PACKAGE DIMENSIONS

CASE 810B–03

300 MIL SOJ

28 LEAD

0.25 (0.010) T B

S S

0.18 (0.007) T B

S S

0.18 (0.007) T A

MSMIN MINMAX MAX

INCHES MILLIMETERS

DIM

1.27 BSC

0.64 BSC

0.050 BSC

0.025 BSC

18.29

7.50

3.26

0.39

2.24

0.67

—

0.89

0.76

8.38

6.60

0.77

18.54

7.74

3.75

0.50

2.48

0.81

0.50

1.14

8.64

6.86

1.01

0.720

0.295

0.128

0.015

0.088

0.026

—

0.035

0.030

0.330

0.260

0.030

0.730

0.305

0.148

0.020

0.098

0.032

0.020

0.045

0.340

0.270

0.040

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. DIMENSION A & B DO NOT INCLUDE MOLD

PROTRUSION. MOLD PROTRUSION SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

3. CONTROLLING DIMENSION: INCH.

4. DIM R TO BE DETERMINED AT DATUM -T-.

KDETAIL Z

DETAIL Z

S RAD

-B-

-A- P

0.10 (0.004)

SEATING PLANE

-T-

D 24 PL

H BRK

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and

specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola

data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”

must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of

others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other

applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury

or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola

and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees

arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that

Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal

Opportunity/Af firmative Action Employer.

Mfax is a trademark of Motorola, Inc.

How to reach us:

USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 4–32–1,

P.O. Box 5405, Denver, Colorado 80217. 303–675–2140 or 1–800–441–2447 Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan. 81–3–5487–8488

Mfax: RMFAX0@email.sps.mot.com – TOUCHTONE 602–244–6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,

– US & Canada ONLY 1–800–774–1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298

INTERNET: http://motorola.com/sps

MCM6206BB/D

◊