1
Microsemi Corporation
Copyright 2012, Microsemi Corporation. All Rights Reserved.
Features
Inputs/Outputs
• Accepts two differential or single-ended inputs
• LVPECL, LVDS, CML, HCSL, LVCMOS
• Glitch-free switching of references
• On-chip input termination and biasing for AC
coupled inputs
• Six precision LVDS outputs
• Operating frequency up to 750 MHz
Power
• Option for 2.5 V or 3.3 V power supply
• Current consumption of 97 mA
• On-chip Low Drop Out (LDO) Regulator for superior
power supply rejection
Performance
• Ultra low additive jitter of 165 fs RMS
Applications
• General purpose clock distribution
• Low jitter clock trees
• Logic translation
• Clock and data signal restoration
• Redundant clock distribution
• Wired communications: OTN, SONET/SDH, GE,
10 GE, FC and 10G FC
• Wireless communications
• High performance micro-processor clock
distribution
November 2012
Figure 1 - Functional Block Diagram
clk0_p
clk0_n
ctrl0
vt0
sel
Termination
and Bias
clk1_p
clk1_n
ctrl1
vt1
Termination
and Bias
Control
out5_p
out5_n
out4_p
out4_n
out3_p
out3_n
out2_p
out2_n
out1_p
out1_n
out0_p
out0_n
Buffer
ZL40221
Precision 2:6 LVDS Fanout Buffer with Glitch-
free Input Reference Switching
and On-Chip Input Termination
Data Sheet
Ordering Information
ZL40221LDG1 32 Pin QFN Trays
ZL40221LDF1 32 Pin QFN Tape and Reel
Matte Tin
Package size: 5 x 5 mm
-40oC to +85oC
ZL40221 Data Sheet
Table of Contents
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Microsemi Corporation
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.0 Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.0 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Clock Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1.1 Clock Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1.2 Clock Input Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 Device Additive Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4.1 Sensitivity to power supply noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4.2 Power supply filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4.3 PCB layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.0 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.0 Performance Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.0 Typical Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.0 Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.0 Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
ZL40221 Data Sheet
List of Figures
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Microsemi Corporation
Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3 - Simplified Diagram of input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4 - Output During Clock Switch - Both Clocks Running . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5 - Clock Input - LVPECL - DC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6 - Clock Input - LVPECL - AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7 - Clock Input - LVDS - DC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 8 - Clock Input - LVDS - AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 9 - Clock Input - CML- AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 10 - Clock Input - HCSL- AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 11 - Clock Input - AC-coupled Single-Ended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 12 - Clock Input - DC-coupled 3.3V CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 13 - Simplified LVDS Output Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 14 - LVDS DC Coupled Termination (Internal Receiver Termination) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 15 - LVDS DC Coupled Termination (External Receiver Termination) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 16 - LVDS AC Coupled Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 17 - LVDS AC Output Termination for CML Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 18 - Additive Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 19 - Decoupling Connections for Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 20 - Differential Voltage Parameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 21 - Input To Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
ZL40221 Data Sheet
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Microsemi Corporation
1.0 Package Description
The device is packaged in a 32 pin QFN
26
28
30
32
12
10
8
64
2
vdd
out5_p
out4_n
out5_n
NC
vt0
clk0_n
clk0_p
out1_n
sel
out0_n
out1_p
gnd
out3_n
vdd
out2_p
14
16
18
2224 20
gnd
vdd
out0_p
clk1_p
out2_n
ctrl1
out3_p
vdd
clk1_n
out4_p
gnd
ctrl0
gnd (E-pad)
vt1
vdd
gnd
vdd
Figure 2 - Pin Connections
ZL40221 Data Sheet
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Microsemi Corporation
2.0 Pin Description
Pin # Name Description
1, 4,
5, 8
clk0_p, clk0_n,
clk1_p, clk1_n
Differential Input (Analog Input). Differential (or singled ended) input signals. For all
input signal configuration see Section 3.1, “Clock Inputs“.
2, 6 vt0, vt1 On-Chip Input Termination Node (Analog). Center tap between internal 50 Ohm
termination resistors.
For a DC coupled LVPECL input connect this pin through a resistor to ground; 50 Ohms
for 3.3V LVPECL or 20 Ohms for 2.5V LVPECL.
For a DC coupled LVDS input or for an AC coupled differential input, leave this pin
unconnected.
3, 7 ctrl0, ctrl1 Digital Control for On-Chip Input Termination (Input). Selects differential input mode;
0: DC coupled LVPECL or LVDS modes
1: AC coupled differential modes
These pins are internally pulled down to GND.
29, 28,
27, 26,
22, 21,
20, 19,
15, 14,
13, 12
out0_p, out0_n
out1_p, out1_n
out2_p, out2_n
out3_p, out3_n
out4_p, out4_n
out5_p, out5_n
Differential Output (Analog Output). Differential outputs.
11, 16,
18, 23,
25, 30
vdd Positive Supply Vo ltage. 2.5VDC or 3.3 VDC nominal.
9, 17,
24, 32
gnd Ground. 0 V.
31 sel Input Select (Input). Selects the reference input that is buffered;
0: clk0
1: clk1
This pin is internally pulled down to GND.
10 NC No Connection. Leave unconnected.
ZL40221 Data Sheet
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Microsemi Corporation
3.0 Functional Description
he ZL40221 is an LVDS clock fanout buffer with six output clock drivers capable of operating at frequencies up to
750MHz.
The ZL40221 provides an internal input termination network for DC and AC coupled inputs; optional input biasing
for AC coupled inputs is also provided. The ZL40221 can accept DC or AC coupled LVPECL and LVDS input
signals, AC coupled CML or HCSL input signals, and single ended signals. A pin compatible device with external
termination is also available.
The ZL40221 is designed to fan out low-jitter reference clocks for wired or optical communications applications
while adding minimal jitter to the clock signal. An internal linear power supply regulator and bulk capacitors
minimize additive jitter due to power supply noise. The device operates from 2.5V+/-5% or 3.3V+/-5% supply. Its
operation is guaranteed over the industrial temperature range -40°C to +85°C.
The device block diagram is shown in Figure 1; its operation is described in the following sections.
3.1 Clock Inputs
The device has a differential input equipped with two on-chip 50 Ohm termination resistors arranged in series with a
center tap. The input can accept many differential and single-ended signals with AC or DC coupling as appropriate.
A control pin is available to enable internal biasing for AC coupled inputs. A block diagram of the input stage is in
Figure 3.
Receiver
clk_n
50
clk_p
Vt
50
Bias
ctrl
Figure 3 - Simplified Diagram of input stage
3.1.1 Clock Input Selection
The select line chooses which input clock is routed to the outputs.
Table 1 - Input Selection
Sel Active Input
0 clk0
1clk1
The following figure shows the expected clock switching performance. The output stops at the first falling edge of
the initial clock after the select pin changes state. During switching there will be a short time when the output clock
is not toggling. After this delay, the output will start toggling again with a rising edge of the newly selected clock.
This behavior is independent of the frequencies of the input clocks. For instance, the two clocks could be at
different frequencies and the behavior would still be consistent with this figure.
2 µs
clk0
clk1
sel
outn
1
0
ZL40221 Data Sheet
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Microsemi Corporation
Figure 4 - Output During Clock Switch - Both Clocks Running
3.1.2 Clock Input Terminations
This following figures give the components values and configuration for the various circuits compatible with the
input stage and the use of the Vt and ctrl pins in each case.
In the following diagrams were the ctrl pin is ’1’ and the Vt pin is not connected, the Vt pin can be instead connected
to VDD with a capacitor. A capacitor can also help in Figure 5 between Vt and VDD. This capacitor will minimize the
noise at the point between the two internal termination resistors and improve the overall performance of the device.
LVPECL
Driver
R
VDD_driver VDD
Z
o
= 50 Ohms
Z
o
= 50 Ohms
c
l
k
_
p
c
l
k
_
n
V
t
C
t
r
l
clk_p
clk_n
Vt
Ctrl
“0”
For 3.3 V: R= 50 Ohms
For 2.5 V: R= 22 Ohms
22 Ohms
22 Ohms
Figure 5 - Clock Input - LVPECL - DC Coupled
LVPECL
Driver
VDD_driver VDD
Z
o
= 50 Ohms
Z
o
= 50 Ohms
clk_p
clk_n
Vt
Ctrl
“1”
For 3.3 V: R= 150 Ohms
For 2.5 V: R= 85 Ohms
NC
RR
22 Ohms
22 Ohms
LVDS
Driver
VDD_driver VDD
Z
o
= 50 Ohms
Z
o
= 50 Ohms
clk_p
clk_n
Vt
Ctrl
“0”
NC
ZL40221 Data Sheet
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Microsemi Corporation
Figure 6 - Clock Input - LVPECL - AC Coupled
Figure 7 - Clock Input - LVDS - DC Coupled
LVDS
Driver
VDD_driver VDD
Zo= 50 Ohms
Zo= 50 Ohms
clk_p
clk_n
Vt
Ctrl
“1”
NC
R
For VDD_driver = 3.3 V: R= 900 Ohms
For VDD_driver = 2.5 V: R = 680 Ohms
Note: This R is only needed to provide a DC
path for the LVDS driver. See driver data
sheet for more information.
CML
Driver
VDD_driver VDD
Z
o
= 50 Ohms
Z
o
= 50 Ohms
clk_p
clk_n
Vt
Ctrl
“1”
R= 50 Ohms
NC
RR
ZL40221 Data Sheet
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Microsemi Corporation
Figure 8 - Clock Input - LVDS - AC Coupled
Figure 9 - Clock Input - CML- AC Coupled
HCSL
Driver
VDD_driver VDD
Z
o
= 50 Ohms
Z
o
= 50 Ohms
clk_p
clk_n
Vt
Ctrl
“1”
R= 50 Ohms
NC
RR
CMOS
Driver
VDD_driver
VDD
Z
o
= 50 Ohms clk_p
clk_n
Vt
Ctrl
“1”
ZL40221 Data Sheet
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Microsemi Corporation
Figure 10 - Clock Input - HCSL- AC Coupled
Figure 11 - Clock Input - AC-coupled Single-Ended
CMOS
Driver
VDD_driver
VDD
Z
o
= 50 Ohms clk_p
clk_n
Vt
Ctrl
“1”
NC
ZL40221 Data Sheet
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Microsemi Corporation
Figure 12 - Clock Input - DC-coupled 3.3V CMOS
ZL40221 Data Sheet
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Microsemi Corporation
3.2 Clock Outputs
LVDS has lower signal swing than LVPECL which results in a low power consumption. A simplified diagram for the
LVDS output stage is shown in Figure 13.
VDD
3 mA
Output
-
+
+
-
Figure 13 - Simplified LVDS Output Driver
The methods to terminate the ZL40221 drivers are shown in the following figures.
LVDS
Receiver
VDD VDD_Rx
Zo= 50 Ohms
Zo= 50 Ohms
ZL40221
clk_p
clk_n
Figure 14 - LVDS DC Coupled Termination (Internal Receiver Termination)
LVDS
Receiver
VDD VDD_Rx
Zo= 50 Ohms
Zo= 50 Ohms
ZL40221
clk_p
clk_n
100 Ohms
Figure 15 - LVDS DC Coupled Termination (External Receiver Termination)
LVDS
Receiver
VDD VDD_Rx
Zo= 50 Ohms
Zo= 50 Ohms
ZL40221
clk_p
clk_n
100 Ohms
R2
VDD_Rx
R1 R1
R2
Note: R1 and R2 values and need for external termination
depend on the specification of the LVDS receiver
Figure 16 - LVDS AC Coupled Termination
ZL40221 Data Sheet
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Microsemi Corporation
ZL40221 Data Sheet
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Microsemi Corporation
Figure 17 - LVDS AC Output Termination for CML Inputs
CML
Receiver
VDD
Zo= 50 Ohms
Zo= 50 Ohms
ZL40221
clk_p
clk_n
VDD_Rx
50 Ohms
50 Ohms
ZL40221 Data Sheet
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Microsemi Corporation
3.3 Device Addi tive Ji tter
The ZL40221 clock fanout buffer is not intended to filter clock jitter. The jitter performance of this type of device is
characterized by its additive jitter. Additive jitter is the jitter the device would add to a hypothetical jitter-free clock as
it passes through the device. The additive jitter of the ZL40221 is random and as such it is not correlated to the jitter
of the input clock signal.
The square of the resultant random RMS jitter at the output of the ZL40221 is equal to the sum of the squares of the
various random RMS jitter sources including: input clock jitter; additive jitter of the buffer; and additive jitter due to
power supply noise. There may be additional deterministic jitter sources, but they are not shown in Figure 18.
+
Jin
2
Jadd
2Jps
2
Jin = Random input clock jitter (RMS)
Jadd = Additive jitter due to the device (RMS)
Jps = Additive jitter due to power supply noise (RMS)
Jout = Resultant random output clock jitter (RMS)
+Jout
2= Jin
2+Jadd
2+Jps
2
Figure 18 - Additive Jitter
ZL40221 Data Sheet
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Microsemi Corporation
3.4 Power Supply
This device operates with either a 2.5V supply or 3.3V supply.
3.4.1 Sensitivity to power supply noise
Power supply noise from sources such as switching power supplies and high-power digital components such as
FPGAs can induce additive jitter on clock buffer outputs. The ZL40221 is equipped with an on-chip linear power
regulator and on-chip bulk capacitors to minimize additive jitter due to power supply noise. The on-chip measures in
combination with the simple recommended power supply filtering and PCB layout minimize additive jitter from
power supply noise.
3.4.2 Power supply filtering
For optimal jitter performance, the ZL40221 should be isolated from the power planes connected to its power
supply pins as shown in Figure 19.
• 10 µF capacitors should be size 0603 or size 0805 X5R or X7R ceramic, 6.3 V minimum rating
• 0.1 µF capacitors should be size 0402 X5R ceramic, 6.3 V minimum rating
• Capacitors should be placed next to the connected device power pins
VDD
0.15 Ohms
10 µF
0.1 µF
0.1 µF
0.1 µF
ZL40221
11
16
18
23
0.1 µF
10 µF
25
30
Figure 19 - Decoupling Connections for Power Pins
3.4.3 PCB layout considerations
The power supply filtering shown in Figure 19 can be implemented either as a plane island, or as a routed power
topology with equal effect.
Absolute Maximum Ratings*
Parameter Sym. Min. Max. Units
1Supply voltage VDD_R -0.5 4.6 V
2Voltage on any digital pin VPIN -0.5 VDD V
3LVPECL output current Iout 30 mA
4Soldering temperature T260 °C
5Storage temperature TST -55 125 °C
6Junction temperature Tj125 °C
7Voltage on input pin Vinput VDD V
8Input capacitance each pin Cp500 fF
ZL40221 Data Sheet
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Microsemi Corporation
4.0 AC and DC Electrical Characteristics
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
* Voltages are with respect to ground (GND) unless otherwise stated
Recommended Operating Conditions*
Characteristics Sym. Min. Typ. Max. Units
1Supply voltage 2.5 V mode VDD25 2.375 2.5 2.625 V
2Supply voltage 3.3 V mode VDD33 3.135 3.3 3.465 V
3Operating temperature TA-40 25 85 °C
* Voltages are with respect to ground (GND) unless otherwise stated
DC Electrical Chara cte ri st ic s - C urrent Con s um pt io n
Characteristics Sym. Min. Typ. Max. Units Notes
1Supply current LVDS drivers -
loaded (all outputs are active)
Idd_load 97 mA
DC Electrical Chara ct e ri stics - Inputs and outputs - for 2.5/3.3 V sup p ly
Characteristics Sym. Min. Typ. Max. Units Notes
1CMOS control logic high-level input VCIH 0.7*VDD V
2CMOS control logic low-level input VCIL 0.3*VDD V
3CMOS control logic Input leakage
current
IIL 1µA VI = VDD or 0 V
4Differential input voltage difference VID 0.25 1 V
5Differential input common mode VCM 1.1 1.6 Vfor 2.5 V
6Differential input common mode VCM 1.1 2.0 Vfor 3.3 V
7Differential input resistance VIR 80 100 120 ohm
ZL40221 Data Sheet
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Microsemi Corporation
* The VOD parameter was measured from 125 MHz to 750 MHz.
Figure 20 - Differentia l Voltage Parameter
* Supply voltage and operating temperature are as per Recommended Operating Conditions
Input
tP
tREFW
tpd
tREFW
Output
Figure 21 - Input To Output Timing
8LVDS output differential voltage* VOD 0.25 0.30 0.40 V
9LVDS output common mode VCM 1.1 1.25 1.375 V
2*VOD
VOD
AC Electrical Characteristics* - Inputs and Outputs (see Figure 21) - for 2.5/3.3 V supply.
Characteristics Sym. Min. Typ. Max. Units Notes
1Maximum Operating Frequency 1/tp750 MHz
2Input to output clock propagation delay tpd 0 1 2 ns
3Output to output skew tout2out 80 150 ps
4Part to part output skew tpart2part 120 300 ps
5Output clock Duty Cycle degradation tPWH/ tPWL -5 0 5 Percent
6LVDS Output slew rate rsl 0.55 V/ns
7Reference transition time tswitch 2 3 us
DC Electrical Chara ct e ri stics - Inputs and outputs - for 2.5/3.3 V sup p ly
Characteristics Sym. Min. Typ. Max. Units Notes
Additive Jitter at 2.5 V*
Output Frequency (MHz) Jitter
Measurement
Filter
Typical
RMS (fs) Notes
1125 12 kHz - 20 MHz 229
2212.5 12 kHz - 20 MHz 217
3311.04 12 kHz - 20 MHz 194
4425 12 kHz - 20 MHz 186
5500 12 kHz - 20 MHz 169
6622.08 12 kHz - 20 MHz 165
7750 12 kHz - 20 MHz 178
Additive Jitter at 3.3 V*
Output Frequency (MHz) Jitter
Measurement
Filter
Typical
RMS (fs) Notes
1125 12 kHz - 20 MHz 231
2212.5 12 kHz - 20 MHz 217
3311.04 12 kHz - 20 MHz 196
4425 12 kHz - 20 MHz 190
5500 12 kHz - 20 MHz 173
6622.08 12 kHz - 20 MHz 167
7750 12 kHz - 20 MHz 181
ZL40221 Data Sheet
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Microsemi Corporation
5.0 Performance Characterization
*The values in this table were taken with an approximate slew rate of 0.8 V/ns.
*The values in this table were taken with an approximate slew rate of 0.8 V/ns.
Additive jitter from a power supply tone*
Carrier
frequency Parameter Typical Units Notes
125 25 mV
at 100 kHz
41 fs RMS
750 25 mV
at 100 kHz
43 fs RMS
* The values in this table are the additive periodic jitter caused by an interfering tone typically caused by a switching power supply. For this test,
measurements were taken over the full temperature and voltage range for VDD = 3.3 V. The magnitude of the interfering tone is measured at the
DUT.
ZL40221 Data Sheet
20
Microsemi Corporation
6.0 Typ ical Behavior
Typical Waveform at 155.52 MHz VOD vs Frequency
Power Supply Tone Frequency versus PSRR Power Supply Tone Magnitude versus PSRR
Propogation Delay versus Temperature
Note: This is for a single device. For more details, see the
characterization section.
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
0 5 10 15 20
Voltage
Time (ns)
0.3
0.31
0.32
0.33
0.34
0.35
0 100 200 300 400 500 600 700 800
VOD
Frequency (MHz)
-90
-85
-80
-75
-70
-65
-60
100 150 200 250 300 350 400 450 500
PSRR (dBc)
Tone Frequency (kHz)
125 MHz
212.5 MHz
425 MHz
750 MHz
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
20 30 40 50 60 70 80 90 100
PSRR (dBc)
Tone Magnitude (mV)
125 MHz
212.5 MHz
425 MHz
750 MHz
0.6
0.65
0.7
0.75
0.8
0.85
0.9
-40 -20 0 20 40 60 80 100
Delay (ns)
Temperature ( C)
ZL40221 Data Sheet
21
Microsemi Corporation
7.0 Package Characteristics
Thermal Data
Parameter Symbol Test Condition Value Unit
Junction to Ambient Thermal Resistance ΘJA Still Air
1 m/s
2 m/s
37.4
33.1
31.5
oC/W
Junction to Case Thermal Resistance ΘJC 24.4 oC/W
Junction to Board Thermal Resistance ΘJB 19.5 oC/W
Maximum Junction Temperature* Tjmax 125 oC
Maximum Ambient Temperature TA85 oC
ZL40221 Data Sheet
22
Microsemi Corporation
8.0 Mechanical Drawing
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