K7B403625B K7B403225B K7B401825B Preliminary 128Kx36 & 128Kx32 & 256Kx18 Synchronous SRAM Document Title 128Kx36 & 128Kx32 & 256Kx18-Bit Synchronous Burst SRAM Revision History History Draft Date Remark 0.0 1. Initial draft May. 15. 2001 Preliminary 0.1 1. Changed DC parameters Icc ; from 300mA to 250mA at -65, from 280mA to 230mA at -75, from 260mA to 210mA at -80, from 240mA to 190mA at -90, June. 12. 2001 Preliminary Aug. 11. 2001 Preliminary Rev. No. Icc ; from 140mA from 130mA from 120mA from 110mA 0.2 to to to to 130mA at -65, 120mA at -75, 110mA at -80, 100mA at -90, ISB1 ; from 100mA to 80mA 1. Add x32 org. and industrial temperature The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- Aug 2001 Rev 0.2 K7B403625B K7B403225B K7B401825B Preliminary 128Kx36 & 128Kx32 & 256Kx18 Synchronous SRAM 4Mb SB/SPB Synchronous SRAM Ordering Information Org. Part Number K7B401825B-QC(I)65/75/80 Speed FT ; Access Time(ns) Pipelined ; Cycle Time(MHz) SB 3.3 6.5/7.5/8.0 ns 3.3 167/138 MHz SPB(2E1D) 3.3 300/275/250/225/200 MHz SB 3.3 6.5/7.5/8.0 ns K7A403200B-QC(I)16/14 SPB(2E1D) 3.3 167/138 MHz K7A403209B-QC(I)30/27/25/22/20 SPB(2E1D) 3.3 300/275/250/225/200 MHz K7A403201B-QC(I)16/14 SPB(2E2D) 3.3 167/138/ MHz K7A401809B-QC(I)30/27/25/22/20 K7B403225B-QC(I)65/75/80 K7B403625B-QC(I)65/75/80 128Kx36 VDD SPB(2E1D) 256Kx18 K7A401800B-QC(I)16/14 128Kx32 Mode SB 3.3 6.5/7.5/8.0 ns K7A403600B-QC(I)16/14 SPB(2E1D) 3.3 167/138 MHz K7A403609B-QC(I)30/27/25/22/20 SPB(2E1D) 3.3 300/275/250/225/200 MHz K7A403601B-QC(I)16/14 SPB(2E2D) 3.3 167/138 MHz -2- PKG Q (100TQFP) Temp C (Commercial Temperature Range) I: (Industrial Temperature Range) Aug 2001 Rev 0.2 K7B403625B K7B403225B K7B401825B Preliminary 128Kx36 & 128Kx32 & 256Kx18 Synchronous SRAM 128Kx36 & 128Kx32 & 256Kx18-Bit Synchronous Burst SRAM FEATURES GENERAL DESCRIPTION * Synchronous Operation. * On-Chip Address Counter. * Write Self-Timed Cycle. * On-Chip Address and Control Registers. * V DD= 3.3V+0.3V/-0.165V Power Supply. * V DDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O. * 5V Tolerant Inputs except I/O Pins. * Byte Writable Function. * Global Write Enable Controls a full bus-width write. * Power Down State via ZZ Signal. * Asynchronous Output Enable Control. * ADSP, ADSC, ADV Burst Control Pins. * LBO Pin allows a choice of either a interleaved burst or a linear burst. * Three Chip Enables for simple depth expansion with No Data Contention. * TTL-Level Three-State Output. * 100-TQFP-1420A * Operating in commeical and industrial temperature range. The K7B403625B, K7B403225B and K7B401825B are 4,718,592 bits Synchronous Static Random Access Memory designed to support zero wait state performance for advanced Pentium/Power PC based system. And with CS 1 high, ADSP is blocked to control signals. It can be organized as 128K(256K) words of 36(18) bits. And it integrates address and control registers, a 2-bit burst address counter and high output drive circuitry onto a single integrated circuit for reduced components counts implementation of high performance cache RAM applications. Write cycles are internally self-timed and synchronous. The self-timed write feature eliminates complex off chip write pulse shaping logic, simplifying the cache design and further reducing the component count. Burst cycle can be initiated with either the address status processor(ADSP) or address status cache controller(ADSC) inputs. Subsequent burst addresses are generated internally in the systems burst sequence and are controlled by the burst address advance(ADV) input. ZZ pin controls Power Down State and reduces Stand-by current regardless of CLK. The K7B403625B, K7B403225B and K7B401825B are implemented with SAMSUNGs high performance CMOS technology and is available in a 100pin TQFP package. Multiple power and ground pins are utilized to minimize ground bounce. FAST ACCESS TIMES PARAMETER Symbol -65 -75 -80 Unit Cycle Time tCYC 7.5 8.5 10 ns Clock Access Time tCD 6.5 7.5 8.0 ns Output Enable Access Time tOE 3.5 3.5 4.0 ns LOGIC BLOCK DIAGRAM CLK LBO BURST CONTROL LOGIC CONTROL REGISTER ADV ADSC BURST ADDRESS A0~A 1 COUNTER 128Kx36/32 , 256Kx18 MEMORY ARRAY A0~A1 A0~A16 or A0~A17 ADSP ADDRESS REGISTER A2~A16 or A2~A17 DATA-IN REGISTER CONTROL REGISTER CS1 CS2 CS2 GW BW OUTPUT BUFFER CONTROL LOGIC WEx (x=a,b,c,d or a,b) OE ZZ DQa0 ~ DQd7 DQPa ~ DQPd 36/32 or 18 or DQa0 ~ DQb7 DQPa ~ DQPb -3- Aug 2001 Rev 0.2 K7B403625B K7B403225B K7B401825B Preliminary 128Kx36 & 128Kx32 & 256Kx18 Synchronous SRAM A6 A7 CS1 CS2 WEd WEc WEb WEa CS2 VDD VSS CLK GW BW OE ADSC ADSP ADV A8 A9 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 100 Pin TQFP (20mm x 14mm) 48 49 50 A15 A16 46 A12 A14 45 A11 47 44 A10 A13 43 41 VDD N.C. 40 VSS 42 39 N.C. N.C. 38 N.C. 35 A2 37 34 A3 A0 33 A4 36 32 A1 31 K7B403625B(128Kx36) /K7B403225B(128Kx32) A5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LBO DQPc/NC DQc 0 DQc 1 V DDQ V SSQ DQc 2 DQc 3 DQc 4 DQc 5 V SSQ V DDQ DQc 6 DQc 7 N.C. V DD N.C. V SS DQd 0 DQd 1 V DDQ V SSQ DQd 2 DQd 3 DQd 4 DQd 5 V SSQ V DDQ DQd 6 DQd 7 DQPd/NC 100 PIN CONFIGURATION(TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPb/NC DQb7 DQb6 V DDQ V SSQ DQb5 DQb4 DQb3 DQb2 V SSQ V DDQ DQb1 DQb0 V SS N.C. V DD ZZ DQa7 DQa6 V DDQ V SSQ DQa5 DQa4 DQa3 DQa2 V SSQ V DDQ DQa1 DQa0 DQPa/NC PIN NAME SYMBOL A 0 - A 16 ADV ADSP ADSC CLK CS 1 CS 2 CS 2 WE x (x=a,b,c,d) OE GW BW ZZ LBO PIN NAME TQFP PIN NO. Address Inputs 32,33,34,35,36,37 44,45,46,47,48,49 50,81,82,99,100 Burst Address Advance 83 Address Status Processor 84 Address Status Controller 85 Clock 89 Chip Select 98 Chip Select 97 Chip Select 92 Byte Write Inputs 93,94,95,96 Output Enable Global Write Enable Byte Write Enable Power Down Input Burst Mode Control 86 88 87 64 31 SYMBOL TQFP PIN NO. Power Supply(+3.3V) Ground 15,41,65,91 17,40,67,90 N.C. No Connect 14,16,38,39,42,43,66 DQa0~a 7 DQb0~b 7 DQc0 ~c7 DQd0~d 7 DQPa~P d /NC V DDQ Data Inputs/Outputs 52,53,56,57,58,59,62,63 68,69,72,73,74,75,78,79 2,3,6,7,8,9,12,13 18,19,22,23,24,25,28,29 51,80,1,30 Output Power Supply (2.5V or 3.3V) Output Ground 4,11,20,27,54,61,70,77 V SSQ -4- PIN NAME V DD V SS 5,10,21,26,55,60,71,76 Aug 2001 Rev 0.2 K7B403625B K7B403225B K7B401825B Preliminary 128Kx36 & 128Kx32 & 256Kx18 Synchronous SRAM A6 A7 CS 1 CS 2 N.C. N.C. WEb WEa CS 2 V DD V SS CLK GW BW OE ADSC ADSP ADV A8 A9 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 100 Pin TQFP (20mm x 14mm) 47 48 49 50 A 14 A 15 A 16 A 17 41 V DD 46 40 V SS A 13 39 N.C. 45 38 N.C. A 12 37 A0 44 36 A1 A 11 35 A2 43 34 A3 N.C. 33 A4 42 32 N.C. 31 K7B401825B(256Kx18) A5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LBO N.C. N.C. N.C. V DDQ V SSQ N.C. N.C. DQb0 DQb1 V SSQ V DDQ DQb2 DQb3 N.C. V DD N.C. V SS DQb4 DQb5 V DDQ V SSQ DQb6 DQb7 DQPb N.C. V SSQ V DDQ N.C. N.C. N.C. 100 PIN CONFIGURATION (TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A 10 N.C. N.C. V DDQ V SSQ N.C. DQPa DQa 7 DQa 6 V SSQ V DDQ DQa 5 DQa 4 V SS N.C. V DD ZZ DQa 3 DQa 2 V DDQ V SSQ DQa 1 DQa 0 N.C. N.C. V SSQ V DDQ N.C. N.C. N.C. PIN NAME SYMBOL PIN NAME TQFP PIN NO. A 0 - A 17 Address Inputs ADV ADSP ADSC CLK CS 1 CS 2 CS 2 W Ex (x=a,b) OE GW BW ZZ LBO Burst Address Advance Address Status Processor Address Status Controller Clock Chip Select Chip Select Chip Select Byte Write Inputs 32,33,34,35,36,37, 44,45,46,47,48,49, 50,80,81,82,99,100 83 84 85 89 98 97 92 93,94 Output Enable Global Write Enable Byte Write Enable Power Down Input Burst Mode Control 86 88 87 64 31 SYMBOL PIN NAME TQFP PIN NO. V DD V SS N.C. Power Supply(+3.3V) Ground No Connect 15,41,65,91 17,40,67,90 1,2,3,6,7,14,16,25,28,29, 30,38,39,42,43,51,52,53, 56,57,66,75,78,79,95,96 DQa 0~a 7 DQb 0~b 7 DQPa, Pb V DDQ Data Inputs/Outputs 58,59,62,63,68,69,72,73 8,9,12,13,18,19,22,23 74,24 4,11,20,27,54,61,70,77 V SSQ -5- Output Power Supply (2.5V or 3.3V) Output Ground 5,10,21,26,55,60,71,76 Aug 2001 Rev 0.2 K7B403625B K7B403225B K7B401825B Preliminary 128Kx36 & 128Kx32 & 256Kx18 Synchronous SRAM FUNCTION DESCRIPTION The K7B4036/3225B and K7B401825B are synchronous SRAM designed to support the burst address accessing sequence of the Pentium and Power PC based microprocessor. All inputs (with the exception of OE , LBO and ZZ) are sampled on rising clock edges. The start and duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins. When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally. Read cycles are initiated with ADSP (or ADSC) using the new external address clocked into the on-chip address register when both GW and BW are high or when B W is low and WEa, WEb, WE c, and WEd are high. When ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE . the data of cell array accessed by the current address are projected to the output pins. Write cycles are also initiated with ADSP(or ADSC) and are differentiated into two kinds of operations; All byte write operation and individual byte write operation. All byte write occurs by enabling GW (independent of BW and WEx.), and individual byte write is performed only when GW is high and BW is low. In K7B403625B, a 128Kx36 organization, WE a controls DQa0 ~ DQa7 and DQPa, WEb controls DQb0 ~ DQb7 and DQPb, WEc controls DQc0 ~ DQc7 and DQPc and WEd controls DQd0 ~ DQd7 and DQPd. CS 1 is used to enable the device and conditions internal use of ADSP and is sampled only when a new external address is loaded. ADV is ignored at the clock edge when ADSP is asserted, but can be sampled on the subsequent clock edges. The address increases internally for the next access of the burst when ADV is sampled low. Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state of the LBO pin. When this pin is Low, linear burst sequence is selected. And this pin is High, Interleaved burst sequence is selected. BURST SEQUENCE TABLE LBO PIN (Interleaved Burst) Case 1 HIGH A1 0 0 1 1 First Address Fourth Address Case 2 A0 0 1 0 1 A1 0 0 1 1 Case 3 A0 1 0 1 0 A1 1 1 0 0 Case 4 A0 0 1 0 1 A1 1 1 0 0 A0 1 0 1 0 Note : 1. LBO pin must be tied to high or low, and floating state must not be allowed. BURST SEQUENCE TABLE LBO PIN (Linear Burst) Case 1 LOW A1 0 0 1 1 First Address Fourth Address Case 2 A0 0 1 0 1 A1 0 1 1 0 Case 3 A0 1 0 1 0 A1 1 1 0 0 Case 4 A0 0 1 0 1 A1 1 0 0 1 A0 1 0 1 0 Note : 1. LBO pin must be tied to high or low, and floating state must not be allowed. ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2) : OPERATION ZZ OE I/O STATUS Sleep Mode H X High-Z L L DQ L H High-Z Write L X Din, High-Z Deselected L X High-Z Read Notes 1. X means "Don't Care". 2. ZZ pin is pulled down internally 3. For write cycles that following read cycles, the output buffersmust be disabled with OE, otherwise data bus contention will occur. 4. Sleep Mode means power down state of which stand-by current does not depend on cycle time. 5. Deselected means power down state of which stand-by current depends on cycle time. -6- Aug 2001 Rev 0.2 K7B403625B K7B403225B K7B401825B Preliminary 128Kx36 & 128Kx32 & 256Kx18 Synchronous SRAM TRUTH TABLES SYNCHRONOUS TRUTH TABLE CS 1 CS2 CS 2 ADV WRITE CLK ADDRESS ACCESSED OPERATION H X X ADSP ADSC X L X X N/A Not Selected L L X L X X X N/A Not Selected L X H L X X X N/A Not Selected L L X X L X X N/A Not Selected L X H X L X X N/A Not Selected L H L L X X X External Address Begin Burst Read Cycle L H L H L X L External Address Begin Burst Write Cycle L H L H L X H External Address Begin Burst Read Cycle X X X H H L H Next Address Continue Burst Read Cycle H X X X H L H Next Address Continue Burst Read Cycle X X X H H L L Next Address Continue Burst Write Cycle H X X X H L L Next Address Continue Burst Write Cycle X X X H H H H Current Address Suspend Burst Read Cycle H X X X H H H Current Address Suspend Burst Read Cycle X X X H H H L Current Address Suspend Burst Write Cycle H X X X H H L Current Address Suspend Burst Write Cycle Notes : 1. X means "Don t Care". 2. The rising edge of clock is symbolized by . 3. WRITE = L means Write operation in WRITE TRUTH TABLE. WRITE = H means Read operation in WRITE TRUTH TABLE. 4. Operation finally depends on status of asynchronous input pins(ZZ and OE ). WRITE TRUTH TABLE( x36/32) GW BW WEa WEb WEc WE d OPERATION H H X X H L H H X X READ H H READ H L L H L H H H H WRITE BYTE a L H H WRITE BYTE b H L H L H H L L WRITE BYTE c and d L L L L WRITE ALL BYTEs L X X X X X WRITE ALL BYTEs Notes : 1. X means "Dont Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK(). WRITE TRUTH TABLE(x18) GW BW WEa WEb OPERATION H H X X READ H L H H READ H L L H WRITE BYTE a H L H L WRITE BYTE b H L L L WRITE ALL BYTEs L X X X WRITE ALL BYTEs Notes : 1. X means "Dont Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK(). -7- Aug 2001 Rev 0.2 K7B403625B K7B403225B K7B401825B Preliminary 128Kx36 & 128Kx32 & 256Kx18 Synchronous SRAM ABSOLUTE MAXIMUM RATINGS* PARAMETER Voltage on V DD Supply Relative to V SS Voltage on V DDQ Supply Relative to V SS SYMBOL RATING UNIT V DD -0.3 to 4.6 V V DDQ V DD V Voltage on Input Pin Relative to VSS V IN -0.3 to V DD+0.3 V Voltage on I/O Pin Relative to VSS V IO -0.3 to V DDQ+0.3 V Power Dissipation Storage Temperature Operating Temperature PD 1.4 W T STG -65 to 150 C Commercial TOPR 0 to 70 C Industrial TOPR -40 to 85 C T BIAS -10 to 85 C Storage Temperature Range Under Bias *Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING CONDITIONS at 3.3V I/O (0C T A70C) PARAMETER Supply Voltage Ground SYMBOL MIN Typ. MAX UNIT V DD 3.135 3.3 3.6 V V DDQ 3.135 3.3 3.6 V V SS 0 0 0 V OPERATING CONDITIONS at 2.5V I/O (0C T A 70C) PARAMETER Supply Voltage Ground SYMBOL MIN Typ. MAX UNIT V DD 3.135 3.3 3.6 V V DDQ 2.375 2.5 2.9 V V SS 0 0 0 V CAPACITANCE* (TA=25C, f=1MHz) PARAMETER Input Capacitance Output Capacitance SYMBOL TEST CONDITION MIN MAX UNIT C IN V IN=0V - 5 pF C OUT V OUT=0V - 7 pF *Note : Sampled not 100% tested. -8- Aug 2001 Rev 0.2 K7B403625B K7B403225B K7B401825B Preliminary 128Kx36 & 128Kx32 & 256Kx18 Synchronous SRAM DC ELECTRICAL CHARACTERISTICS (T A=0 to 70C, V DD=3.3V +0.3V/-0.165V) PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNIT Input Leakage Current(except ZZ) IIL V DD=Max , V I N= VSS to V DD -2 +2 A Output Leakage Current IOL Output Disabled, VOUT=VSS to V DDQ -2 +2 A - 250 ICC Device Selected, I OUT=0mA, ZZV IL, All Inputs=VIL or V IH Cycle Time tCYC min -65 Operating Current -75 - 230 -80 - 210 Device deselected, I OUT=0mA, ZZV IL, f=Max, All Inputs0.2V or V DD-0.2V -65 - 130 -75 - 120 -80 - 110 ISB Standby Current mA mA mA ISB1 Device deselected, I OUT=0mA, ZZ0.2V, f=0, All Inputs=fixed (V DD-0.2V or 0.2V) - 80 ISB2 Device deselected, IOUT=0mA, ZZ V DD-0.2V, f=Max, All InputsV IL or V I H - 50 Output Low Voltage(3.3V I/O) V OL IOL = 8.0mA - 0.4 V Output High Voltage(3.3V I/O) V OH IO H = -4.0mA 2.4 - V Output Low Voltage(2.5V I/O) V OL IOL = 1.0mA - 0.4 V Output High Voltage(2.5V I/O) V OH IO H = -1.0mA 2.0 - V Input Low Voltage(3.3V I/O) V IL -0.5* 0.8 V Input High Voltage(3.3V I/O) V IH 2.0 V DD+03** V Input Low Voltage(2.5V I/O) V IL -0.3* 0.7 V Input High Voltage(2.5V I/O) V IH 1.7 V DD+0.3** V mA * V IL (Min)=-2.0(Pulse Width tCYC/2) ** V IH (Max)=4.6(Pulse Width tCYC/2) ** In Case of I/O Pins, the Max. V IH=V DDQ +0.3V TEST CONDITIONS (VDD=3.3V+0.3V/-0.165V,VDDQ=3.3V+0.3/-0.165V or VDD=3.3V+0.3V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0 to 70C) PARAMETER VALUE Input Pulse Level(for 3.3V I/O) 0 to 3V Input Pulse Level(for 2.5V I/O) 0 to 2.5V Input Rise and Fall Time(Measured at 0.3V and 2.7V for 3.3V I/O) 1ns Input Rise and Fall Time(Measured at 0.3V and 2.1V for 2.5V I/O) 1ns Input and Output Timing Reference Levels for 3.3V I/O 1.5V Input and Output Timing Reference Levels for 2.5V I/O V DDQ/2 Output Load See Fig. 1 -9- Aug 2001 Rev 0.2 K7B403625B K7B403225B K7B401825B Preliminary 128Kx36 & 128Kx32 & 256Kx18 Synchronous SRAM Output Load(A) Dout Output Load(B) (for tLZC, tLZOE , tHZOE & tHZC) RL=50 Z0=50 30pF* +3.3V for 3.3V I/O /+2.5V for 2.5V I/O VL=1.5V for 3.3V I/O V DDQ /2 for 2.5V I/O 319 / 1667 Dout 353 / 1538 * Capacitive Load consists of all components of the test environment. 5pF* * Including Scope and Jig Capacitance Fig. 1 AC TIMING CHARACTERISTICS (TA=0 to 70C, VDD =3.3V+0.3V/-0.165V) PARAMETER -65 Symbol -75 -80 UNIT Min Max Min Max Min Max Cycle Time tCYC 7.5 - 8.5 - 10 - ns Clock Access Time tCD - 6.5 - 7.5 - 8.0 ns Output Enable to Data Valid tOE - 3.5 - 3.5 - 4.0 ns Clock High to Output Low-Z tLZC 0 - 0 - 0 - ns Output Hold from Clock High tOH 2.5 - 2.5 - 2.5 - ns Output Enable Low to Output Low-Z tLZOE 0 - 0 - 0 - ns Output Enable High to Output High-Z tHZOE - 3.5 - 3.5 - 4.0 ns Clock High to Output High-Z tHZC 2 3.5 2 3.5 2 3.5 ns Clock High Pulse Width tCH 2.5 - 3 - 4 - ns Clock Low Pulse Width tCL 2.5 - 3 - 4 - ns Address Setup to Clock High tAS 1.5 - 2.0 - 2.0 - ns Address Status Setup to Clock High tSS 1.5 - 2.0 - 2.0 - ns Data Setup to Clock High tDS 1.5 - 2.0 - 2.0 - ns Write Setup to Clock High(GW, BW, WE x) tWS 1.5 - 2.0 - 2.0 - ns Address Advance Setup to Clock High tADVS 1.5 - 2.0 - 2.0 - ns Chip Select Setup to Clock High tCSS 1.5 - 2.0 - 2.0 - ns Address Hold from Clock High tAH 0.5 - 0.5 - 0.5 - ns Address Status Hold from Clock High tSH 0.5 - 0.5 - 0.5 - ns Data Hold from Clock High tDH 0.5 - 0.5 - 0.5 - ns Write Hold from Clock High(G W, BW, WEx) tWH 0.5 - 0.5 - 0.5 - ns Address Advance Hold from Clock High tADVH 0.5 - 0.5 - 0.5 - ns Chip Select Hold from Clock High tCSH 0.5 - 0.5 - 0.5 - ns ZZ High to Power Down tPDS 2 - 2 - 2 - cycle ZZ Low to Power Up tPUS 2 - 2 - 2 - cycle Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 2. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled. 3. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state. 4. At any given voltage and temperature, tHZC is less than tLZC. - 10 - Aug 2001 Rev 0.2 - 11 - Data Out OE ADV CS WRITE ADDRESS ADSC ADSP CLOCK tCSS tAS tSS tOE Q1-1 tHZOE tADVH tWH tSS A2 tSH Q 2-1 tCD tOH Q2-2 CS = L mean s CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L a nd CS 2 = H, or CS 1 = L, an d CS2 = L Q2-3 A3 Q2-4 (ADV INSERTS WAIT STATE) BURST CONTINUED WITH NEW BASE ADDRESS tCYC tCL NOTES : WRITE = L means G W = L, o r G W = H, BW = L, WEx.= L tADVS tCSH tWS tLZOE A1 tAH tSH tCH TIMING WAVEFORM OF READ CYCLE Q 3-1 Q3-2 Q 3-3 Unde fine d Dont Care Q 3-4 tHZC K7B403625B K7B403225B K7B401825B Preliminary 128Kx36 & 128Kx32 & 256Kx18 Synchronous SRAM Aug 2001 Rev 0.2 - 12 - Data Out Data In OE ADV CS WRITE ADDRESS ADSC ADSP CLOCK Q0-3 tCSS tAS tSS Q0-4 A1 tLZOE tCSH tAH tSH D1-1 tCL tCYC tCH A2 D2-1 D2-2 (ADV SUSPENDS BURST) D2-2 D2-3 (ADSC EXTENDED BURST) TIMING WAVEFORM OF WRTE CYCLE D2-4 D3-1 A3 tDS tADVS tWS tSS D3-2 tDH tADVH tWH tSH D3-3 Un defined Do nt Care D3-4 K7B403625B K7B403225B K7B401825B Preliminary 128Kx36 & 128Kx32 & 256Kx18 Synchronous SRAM Aug 2001 Rev 0.2 - 13 - Data Out Data In OE ADV CS WRITE ADDRESS ADSP CLOCK tHZC tSS A1 tLZC tCD tSH Q1-1 tHZOE t AS A2 tCL tCYC tDS tADVS tWS tAH tCH D2-1 tDH tADVH tWH A3 tLZOE tOE Q 3-1 Q3-2 Q3-3 tOH Q3-4 TIMING WAVEFORM OF COMBINATION READ/WRTE CYCLE(ADSP CONTROLLED, ADSC=HIGH) Un defined Do nt Care K7B403625B K7B403225B K7B401825B Preliminary 128Kx36 & 128Kx32 & 256Kx18 Synchronous SRAM Aug 2001 Rev 0.2 - 14 - Data In Data Out OE ADV CS WRITE ADDRESS ADSC CLOCK tCSS tSS A1 tLZOE tOE tCSH tSH Q1-1 A2 Q2-1 A3 Q3-1 A4 Q4-1 tHZOE D5-1 A5 tDS tWS D6-1 A6 tDH tWH D7-1 A7 tWS tCD A8 tCYC tWH tCH A9 Q8-1 tCL TIMING WAVEFORM OF SINGLE READ/WRITE CYCLE(ADSC CONTROLLED, ADSP=HIGH) Aug 2001 Rev 0.2 Un defined Do nt Care Q9-1 tOH K7B403625B K7B403225B K7B401825B Preliminary 128Kx36 & 128Kx32 & 256Kx18 Synchronous SRAM - 15 - Data In Data Out OE ADV CS WRITE ADDRESS ADSP CLOCK t CSS tSS tOE tCSH t L ZOE A1 tSH Q1-1 A2 Q2-1 A3 tAS Q3-1 A4 tAH tCYC tCH A5 Q 4-1 tCL tHZOE D5-1 A6 tDS D6-1 tDH A7 D7-1 tCD A8 Q 8-1 A9 TIMING WAVEFORM OF SINGLE READ/WRITE CYCLE(ADSP CONTROLLED, ADSC=HIGH) Q 9-1 tOH Un defined Do nt Care K7B403625B K7B403225B K7B401825B Preliminary 128Kx36 & 128Kx32 & 256Kx18 Synchronous SRAM Aug 2001 Rev 0.2 - 16 - ZZ Data Out Data In OE ADV CS WRITE ADDRESS ADSC ADSP CLOCK tCSS tAS tSS A1 tLZOE tOE tCSH tAH tSH Q1-1 ZZ Setup Cycle tPDS tHZC Sleep State tPUS tCL ZZ Recovery Cycle tCYC tCH TIMING WAVEFORM OF POWER DOWN CYCLE tWS Normal Operation Mode tHZOE A2 D2-1 tWH Un defined Do nt Care D2-2 K7B403625B K7B403225B K7B401825B Preliminary 128Kx36 & 128Kx32 & 256Kx18 Synchronous SRAM Aug 2001 Rev 0.2 K7B403625B K7B403225B K7B401825B Preliminary 128Kx36 & 128Kx32 & 256Kx18 Synchronous SRAM APPLICATION INFORMATION DEPTH EXPANSION The Samsung 128Kx36 Synchronous Burst SRAM has two additional chip selects for simple depth expansion. This permits easy secondary cache upgrades from 128K depth to 256K depth without extra logic. I/O[0:71] Data Address A[0:17] A[17] A[0:16] A[17] Address CLK 64-bits Microprocessor Address CS2 CS2 CS2 ADSC CLK Data CS2 CLK Address A[0:16] 128Kx36 SB SRAM CLK ADSC WEx (Bank 1) OE OE CS1 CS1 ADV 128Kx36 SB SRAM WEx (Bank 0) Cache Controller Data ADV ADSP ADSP ADS INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing) (ADSP CONTROLLED , ADSC=HiGH) CLOCK tSS tSH ADSP tAS ADDRESS [0:n] A1 tAH A2 tWS tWH WRITE tCSS tCSH CS1 Bank 0 is selected by CS 2, and Bank 1 deselected by CS2 An+1 tADVS Bank 0 is deselected by CS2, and Bank 1 selected by CS2 tADVH ADV OE tOE Data Out (Bank 0) Data Out (Bank 1) tLZOE tHZC Q1-1 Q1-2 Q1-3 Q1-4 tCD tLZC Q2-1 Q2-2 *Notes : n = 14 32K depth, 15 64K depth, 16 128K depth, 17 256K depth - 17 - Q2-3 Q2-4 Dont Care Undefined Aug 2001 Rev 0.2 K7B403625B K7B403225B K7B401825B Preliminary 128Kx36 & 128Kx32 & 256Kx18 Synchronous SRAM APPLICATION INFORMATION DEPTH EXPANSION The Samsung 256Kx18 Synchronous Burst SRAM has two additional chip selects for simple depth expansion. This permits easy secondary cache upgrades from 256K depth to 512K depth without extra logic. I/O[0:71] Data Address A [0:18] A [18] A [18] A [0:17] Address CLK Microprocessor CS2 CS 2 CS2 ADSC CLK Address CS 2 CLK Address Data 256Kx18 SB SRAM CLK ADSC WEx OE OE CS 1 CS1 ADV Data 256Kx18 SB SRAM WEx (Bank 0) Cache Controller A [0:17] ADSP (Bank 1) ADV ADSP ADS INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing) (ADSP CONTROLLED , ADSC=HIGH) CLOCK tSS tSH ADSP tAS ADDRESS [0:n] A1 tAH A2 tWS tWH WRITE tCSS tCSH CS1 Bank 0 is selected by CS 2, and Bank 1 deselected by CS2 An+1 tADVS Bank 0 is deselected by CS2, and Bank 1 selected by CS2 tADVH ADV OE tOE Data Out (Bank 0) Data Out (Bank 1) tLZOE tHZC Q1-1 Q1-2 Q1-3 Q1-4 tCD tLZC Q2-1 Q2-2 *Notes : n = 14 32K depth, 15 64K depth, 16 128K depth, 17 256K depth - 18 - Q2-3 Q2-4 Dont Care Undefined Aug 2001 Rev 0.2 K7B403625B K7B403225B K7B401825B Preliminary 128Kx36 & 128Kx32 & 256Kx18 Synchronous SRAM PACKAGE DIMENSIONS 100-TQFP-1420A Units:millimeters/inches 0~8 22.00 0.30 0.127 +- 0.10 0.05 20.00 0.20 16.00 0.30 14.00 0.20 0.10 MAX (0.83) 0.50 #1 0.65 0.30 0.10 0.10 MAX 0.10 (0.58) 1.40 0.50 0.10 - 19 - 0.10 1.60 MAX 0.05 MIN Aug 2001 Rev 0.2