IRDCIP2005C-1 - International Rectifier

International Rectifier  233 Kansas Street

El Se

undo

CA 90245 USA

IRDCiP2005C-1

IRDCiP2005C-1: 500kHz, 60A, Single Output,

Dual Phase Synchronous Buck Converter

Featuring iP2005C and IR3623M

Overview

This reference design is capable of delivering a continuous current of 60A

without heatsink at an ambient temperature of 45ºC and airflow of 200LFM.

Fig. 4 - Fig. 17 provide performance graphs, thermal images, and waveforms.

Fig. 1 - Fig. 3 are provided to engineers as design references for implementing

an IR3623+iP2005C solution.

The components installed on this demoboard were selected based on operation

at an input voltage of 12V (+/-10%), a switching frequency of 500kHz (+/-

15%), and an output voltage of 1.2V. Major changes from these set points may

require optimizing the control loop and/or adjusting the values of input/output

filters in order to meet the user’s specific application requirements. Refer to iP2005C and IR3623 datasheets for more

information.

IRDCiP2005C-1 Recommended Operating Conditions

(refer to the iP2005C datasheet for maximum operating conditions)

Input voltage: 8.5V – 14.5V

Output voltage: 0.8 – 5V

Switching Freq: 500kHz

Output current: This reference design is capable of delivering a continuous current of 60A without heatsink at an

ambient temperature of 45ºC and airflow of 200LFM.

Demoboard Quic k Star t Guide

Initial Settings:

VOUT is set to 1.2V, but can be adjusted from 0.8V to 5V by changing the values of R11 and R15 according to the following

formula: R11 = R15 = (10k * 0.8) / (VOUT - 0.8)

The switching frequency is set to 500kHz, but can be adjusted by changing the value of R26. See Fig. 4 for the relationship

between R26 and the switching frequency.

7/8/2009

IRDCiP2005C-1

Power Up Procedure:

1. Apply input voltage across VIN and PGND.

2. If R45 is not installed, apply bias voltage across VDD and PGND.

3. Apply load across VOUT pads and PGND pads.

4. Toggle the SEQ (SW1) and EN (SW2) switches to the ON position.

5. Adjust load to desired level. See recommendations above.

www.irf.com 2

IRDCiP2005C-1

Demoboard Schematic

Fig. 1 Schematic

3 www.irf.com

IRDCiP2005C-1

Bill of Material

www.irf.com 4

IRDCiP2005C-1

Demoboard Component Placement

Fig. 2

Top Layer (Face View)

Fig. 3

Bottom Layer (Through View)

5 www.irf.com

IRDCiP2005C-1

Description of Test Points and Connectors

Jumpers

Jumper Pin Name Description

SW1 EN Board Enable ( switch Up=Off, Down=On ) - Vin pin on top

SW2 SEQ Sequence ( switch Up=Off, Down=On ) - Vin pin on top

Test Points/Connectors

Test Point Pin Name Description

T1 / T2 VIN / PGND Vin supply voltage

TP2 / TP28 VIN / PGND Vin supply voltage sense

T3 / T5 / T7 VOUT1 / PGND / PGND Channel 1 Output, connect to DC load

TP35 / TP33 VOUT1 / PGND Channel 1 Output sense

TP21 / TP37 VSW1 / PGND Channel 1 switch node / PGND test points

TP9 EN1 Channel 1 Enable test point

TP11 PWM1 Channel 1 PWM test point

TP19 CC1 Channel 1 error amplifier output

TP25 FB1 Channel 1 error amplifier non-inverting input

T4 / T6 / T9 VOUT2 / PGND / PGND Channel 2 Output, connect to DC load

TP36 / TP34 VOUT2 / PGND Channel 2 Output sense

TP22 / TP38 VSW2 / PGND Channel 2 switch node / PGND test points

TP10 EN2 Channel 2 Enable test point

TP12 PWM2 Channel 2 PWM test point

TP20 CC2 Channel 2 error amplifier output

TP26 FB2 Channel 2 error amplifier non-inverting input

TP7 / TP8 VDD / PGND iP2005C internal bias voltage test points

TP23 SYNC External frequency synchronization input

TP17 TRACK1 Channel 1 tracking input, pull-up to Vout3 if not used

TP18 TRACK2 Track2 test point

TP15 PGOOD1 Channel 1 Power good test point

TP16 PGOOD2 Channel 2 Power good test point

TP13 SS1 Channel 1 Soft start test point

TP14 SS2 Channel 2 Soft start test point

TP24 FAULT Fault monitor test point

3. Test points for Efficiency Measurement

Test Point Pin Name Description

TP1 / TP4 +VINS1 / -VOUTS1 Channel 1 Vin sense for efficiency measurement

TP3 / TP4 +VOUTS1 / -VOUTS1 Channel 1 Output sense for efficiency measurement

TP27 / TP6 +VINS2 / -VOUTS2 Channel 2 Vin sense for efficiency measurement

TP5 / TP6 +VOUTS2 / -VOUTS2 Channel 2 Output sense for efficiency measurement

www.irf.com 6

IRDCiP2005C-1

Test Results

Fig. 4 Relationship Between Switching Frequency and R26

VIN = 12V, VOUT = 1.2V, Iout = 40A, fsw = 500 kHz

Fig. 5 Power Up Sequence (C3: EN, C1: SS1, C4: VOUT)

VIN = 12V, VOUT = 1.2V, Iout = 60A, fsw = 500 kHz

Fig. 6 Power Down Sequence (C3: EN, C1: SS1, C4: VOUT)

7 www.irf.com

IRDCiP2005C-1

7 Hiccup Mode Over Current Protection (C1: SS, C4: Iout, C3: VFig. UT)

Fig. UT)

8 Hiccup Mode Over Current Protection (C1: SS, C4: Iout, C3: VO

VIN = 12V, VOUT = 1.2V, f = 500 kHz

VIN = 12V, VOUT = 1.2V, fsw = 500 kHz

VIN = 12V, VOUT = 1.2V, Iout = 20A, fsw = 500 kHz

Fig. 9 Deadtime and Ri n gin g on Switch Node

www.irf.com 8

IRDCiP2005C-1

Fig. 10 Output Vol t age DC Ripple

Fig. 2)

Fig. 11 Output Vol t age DC Ripple

12 Load Transient Response (C1: VOUT – AC, C2: Iout divided

VIN = 12V, VOUT = 1.2V, I = 20A, f = 500 kHz

VIN = 12V, VOUT = 1.2V, Iout = 20A, fsw = 500 kHz

Vp-p = 20.8 mV

VIN = 12V, VOUT = 1.2V, Iout = 0-60A, 0 . 5A/us,

Vp-p = 17 mV

out sw

fsw = 500 k z

9 www.irf.com

IRDCiP2005C-1

urrent Sharing Accuracy

Fig. 13 Bode Plot (VIN = 12V, VOUT = 1.2V, Iout = 20A)

fc = 69 kHz

PM = 49

ested by measuring the DC voltage across the two inductors at the following

UT = 1.2V; Iout = 20 – 60A; TA = 25oC; no airflow. The test results are shown

Iout (A) (mV)

The Accuracy of current sharing is t

perating conditions: VIN = 12V; VOo

below:

Table 1 Inductor DC Voltages at Different urrents

VL1 (mV) VL2

20 3.2 3.4

40 6.7 6.9

60 10.0 10.2

www.irf.com 10

IRDCiP2005C-1

VIN = 12V, V OUT = 1.2V, 200LFM, fsw = 500kHz, No Heatsink

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

10.0

11.0

0 102030405060

Load Current (A)

Power Loss (W)

Internal VDD, TA = 45C

Internal VDD, TA = Room

VDD = 6V, TA = 45C

VDD = 6V, TA = Room

Fig. 14 Power Loss

VIN = 12V, V OUT = 1.2V, 200LFM, fsw = 500kHz, No Heatsink

76%

78%

80%

82%

84%

86%

88%

90%

92%

0 102030405060

Load Current (A)

Efficiency

Internal VDD, TA = 45C

Internal VDD, TA = Room

VDD = 6V, TA = 45C

VDD = 6V, TA = Room

Fig. 15 Efficiency

11 www.irf.com

IRDCiP2005C-1

www.irf.com 12

Fig. 16 Thermal Image: Iout = 60A, VIN = 12V, with Internal VDD, VOUT = 1.2V, TA = 45oC, fsw = 500kHz,

200LFM, No Heatsi n k

Fig. 17 Thermal Image: Iout = 60A, VIN = 12V, VDD = 6V, VOUT = 1.2V, TA = 45oC, fsw = 500kHz, 200LFM, No

Heatsink

Table 2 Maximum Temperature for iP2005C Single Output Configuration

Bias Voltage U1 U2

Internal VDD = 5.2V 99.2oC 100oC

External VDD = 6V 95.9oC 96.9oC

IRDCiP2005C-1

13 www.irf.com

Refer to the following application notes for detailed guidelines and suggestions when

implementing iPOWIR Technology products:

AN-1043: Stabilize the Buck Converter with Transconductance Amplifier

This paper explains how to design the voltage compensation network for Buck Converters with

Transconductance Amplifier. The design methods and equations for Type II and Type III compensation

are given.

AN-1028: Recommended Design, Integration and Rework Guidelines for International Rectifier’s

iPowIR Technology BGA and LGA and Packages

This paper discusses optimization of the layout design for mounting iPowIR BGA and LGA packages on

printed circuit boards, accounting for thermal and electrical performance and assembly considerations.

Topics discussed include PCB layout placement, and via interconnect suggestions, as well as soldering,

pick and place, reflow, inspection, cleaning and re working recommendations.

AN-1030: Applyi ng iPOWIR Products in Your Thermal Environment

This paper explains how to use the Power Loss and SOA curves in the data shee t to validate if the

operating conditions and thermal environment are within the Safe Operating Area of the iPOWIR product.

AN-1047: Graphical solution for two branch heatsinking Safe Operating Area

Detailed explanation of the dual axis SOA graph and how it is derived.

Use of this design for any application should be fully verified by the customer. International Rectifier

cannot guarantee suitability for your applications, and is not liable for any result of usage for such

applications including, without limitation, personal or property damage or violation of third party

intellectual property rights.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, Calif ornia 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7 903