ATF1502AS-10QC44 - Atmel Corporation

Features

•High Density, High Performance Electrically Erasable Complex Programmable Logic

Device

– 32 Macrocells

– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell

– 44 pin

– 7.5 ns Maximum Pin-to-Pin Delay

– Registered Operation Up To 125 MHz

– Enhanced Routing Resources

•In-System Programm abi lity (ISP) via JTAG

•Flexible Logic Macrocell

– D/T/Latch Configurable Flip Flops

– Global and Individual Register Control Signals

– Global and Individual Output Enable

– Programmable Output Slew Rate

– Programmable Output Open Collector Option

– Maximum Logic utilization by burying a register with a COM output

•Advanced Power Management Features

– Automatic 3 mA Stand-By for “L” Version

– Pin-Controlled 4 mA Stand-By Mode (Typical)

– Programmable Pin-Keeper Inputs and I/Os

– Reduced-Power Feature Per Macrocell

•Available in Commercial and Industrial Temperature Ranges

•Available in 44-pin PLCC; TQFP; and PQFP

•Advanced EEPROM Technology

– 100% Tested

– Completely Reprogrammable

– 100 Pr o gram/ Erase Cycles

– 20 Year Data Retention

– 2000V ESD Protection

– 200 mA Latch-Up Immunity

•JTAG Boundary-Scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported

•PCI-compliant

•3.3 or 5.0V I/O pins

•Security Fuse Feature

Enhanced Features

•Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)

•Output Enable Product Terms

•D - Latch Mode

•Combinatorial Output with Registered Feedback within any Macrocell

•Three Global Clock Pins

•ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O

•Fast Registered Input from Product Term

•Programmable “Pin-Keeper” Option

•VCC Power-Up Reset Option

•Pull-Up Option on JTAG Pins TMS and TDI

•Advanced Power Management Features

– Edge Controlled Power Down “L”

– Individual Macrocell Power Option

– Disable ITD on Global Clocks, Inputs and I/O

High

Performance

E2PROM CPLD

ATF1502AS

Preliminary

Rev. 0995A–04/98

ATF1502AS

44-Lead TQFP/PQFP

Top View 44-Lead PLCC

Top View

Description

The ATF1502 AS is a high perfo rman ce, hig h density Com-

plex Programmable Logic Device (CPLD) which utilizes

Atmel’s pr oven electrically erasable techno logy. With 32

logic ma crocells and up to 36 inputs, it easily integ rates

logic from several TTL, SSI,MSI, LSI and classic PLDs.

The ATF1502AS’s enhanced routing switch matrices

increase usable gate count, and the odds of successful pin-

locked design modifications.

The ATF1502AS has up to 32 bi-directional I/O pins and 4

dedicated input pins, depending on the type of device pack-

age selected. Each dedicated pin can also serve as a glo-

bal contr ol signal; registe r clock, regis ter reset or outp ut

enab le. Each of these cont rol signa ls can be s elected for

use individually within each macrocell.

Bloc k Diagram

Each of the 32 macrocells generates a buried feedback,

which goe s to the gl obal bus . Each input and I/O pin als o feeds into the global bus. The switch matrix in each logic

block then selects 40 individual signals from the global bus.

I/O/TDI

I/O

GND

PD1/I/O

I/O

TMS/I/O

I/O

VCC

I/O

I/O/TDO

I/O

VCC

I/O

I/O/TCK

I/O

GND

I/O

GND

VCC

I/O

I/O/PD1

VCC/PD2

I/OE2/GCK2

GCLR/I

I/OE1

GCK1/I

GND

GCK3

I/O

TDI/I/O

I/O

GND

PD1/I/O

I/O

I/O/TMS

I/O

VCC

I/O

I/O/TDO

I/O

VCC

I/O

I/O/TCK

I/O

GND

I/O

GND

VCC

I/O

PD2/I/O

I/O

I/O/PD1

VCC/PD2

GCK2/OE2/I

GCLR/I

OE1/I

GCK1/I

GND

I/O/GCLK3

I/O

ATF1502AS

Each macrocell also generates a foldback logic term, which

goes to a regional bus. C ascade lo gic bet ween macr ocells

in the A TF1502AS allows fast, effi cient ge nerati on of com-

plex logic functions. T he ATF1502AS contains four such

logic chains, each capable of creating sum term logic with a

fan in of up to 40 product terms.

The ATF1502AS macrocell shown in F igure 1, is flexible

enough to s upp ort highly c om ple x lo gi c func ti ons o per at ing

at high speed. The macrocell consists of five sections:

product terms and product term select multiplexer;

OR/XOR/CASCADE logic; a flip-flop; output select and

enable; and logic array inputs.

Unused pr oduct terms are automatical ly disabled by the

compiler to decrease power consumption. A Security Fuse,

when programmed, protects the contents of the

ATF1502AS. Two bytes (16-bits) of User Signature are

accessible to the user for purposes such as storing project

name, part nu mbe r, revisi on or date . The Use r Sig natu re is

accessible regardless of the state of the Security Fuse.

The ATF1502AS device is an In-System Programmable

(ISP) device. It uses the industry standard 4-pin JTAG

interface (IEEE Std. 1149.1), and is fully compliant with

JTAG’s Boundary Scan Description Language (BSDL). ISP

allows the device to be pr ogrammed without removing it

from the printed circuit board. In addition to simplifying the

manufacturing flow, ISP also allows design modifications to

be made in the field via software.

Figure 1. ATF1502AS Macrocell

Product Terms and Select MUX

Each ATF1502AS macrocel l has five product terms. Each

product ter m r ec ei ves as its i nput s a ll si gna ls fr om both the

global bus and regional bus.

The produ ct ter m selec t multi plexer (PTMU X) allo cates the

five produ ct terms as needed to the macr ocell logic g ates

and control signals. The PTMUX programming is deter-

mined by the desi gn compiler , which sel ects the optimum

macrocell configuration.

OR/XOR/CASCADE Logic

The ATF1502AS’s logic structure is designed to efficiently

support all types of logic. Within a single macrocell, all the

product terms can be routed to the OR gate, creating a 5-

input AND/OR sum term. With the addition of the CASIN

from neighboring macrocells, this can be expanded to as

many as 40 product terms with a very small additional

delay.

The macrocell’s XOR gate allows efficient implementation

of compar e and arithm etic fun ctions. O ne inpu t to the XOR

comes from the OR sum term. The other XOR input can be

a product term or a fixed high or low level. For combinato-

rial outp uts, the fixe d level inpu t allows polar ity selec tion.

For regi stered func tions, the fixe d levels all ow DeMorgan

minimization of product terms. The XOR gate is also used

to emulate T- and JK-type flip-flops.

Flip Flop

The ATF1502AS’s flip flop has very flexible data and con-

trol functions. The data input can come from either the XOR

gate, from a separate product term or directly from the I/O

pin. Se lect ing the separat e prod uct term allows creati on of

a buried registered feedback within a combinatorial output

ATF1502AS

macrocell. (This feature is automatically implemented by

the fit ter softwa re). In addi tion to D, T, J K and SR ope ra-

tion, the flip flop c an also be confi gured as a flow-through

latch. In this mode, data passes through when the clock is

high and is latched when the clock is low.

The cloc k its elf can eit her be on e of the Glo bal CLK Signal

GCK[0 : 2] or an individual product term. The flip flop

changes state on the clock’s rising edge. When the GCK

signal is used as the clock, one of the macrocell product

terms can be selecte d as a clock enable . When t he cloc k

enable function is active and the enable signal (product

term) is low, all clock edges are ignored. The flip flop’s

asynchronous reset signal (AR) can be either the Global

Clear (GCLEAR), a product term, or always off. AR can

also be a logic O R of GCLEAR with a product term . The

asynch ro nou s pr es et (AP ) can be a pr odu ct te rm or alway s

off.

Output Select and Enable

The ATF1 502AS ma croce ll out put can be selec ted as reg-

istered or combinatorial. The buried feedback signal can be

either combinatorial or registered signal regardless of

whether the output is combinatorial or registered.

The output enable multiplexer (MOE) controls the output

enable sig nals. A ny buffer can be perma nentl y en abled for

simple outp ut oper ation. Buffers can also be perma nently

disable d to allow use of the pin as an input. In th is con figu-

ration all the macr oce ll re sour ces are st ill availa ble, inc lud-

ing the buri ed feedback, expander and CASCADE log ic.

The out put enabl e for each mac rocell ca n be selec ted as

either of the two dedicated OE input pins as an I/O pin con-

figured as an input, or as an individual product term.

Global Bus/Switch Matrix

The global bus contains all input and I/O pin signals as well

as the bur ied feedback signal from a ll 32 macr ocells. The

Switch Matrix in each Logic Block receives as its inputs all

signals from the global bus . Under software contr ol, up to

40 of these signals can be sel ected as inputs to the Logic

Block.

Foldback Bus

Each macrocell a lso genera tes a foldback product term .

This signal goes to the regional bus and is available to 4

macrocells. The foldback is an inverse polarity of one of the

macrocell’s product ter ms. The 4 foldback terms in each

region allows generation of high fan-in sum terms (up to 9

product terms) with a small additional delay.

Programmable Pin-Keeper Option for

Inputs and I/Os

The ATF1502A S off ers the op tion o f progr ammin g all input

and I/O pins so that pin keeper circuits can be utilized.

When any pin is driven high or low and then subsequently

left floating, it will stay at that previous high or low level.

This circuitry prevents unused input and I/O lines from

floatin g to inte rmedi ate v olt age l evels , wh ich cau se unn ec-

essary power consumption and system noise. The keeper

circuits eliminate the need for external pull-up resistors and

eliminate their DC power consumption.

Input Diagram

I/O Diagram

Speed /Power Manage men t

The ATF1502AS has several built-in speed and power

management features. The ATF1502A S contains circuitry

that automatically puts the dev ice into a low power st and-

by mode when no logic tr ansitions ar e occurring. This not

only reduces power consumption during inactive periods,

but al so provi des a p roportion al power s avings f or most

applica tio ns running at system sp eeds bel ow 50 MHz. This

feature may be selected as a design option.

To further reduce power, each ATF1502AS macrocell has

a Reduced P ower b it feat ure. Th is fe ature all ows indi v idual

macro cells to be config ured f or maxi mum p ower sa vings.

This feature may be selected as a design option.

The ATF1502A Ss also has an optiona l power down mo de.

In this mod e, current drops to below 10 mA. When the

power down option is selected, either PD1 or PD2 pins (or

both) can be used to power down the part. The power down

ATF1502AS

option i s select ed in the de sign so urce file . When en abled ,

the device goes into power down when either PD1 or PD2

is high. In the power down mo de, all inter nal logic s ignals

are latched and held, as are any enabled outputs.

All pin transi tions are ignored until the PD pi n is brought

low. When the power down feature is enabled, the PD1 or

PD2 pin cannot be used as a l ogic input or output. How-

ever, the pin’s ma croc ell m ay st ill be used to gener ate bur-

ied foldback and cascade logic signals.

All Powe r-Down AC Characteri stic parameters are com-

puted from external input or I/O pins, with Reduced Power

Bit turned on. For macrocells in reduced-power mode

(Reduced power bit turned on), the reduced power adder,

tRPA, mus t be added to the AC par ameters, whi ch include

the data paths tLAD, tLAC, tIC, tACL, tACH and tSEXP.

The ATF1502AS macrocell also has an option whereby the

power can be reduced on a per macrocell basis. By

enabling this power down option, macrocells that are not

used in an application can be turned down thereby reduc-

ing the overall power consumption of the device.

Each o utpu t als o ha s i ndi vidua l s lew r ate c on tr ol. Thi s m ay

be used to reduce sy stem noise by slowing down outputs

that do not need to operate at maxim um speed. Outputs

default to slow switching, and may be specified as fast

switching in the design file.

Design Software Support

ATF15 02AS des igns are supp orted by sev eral thir d party

tools. Automated fitters allow logic synthesis using a variety

of high level description languages and formats.

Power Up Reset

The ATF1502AS has a power-up reset option at two differ-

ent voltage trip levels when the dev ice is being powered

down. Within the fitter, or during a conversion, if the

“power-reset” option is turned “on” (which is the default

option), the trip levels during power up or power down is at

2.8V. The user can change this default option from “on” to

“off” (within the fitter or specify it as a switch during conver-

sion). When this is done, the voltage trip level during

power-down changes from 2.8V to 0.7V. This is to ensure a

robust operating environment.

The regis ters i n th e A TF1502 AS ar e d es igned to r es et dur-

ing power up. At a poi nt delayed slig htly from VCC crossing

Vrst, all registers will be r eset to the low state. The output

state will depend on the polarity of the buffer.

This feature is critical for state machine initialization. How-

ever, due to the asynchronous nature of reset and the

uncerta inty of how V CC actua lly ris es in the s ystem, th e fol-

lowing conditions are required:

1. The VCC rise must be monotonic,

2. After reset occurs, all input and feedback setup

times must be met before driving the clock pin-

high, and,

3. The clock must remain stable during TD.

Security Fuse Usage

A single fuse i s provided to preven t unauthorized copying

of the ATF1502AS fuse patterns. Once programmed, fuse

verify is inhibited. However, the 16-bit User Signature

remains accessible.

Programming

ATF1502AS devices are In-System Programmable ( ISP)

devices utilizing the 4-pin JTAG protocol. This capability

eliminat es pac ka ge h andling no r mal ly r equi r ed fo r pro gr am

and facilitates rapid design iterations and field changes.

Atmel provides ISP hardware and software to allow pro-

grammi ng of the ATF1502AS v ia the PC. ISP is per formed

by using either a down load c able, o r a comp arable b oard

tester or a simple microprocessor interface.

When using the ISP hardware or S/W to program the

ATF1502AS dev ic es, four I/0 pins mus t b e res er ved for the

JTAG interface. However, the logic features the macrocells

associated with these I/0 pins are still available to the

design for burned logic functions.

To facilitate ISP programming by the Automated Test

Equipment (ATE) ve ndors. Se ri al Vector Form at (SVF) file s

can be created by Atmel provided Software utilities.

ATF1502AS devices can also be programmed using stan-

dard 3rd party programmers. With 3rd party programmer

the JTAG ISP port can be disabled thereby allowing 4 addi-

tional I/O pins to be used for logic.

Contact your local Atmel representatives or Atmel PLD

applications for details.

ISP Programming Protection

The ATF1502AS has a special feature which locks the

devic e and prevents the inputs and I /O from drivin g if t he

programming process is interrupted due to any reason. The

inputs and I/O default to high-Z state during such a condi-

tion. In add ition, th e pin keep er optio n preserve s the pre vi-

ous state of the input and I/0 PMS during programming.

All ATF1502A S devices are initial ly shipped in the erased

state thereby making them ready t o use f or ISP.

Note: For more information refer to the “Designing for In-Sys-

tem Program mability with Atmel CPLDs” application

note.

ATF1502AS

JTAG-BST/ISP Overview

The JTAG boundary-scan testing is controlled by the Test

Access Port (TAP) controller in the ATF1502AS. The

boundary-sca n technique i nvolves the inc lusion of a shift-

registe r sta ge (con tained in a bo undar y-sca n cell ) adj acent

to each component so that signals at component bound-

aries can b e controlled a nd observed u sing scan testing

methods. Each input pin and I/O pin has its own boundary

scan cell (BSC) to support boundary scan testing. The

ATF1502AS does not include a Test Reset (TRST) input

pin because the TAP controller is automatically reset at

power up. The five JTAG modes supported include: SAM-

PLE/PRELOAD, EXTEST, BYPASS, IDCODE and HIGHZ.

The ATF1502AS’s ISP can be fully described using JTAG’s

BSDL as des cribed in IE EE S tandard 114 9.1b. Th is a llows

ATF1502AS programming to be described and imple-

mented us ing any one of th e 3rd pa rty devel opment too ls

supporting this standard.

The ATF 1502AS has th e option of us ing four JTA G-stan-

dard I/O pins for bounda ry scan testing (BST) and in -sys-

tem programming (ISP) purposes. The ATF1502AS is

programmable through the four JTAG pins using the IEEE

standar d JTAG progra mming protoco l established by IE EE

Standard 1149.1 using 5V TTL-level programming signals

from the ISP interface for in-system programming. The

JTAG fea ture is a program mable optio n. If JTAG (BST or

ISP) is not needed, then the four JTAG control pins are

available as I/O pins.

JTAG Boun dary Scan Cell (BSC)

Testing

The ATF1502AS contains up to 32 I/O pins and 4 input

pins, depe ndin g on the an d pa ckage type sele cted . Ea ch

input pin an d I/O pin ha s its own bo und ary sc an ce ll ( BSC)

in o rder to s upport boundary scan t estin g as de scribed in

detail by IEEE Standard 1149.1. Typical BSC consists of

three capture registers or scan registers and up to two

update registers. There are two types of BSCs, one for

input or I/O pin, an d one for the mac rocells. Th e BSCs in

the dev ice a re chai ned toge ther thr ough th e capt ure reg is-

ters. Input to the capture register chain is fed in from the

TDI pin while the output is directed to the TDO pin. Capture

registers are used to capture active device data signals, to

shift da ta in and out of the device an d to load data into the

update register s. Control signals a re generat ed inter nally

by the J TAG TA P contro ller. The BSC c onfig uration f or the

input and I/O pins and macrocells are shown below.

BSC Configuration for Input and I/O

Pins (except JTAG TAP Pins)

Note: The ATF1502AS has pull-up option on TMS and TDI

pins. This featu re is selec ted as a design option.

DC and AC Operating Conditions

Commercial Industrial

Operating Temperature (Case) 0°C - 70°C-40

C - 85°C

VCCINT or VCCIO (5V) Power

Supply 5V ± 5% 5V ± 10%

VCCIO (3.3V) Power Supply 3.0V - 3.6V 3.0V - 3.6V

ATF1502AS

Note: Not more than one output at a time should be shor ted. Duration of short circuit test should not exceed 30 sec.

Note: Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.

The OGI pin (high-voltage pin during programming) has a maximum capacitance of 12 pf.

DC Characteristics

Symbol Parameter Condition Min Typ Max Units

IIL Input or I/O Low

Leakage C urrent VIN = VCC -2 -10 µA

IIH Input or I/O High

Leakage C urrent 210

OZ Tri-State Output

Off-State Current VO = VCC or GND -40 40 µA

ICC1 Power Supply Current,

Stand-by VCC = Max

VIN = 0, VCC

Std Mode Com. 60 mA

Ind. 75 mA

“Z” Mode Com. 40 µA

Ind. 40 µA

ICC2 Power Supply Current,

Power Down Mode VCC = Max

VIN = 0, VCC “PD” Mode 1 mA

ICC3 Clock ed P ower Supply

Current VCC = Max

VIN = 0, VCC “Z” Mode 2 mA/

MHz

IOS Output Short Circuit

Current VOUT = 0.5V -150 mA

VCCIO Supply Voltage 5.0V Device Output Com. 4.75 5.25 V

Ind. 4.5 5.5 V

VCCIO Suppl y Vo ltage 3.3V Device Output 3.0 3.6 V

VIL Input Low Voltage -0.3 0.8 V

VIH Input High Voltage 2.0 VCCINT +

0.3 V

VOL Output Low Voltage VIN = VIH or VIL

VCCIO = MIN, IOL = 12 mA Com. 0.45 V

Ind.

VOH Output High Volt age VIN = VIH or VIL

VCCIO = MIN, IOH = -4.0 mA 2.4 V

Pin Capacitance

Typ Max Units Conditions

CIN 810pF V

IN = 0V; f = 1.0 MHz

CI/O 810pF V

OUT = 0V; f = 1.0 MHz

ATF1502AS

Absolute Maximum Ratings*

Temperature Under Bias.................................. -40°C to +85°C *NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. Th is is a s tress rating only an d

funct ion al ope ration of th e d evice at thes e or an y

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditi ons f or e xtended p eriods ma y af fect dev ice

reliability.

Note: 1. Minimum voltage is -0.6V DC, which may under-

shoot to -2.0V for pulses of less than 20 ns. Max-

imum output pin voltage is VCC + 0.75V DC,

which may overshoot to 7.0V for pulses of less

than 20 ns.

Storage Temperature..................................... -65°C to +150°C

Voltage on Any Pin with

Respect to Ground .........................................-2.0V to +7.0V(1)

Voltage on Input Pins

with Respect to Ground

During Programming.....................................-2.0V to +14.0V(1)

Programming Voltage with

Respect to Ground .......................................-2.0V to +14.0V(1)

AC Characteristics

Symbol Parameter

-7 -10 -15 -20 -25

UnitsMin Max Min Max Min Max Min Max Min Max

tPD1 Input or Feedback to

Non-Registered Output 7.5 10 3 15 20 25 ns

tPD2 I/O Input or Feedback to

Non-Registered Feedback 793121625ns

SU Global Clock Setup Time 6 7 11 16 20 ns

tHGlobal Clock Hold Time 0 0 0 0 0 ns

tFSU Global Clock Setup Time of

Fast Input 33335ns

FH Global Clock Hold Time of

Fast Input 0.5 0.5 1 1.5 2 MHz

tCOP Global Clock to Output Delay 4.5 5 8 10 13 ns

tCH Global Clock High Time 3 4 5 6 7 ns

tCL Global Clock Low Time 3 4 5 6 7 ns

tASU Array Clock Setup Time 3 3 4 4 5 ns

tAH Array Clock Hold Time 2 3 4 5 6 ns

tACOP Array Clock Output Delay 7.5 10 15 20 25 ns

tACH Array Clock High Time 3 4 6 8 10 ns

tACL Array Clock Low Time 3 4 6 8 10 ns

tCNT Minimum Clock Global Period 8 10 13 17 22 ns

fCNT Maximum Internal Global

Clock Frequency 125 100 76.9 66 50 MHz

tACNT Minimum Array Clock Period 8 10 13 17 22 ns

fACNT Maximum Internal Array

Clock Frequency 125 100 76.9 66 50 MHz

ATF1502AS

Note: See ordering information for valid part numbers. (continued)

Timing Model

FMAX Maximum Clock Frequency 166.7 125 100 83.3 60 MHz

tIN Input Pad and Buffer Delay 0.5 0.5 2 2 2 ns

tIO I/O Input Pad and Buffer Delay 0.5 0.5 2 2 2 ns

tFIN Fast Input Delay 1 1 2 2 2 ns

tSEXP Foldback Term Delay 4 5 8 10 12 ns

tPEXP Cascade Logic Delay 0.8 0.8 1 1 1.2 ns

tLAD Logic Array Delay 3 5 6 7 8 ns

tLAC L ogi c C ontro l De lay 3 5 6 7 8 ns

tIOE Internal Output Enable Delay 2 2 3 3 4 ns

tOD1

Output Buffer and Pad Delay

(Slow slew rate = OFF;

VCCIO = 5V; CL = 35 pF) 21.5 4 5 6ns

OD2

Output Buffer and Pad Delay

(Slow slew rate = OFF;

VCCIO = 3.3V; CL = 35 pF) 2.5 2.0 5 6 7 ns

AC Characteristics (Continued)

Symbol Parameter

-7 -10 -15 -20 -25

UnitsMin Max Min Max Min Max Min Max Min Max

ATF1502AS

Notes: 1. See orderi ng information for valid part numbers.

2. The tRPA parameter must be added to the tLAD, tLAC,tTIC, tACL, and tSEXP parameters for macrocells running in the reduced-

power mode.

Input Test Waveforms and

Measurement Levels

tR, tF = 1.5 ns typical

Output AC Test Loads

Note: *Numbers in parenthesis refer to 3.0V operating condi-

tions (preliminary)

AC Characteristics (Continued)

Symbol Parameter

-7 -10 -15 -20 -25

UnitsMinMaxMinMaxMinMaxMinMaxMinMax

ZX1

Output Buffer Enable Delay

(Slow slew rate = OFF;

VCCIO = 5.0V; CL = 35 pF) 4.0 5.0 7 9 10 ns

tZX2

Output Buffer Enable Delay

(Slow slew rate = OFF;

VCCIO = 3.3V; CL = 35 pF) 4.5 5.5 7 9 10 ns

tZX3

Output Buffer Enable Delay

(Slow slew rate = ON;

VCCIO = 5.0V/3.3V; CL = 35 pF) 9 9 10 11 12 ns

tXZ Out put Buffer Disable Delay

(CL = 5 pF) 45678ns

SU Register Setup Time 3 3 4 5 6 ns

tHRegister Hold Time 2 3 4 5 6 ns

tFSU Register Setup Time of Fast Input 3 3 2 2 3 ns

tFH Register Hold Time of Fast Input 0.5 0.5 2 2 2.5 ns

tRD Register Delay 1 2 1 2 2 ns

tCOMB Combin atorial Delay 1 2 1 2 2 ns

tIC Array Clock Delay 35678ns

EN Register Enable Time 3 5 6 7 8 ns

tGLOB Global Control Delay 1 1 1 1 1 ns

tPRE Register Preset Time 23456ns

CLR R egister C lear Time 2 3 4 5 6 ns

tUIM Switch Matrix Delay 11222ns

RPA Reduced-Power Adder(2) 10 11 13 14 15 ns

(3.0V)*

(703 )*

(8060 )*

ATF1502AS

Power Down Mode

The AT F1502A S includ es an op tional pi n contro lled p ower

down feature.When this mode is enabled, the PD pin acts

as the power down pin. When the PD pin is high, the device

suppl y curre nt is red uced t o less th an 3 mA. Durin g power

down, all o utput data and internal logic states are latched

and held. Therefore, all registered and combinatorial output

data rema in vali d. An y outp uts which w ere in a Hi -Z st ate at

the onset will remain at Hi-Z. During power down, all input

signals except the power down pin are blocked. Input and

I/O hold latches rem ain active to insure that pins do not

float to indeterminate levels, further reducing system

power. The power down pin feature is enabled in the logic

design fi le . Des igns us in g the pow er down pi n ma y n ot u se

the PD pin logic array input. However, all other PD pin mac-

rocell reso urces may still be used, including the buried

feedback and foldback product term array inputs.

Notes: 1. For slow slew outputs, add tSSO.

2. Pin or Product Term.

Po wer Down AC Characteristics(1)(2)

Symbol Parameter

-7 -10 -15 -20 -25

UnitsMinMaxMinMaxMinMaxMinMaxMinMax

IVDH Valid I, I/O Before PD High 7 10 15 20 25 ns

tGVDH Valid OE(2) Before PD High 7 10 15 20 25 ns

tCVDH Valid Clock(2) Before PD High 7 10 15 20 25 ns

tDHIX I, I/O Don’t Care After PD High 12 15 25 30 35 ns

tDHGX OE(2) Don’t Care After PD High 12 15 25 30 35 ns

tDHCX Clock(2) Don’t Care After PD High 12 15 25 30 35 ns

tDLIV PD Low to Valid I, I/O 1 1 1 1 1 µs

tDLGV PD Low to Valid OE (Pin or Term) 1 1 1 1 1 µs

tDLCV PD Low to Valid Clock (Pin or Term) 1 1 1 1 1 µs

tDLOV PD Low to Valid Output 1 1 1 1 1 µs

ATF1502AS

BSC Configuration for Mac

1DQ

DQ DQ

Capture

DR Update

DQ DQ

TDI

OUTJ

OEJ

Shift

Clock

Mode

TDO

BSC for Dedicated Input

BSC for I/O Pins and Macrocells

TDI

CLOCK

TDO

ATF1502AS

PCI Com pli a nc e

The ATF1502AS also supports the growing need in the

industry to support the new Peripheral Component Inter-

connect (PCI) interface standard in PCI-based designs and

specif ications . The PCI inter face call s for high curr ent driv-

ers which are much larger than the traditional TTL drivers.

In general, PLDs and FPGAs parallel outputs to support the

high current load required by the PCI interface. The

ATF1502AS allows this without contributing to system

noise while delivering low output to output skew. Having a

program mable hig h drive o ption is a lso pos sible with out

increasing output delay or pin capacitance. The PCI electri-

cal characteristics appear on the next page.

PCI Voltag e-to-Cu rrent Curves for +5V Signaling in Pull-Up Mode

PCI Voltag e-to-Cu rrent Curves for +5V Signaling in Pull-Down Mode

2.4

VCC

1.4

-2 -44 -178

Current (mA)

AC drive

point

drive point

Voltage

Pull Up

Test Point

2.2

VCC

0.55

3.6 95 380

Current (mA)

AC drive

point

drive point

Voltage

Pull Down

Test Point

ATF1502AS

Note: Leak ag e Current is with Pin-Keeper off.

Notes: 1. Equation A: IOH = 11.9 (VOUT - 5.25) * (VOUT + 2.45) for VCC > VOUT > 3.1V.

2. Equation B: IOL = 78.5 * VOUT * (4.4 - VOUT) for 0V < VOUT < 0.71V.

PCI DC Characteristics (Preliminary)

Symbol Parameter Conditions Min Max Units

VCC Supply Voltage 4.75 5.25 V

VIH Input High Voltage 2.0 VCC + 0.5 V

VIL Input Low Voltage -0.5 0.8 V

IIH Input High Leakage Current VIN = 2.7V 70 µA

IIL Input Low Leakage Current VIN = 0.5V -70 µA

VOH Output High Voltage IOUT = -2 mA 2.4 V

VOL O utput Low Voltage I OUT = 3 mA, 6 mA 0.55 V

CIN Input Pin Capacitance 10 pF

CCLK CLK Pin Capacitance 12 pF

CIDSEL IDSEL Pin Capacitance 8 pF

LPIN Pin Induct anc e 20 nH

PCI AC Characteristics (Preliminary)

Symbol Parameter Conditions Min Max Units

IOH(AC) Switching 0 < VOUT ≤ 1.4 -44 mA

Current High 1.4 < VOUT < 2.4 -44+(VOUT - 1.4)

/0.024 mA

3.1 < VOUT < VCC Equa tion A mA

(Test High) VOUT = 3.1V -142 µA

IOL(AC) Switching VOUT > 2.2V 95 mA

Current Low 2.2 > VOUT > 0 VOUT/0.023 mA

0.1 > VOUT > 0 Equation B mA

(Test Point) VOUT = 0.71 206 mA

ICL Low Clamp Current -5 < VIN ≤-1 -25+(VIN + 1)

/0.015 mA

SLEWROutput Rise Slew Rate 0.4V to 2.4V load 1 5 V/ns

SLEWFOutput Fall Slew Rate 2.4V to 0.4V load 1 5 V/ns

ATF1502AS

OE (1, 2) Global OE Pins

GCLR Global Clear Pin

GCLK (1, 2, 3) Global Clock Pins

PD (1, 2) Power down pins

TDI, TMS, TCK, TDO JTAG pins used for Boundary Scan Testing or In-System Programming

GND Ground Pins

VCCINT VCC pins for the device (+5V - Internal)

VCCIO VCC pins for output drivers (for I/O pins) (+5V or 3.3V - I/Os)

ATF1502AS Dedicated Pinouts

Dedicated Pin 44-Pin

TQFP 44-Pin

J-Lead 44-Pin

PQFP

INPUT/OE2/GCLK2 40 2 40

INPUT/GCLR 39 1 39

INPUT/OE1 38 44 38

INPUT/GCLK1 37 43 37

I/O /GCLK3 35 41 35

I/O / PD (1,2) 5, 19 11, 25 5, 19

I/O / TDI (JTAG) 1 7 1

I/O / TMS (JTAG) 7 13 7

I/O / TCK (JTAG) 26 32 26

I/O / TDO (JTAG) 32 38 32

GND 4, 16, 24, 36 10, 22, 30, 42 4, 16, 24, 36

VCCINT 9, 17, 29, 41 3, 15, 23, 35 9, 17, 29, 41

VCCIO ---

N/C ---

# of Signal Pins 36 36 36

# User I/O Pins 32 32 32

ATF1502AS

ATF1502AS I/O Pinouts

MC PLC 44-Pin PLCC 44-Pin TQFP 44-Pin PQFP

1A4 4242

2A5 4343

3A/PD1 64141

4A7 1 1

5A8 2 2

6A9 3 3

7A11 5 5

8/TDI A12 6 6

9A13 7 7

10 A 14 8 8

11A161010

12A171111

13A181212

14A191313

15A201414

16A211515

17B413535

18B403434

19B393333

20B383232

21B373131

22B363030

23B342828

24B332727

25B322626

26B312525

27B292323

28B282222

29B272121

30B262020

31B251919

32/TMS B241818

ATF1502AS

Ordering Information

tPD

(ns) tCO1

(ns) fMAX

(MHz) Ord ering Code Package Operation Range

7.5 4.5 166.7 ATF1502AS-7 AC44

ATF1502AS-7 JC44

ATF1502AS-7 QC44

44A

44J

44Q

Commercial

(0°C to 70°C)

10 5 125 ATF1502AS-10 AC44

ATF1502AS-10 JC44

ATF1502AS-10 QC44

44A

44J

44Q

Commercial

(0°C to 70°C)

10 5 125 ATF1502AS-10 AI44

ATF1502AS-10 JI44

ATF1502AS-10 QI44

44A

44J

44Q

Industrial

(-40°C to +85°C)

15 8 100 ATF1502AS-15 AC44

ATF1502AS-15 JC44

ATF1502AS-15 QC44

44A

44J

44Q

Commercial

(0°C to 70°C)

15 8 100 ATF1502AS-15 AI44

ATF1502AS-15 JI44

ATF1502AS-15 QI44

44A

44J

44Q

Industrial

(-40°C to +85°C)

20 12 83.3 ATF1502ASL-20 AC44

ATF1502ASL-20 JC44

ATF1502ASL-20 QC44

44A

44J

44Q

Commercial

(0°C to 70°C)

20 12 83.3 ATF1502ASL-20 AI44

ATF1502ASL-20 JI44

ATF1502ASL-20 QI44

44A

44J

44Q

Industrial

(-40°C to +85°C)

25 15 70 ATF1502ASL-25 AC44

ATF1502ASL-25 JC84

ATF1502ASL-25 QC44

44A

44J

44Q

Commercial

(0°C to 70°C)

25 15 70 ATF1502ASL-25 AI44

ATF1502ASL-25 JI84

ATF1502ASL-25 QI44

44A

44J

44Q

Industrial

(-40°C to +85°C)

Package Type

44A 44-Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)

44J 44-Lead, Plastic J-Leaded Chip Carrier OTP (PLCC)

44Q 44-Lead, Plastic Gull Wing Quad Flatpack (PQFP)

ATF1502AS

Packaging Information

* Controlling dimension: millimeters

.045(1.14) X 45° PIN NO. 1

IDENTIFY .045(1.14) X 30° - 45° .012(.305)

.008(.203)

.021(.533)

.013(.330)

.630(16.0)

.590(15.0)

.043(1.09)

.020(.508)

.120(3.05)

.090(2.29)

.180(4.57)

.165(4.19)

.500(12.7) REF SQ

.032(.813)

.026(.660)

.050(1.27) TYP

.022(.559) X 45° MAX (3X)

.656(16.7)

.650(16.5)

.695(17.7)

.685(17.4)SQ

* Controlling dimension: millimeters

44A, 44-Lead, Thin (1.0 mm) Plastic Gull Wing

Quad Flat Package (TQFP)

Dimensions in Millimeters and (Inches)*

44J, 44-Lead, Plastic J-Leaded Chip Carrier (PLCC)

Dimensions in Inches and (Millimeters)

JEDEC STANDARD MS-018 AC

44Q, 44 Lead, Plastic Gull Wing Quad Flat

Package (PQFP)

Dimensions in Inches and (Millimeters)