Rev.2.00 Sep. 07, 2005 page 1 of 5
2SK2315
Silicon N Channel MOS FET REJ03G1006-0200
(Previous: ADE-208-1354)
Rev.2.00
Sep.07,2005
Application
High speed power switching
Features
• Low on-resistance
• High speed switching
• Low drive current
• 2.5 V gate drive device can be driven from 3 V source.
• Suitable for DC-DC converter, motor drive, power switch, solenoid drive
Outline
RENESAS Package code: PLZZ0004CA-A
(Package name: UPAK )
R
1. Gate
2. Drain
3. Source
4. Drain
4
321D
G
S
Note: Marking is “TY”
*UPAK is a trademark of Renesas Technology Corp.
2.5 V gate drive device can be driven from 3 V source.
Suitable for DC-DC converter, motor drive, power switch, solenoid drive
RENESAS Package code: PLZZ0004CA-A
(Package name: UPAK )
R
(Package name: UPAK )
R
(Package name: UPAK )
4
3
1
G
S
*UPAK is a trademark of Renesas Technology Corp.
2SK2315
Rev.2.00 Sep. 07, 2005 page 2 of 5
Absolute Maximum Ratings
(Ta = 25°C)
Item Symbol Ratings Unit
Drain to source voltage VDSS 60 V
Gate to source voltage VGSS ±20 V
Drain current ID 2 A
Drain peak current ID(pulse)*1 4 A
Body to drain diode reverse drain current IDR 2 A
Channel dissipation Pch*2 1 W
Channel temperature Tch 150 °C
Storage temperature Tstg –55 to +150 °C
Notes: 1. PW ≤ 10 µs, duty cycle ≤ 1 %
2. When using the alumina ceramic board (12.5 × 20 × 0.7mm)
Electrical Characteristics
(Ta = 25°C)
Item Symbol Min Typ Max Unit Test Conditions
Drain to source breakdown voltage V(BR)DSS 60 — — V ID = 10 mA, VGS = 0
Gate to source breakdown voltage V(BR)GSS ±20 — — V IG = ±100 µA, VDS = 0
Gate to source leak current IGSS — — ±5µA VGS = ±16 V, VDS = 0
Zero gate voltage drain current IDSS — — 5 µA VDS = 50 V, VGS = 0
Gate to source cutoff voltage VGS(off) 0.5 — 1.5 V ID = 1 mA, VDS = 10 V
— 0.4 0.6 Ω I
D = 0.3 A, VGS = 3 V*3
Static drain to source on state
resistance RDS(on) — 0.35 0.45 Ω I
D = 1 A, VGS = 4 V*3
Forward transfer admittance |yfs| 1.5 1.8 — S ID = 1 A, VDS = 10 V*3
Input capacitance Ciss — 173 — pF
Output capacitance Coss — 85 — pF
Reverse transfer capacitance Crss — 23 — pF
VDS = 10 V, VGS = 0,
f = 1 MHz
Turn-on time ton — 21 — ns
Turn-off time toff — 85 — ns ID = 1 A, RL = 30 Ω,
VGS = 10 V
Note: 3. Pulse Test
Electrical Characteristics
Item Symbol
Drain to source breakdown voltage V
(BR)DSS
60 — — V I
Gate to source breakdown voltage V
(BR)GSS
±
20 — — V I
Gate to source leak current
I
GSS
— —
Zero gate voltage drain current I
DSS
— — 5
Gate to source cutoff voltage V
GS(off)
0.5 — 1.5 V I
— 0.4 0.6
R
DS(on)
— 0.35 0.45
|y
fs
| 1.5 1.8 — S I
Ciss — 173 — pF
Coss — 85 — pF
Coss — 85 — pF
Reverse transfer capacitance Crss — 23 — pF
— 21 — ns
— 85 — ns
2SK2315
Rev.2.00 Sep. 07, 2005 page 3 of 5
Main Characteristics
1.6
1.2
0.8
0.4
0
Channel Dissipation Pch** (W)
(** on the almina ceramic board)
50 100 150 200
Ambient Temperature Ta (°C)
Power vs. Temperature Derating
Drain to Source Voltage VDS (V)
Drain Current I
D
(A)
Maximum Safe Operation Area
5
2
1
0.5
0.2
0.1
0.02
0.05
0.01
0.005
0.2 0.5 1 2 5 10 20 50 100 200
1 ms
Operation in
this area is
limited by RDS(on)
PW = 10 ms
100 µs
Ta = 25°C
1 shot pulse
DC Operation
5
4
3
2
1
0
Drain to Source Voltage VDS (V)
Drain Current I
D
(A)
Typical Output Characteristics
2 4 6 8 10
3 V
2.5 V
2 V
Ta = 25°C
Pulse Test
V
GS
= 1.5 V
10 V
5 V
4 V
3.5 V
5
4
3
2
1
0
Gate to Source Voltage VGS (V)
Drain Current I
D
(A)
Typical Transfer Characteristics
Tc = 75°C
25°C
–25°C
V
DS
= 10 V
Pulse Test
12345
1.0
0.8
0.6
0.4
0.2
0
Gate to Source Voltage VGS (V)
Drain to Source Saturation Voltage vs.
Gate to Source Voltage
Drain to Source Saturation Voltage V
DS(on)
(V)
4 8 12 16 20
1 A
0.5 A
I
D
= 2 A
Pulse Test
Ta = 25°C
Drain Current ID (A)
Drain to Source On State Resistance
R
DS(on)
(Ω)
Static Drain to Source State Resistance
vs. Drain Current
0.1
5
2
1
0.2
0.5
0.1
0.05 0.2 0.5 1 2 5 10
10 V
Ta = 25°C
Pulse Test
V
GS
= 3 V
50 100 150 200
Ambient Temperature Ta (
Typical Output Characteristics
3 V
2.5 V
Ta = 25
°
C
Pulse Test
10 V
5 V
4 V
3.5 V
2
1
0
Gate to Source Voltage V
Drain Current I
12345
Static Drain to Source State Resistance
vs. Drain Current
Ta = 25
°
2SK2315
Rev.2.00 Sep. 07, 2005 page 4 of 5
1.0
0.8
0.6
0.4
0.2
–40 0 40 80 120 160
Case Temperature Tc (°C)
0
Static Drain to Source on State Resistance
RDS(on) (Ω)
Static Drain to Source on State Resistance
vs. Temperature
1 A
0.5 A
V
GS
= 10 V I
D
= 2 A
V
GS
= 3 V
I
D
= 2 A
1 A 0.5 A
Forward Transfer Admittance |yfs| (S)
Drain Current ID (A)
Forward Transfer Admittance vs.
Drain Current
10
2
5
1
0.2
0.5
0.1
0.1 0.2 0.5 1 2 5 10
V
DS
= 10 V
Pulse Test
Tc = –25°C
25°C
75°C
1000
100
10
10
Capacitance C (pF)
Drain to Source Voltage VDS (V)
Typical Capacitance vs.
Drain to Source Voltage
10 20 30 40 50
Ciss
Coss
Crss
V
GS
= 0
f = 1 MHz
100
80
60
40
20
0
Gate Charge Qg (nc)
Drain to Source Voltage VDS (V)
20
16
12
8
4
0
Gate to Source Voltage VGS
(V)
Dynamic Input Characteristics
V
GS
V
DS
V
DD
= 50 V
25 V
10 V
I
D
= 2 A
246810
V
DD
= 50 V
25 V
10 V
Drain Current ID (A)
Switching Time t (ns)
Switching Characteristics
0.05 0.1 0.2 0.5 1 2 5
200
100
20
50
10
2
5
V
GS
= 10 V, PW = 2 µs
VDD = 30 V, duty < 1 %
tf
trtd(on)
td(off)
5
4
3
2
1
00.4 0.8 1.2 1.6 2.0
Source to Drain Voltage VSD (V)
Reverse Drain Current IDR (A)
Reverse Drain Current vs.
Source to Drain Voltage
10 V 5 V
V
GS
= 0
Pulse Test
Case Temperature Tc (
Typical Capacitance vs.
Drain to Source Voltage
Ciss
Coss
40
20
0
Gate Charge Qg (nc)
Drain to Source Voltage V
246810
5
Reverse Drain Current vs.
Source to Drain Voltage
Pulse Test
2SK2315
Rev.2.00 Sep. 07, 2005 page 5 of 5
Package Dimensions
4.5 ± 0.1
1.8 Max 1.5 ± 0.1
0.44 Max
0.44 Max
0.48 Max
0.53 Max
1.5 1.5
3.0
2.5 ± 0.1
4.25 Max
0.8 Min
φ1
0.4
(1.5)
(2.5)
(0.4)
(0.2)
Package Name
PLZZ0004CA-A UPAK / UPAKV
MASS[Typ.]
0.050g
SC-62
RENESAS CodeJEITA Package Code
Unit: mm
Ordering Information
Part Name Quantity Shipping Container
2SK2315TYTL-E 1000 pcs Taping
2SK2315TYTR-E 1000 pcs Taping
Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of
production before ordering the product.
1.5
1.5
3.0
Shipping Container
Taping
Taping
Note: For some grades, production may be terminated. Please
contact the Renesas sales office to check the state of
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© 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .3.0
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placeme
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas T
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents i
publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvement
therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distrib
information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies o
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Techn
home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, a
evaluate all information as a total system before making a final decision on the applicability of the information and products.
no responsibility for any damage, liability or other loss resulting from the information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under ci
is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor
product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerosp
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materi
7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a lic
cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is
8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
" for the latest and detailed information.
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