1. Features
•Write Protect Pin for Hardware Data Protection
– Utilizes Different Array Protection Compared to the AT24C02B/04B
•Medium-voltage and Standard-voltage Operation
– 2.5 (VCC = 2.5V to 5.5V)
•Automotive Temperature Range –40°C to 125°C
•Internally Organized 256 x 8 (2K), 512 x 8 (4k)
•Two-wire Serial Interface
•Schmitt Trigger, Filtered Inputs for Noise Suppression
•Bidirectional Data Transfer Protocol
•400 kHz (2.5V) Compatibility
•Write Protect Pin for Hardware Data Protection
•8-byte Page (2k), 16-byte Page (4k) Write Modes
•Partial Page Writes are Allowed
•Self-timed Write Cycle (5 ms max)
•High-reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
•8-lead JEDEC SOIC and 8-lead TSSOP Packages
2. Description
The AT24HC02B/04B provides 2048/4096 bits of serial electrically erasable and pro-
grammable read-only memory (EEPROM) organized as 256/512 words of 8 bits each.
The device is optimized for use in many automotive applications where low-power and
low-voltage operation are essential. The AT24HC02B/04B is available in space-sav-
ing 8-lead JEDEC SOIC and 8-lead TSSOP packages and is accessed via a two-wire
serial interface. In addition, the entire family is available in 2.5V (2.5V to 5.5V)
versions.
Table 2-1. Pin Configurations
Pin Name Function
A0 − A2 Address Inputs
SDA Serial Data
SCL Serial Clock Input
WP Write Protect
NC No Connect
Two-wire
Automotive
Temperature
Serial EEPROM
2K (256 x 8)
4k (512 x 8)
AT24HC02B
AT24HC04B
5192C–SEEPR–01/09
8-lead SOIC
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
8-lead TSSOP
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
2
5192C–SEEPR–01/09
AT24HC02B/04B
Figure 2-1. Block Diagram
3. Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM
device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-
drain driven and may be wire-ORed with any number of other open-drain or open-collector
devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs
that are hard wired for the AT24HC02B. As many as eight 2K devices may be addressed on a
single bus system (device addressing is discussed in detail under the Device Addressing
section).
Absolute Maximum Ratings
Operating Temperature......................................−55°C to +125°C*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Temperature .........................................−65°C to +150°C
Voltage on Any Pin
with Respect to Ground ........................................ −1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
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5192C–SEEPR–01/09
AT24HC02B/04B
The AT24HC04B uses the A2 and A1 inputs for hardware addressing, and a total of four 4K
devices may be addressed on a single bus system. The A0 pin is a no-connect.
WRITE PROTECT (WP): The AT24HC02B/04B have a Write Protect pin that provides hardware
data protection. The Write Protect pin allows normal read/write operations when connected to
ground (GND). When the Write Protect pin is connected to VCC, the write protection feature is
enabled and operates as shown in the following table.
Table 3-1. Write Protect
WP Pin
Status
Part of the Array Protected
AT24HC02B/04B
At VCC Upper Half (1K/2K) Array
At GND Normal Read/Write Operations
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5192C–SEEPR–01/09
AT24HC02B/04B
4. Memory Organization
AT24HC02B, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each, the 2K
requires an 8-bit data word address for random word addressing.
AT24HC04B, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each. Ran-
dom word addressing requires a 9-bit data word address.
Note: 1. This parameter is characterized and is not 100% tested.
Note: 1. VIL min and VIH max are reference only and are not tested.
Table 4-1. Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +2.5V
Symbol Test Condition Max Units Conditions
CI/O Input/Output Capacitance (SDA) 8 pF VI/O = 0V
CIN Input Capacitance (A0, A1, A2, SCL) 6 pF VIN = 0V
Table 4-2. DC Characteristics
Applicable over recommended operating range from: TA = −40°C to +125°C, VCC = +2.5V to +5.5V (unless otherwise noted)
Symbol Parameter Test Condition Min Typ Max Units
VCC1 Supply Voltage 2.5 5.5 V
ICC Supply Current VCC = 5.0V Read at 100 kHz 0.4 1.0 mA
ICC Supply Current VCC = 5.0V Write at 100 kHz 2.0 3.0 mA
ISB1 Standby Current VCC = 2.5V VIN = VCC or VSS 1.6 4.0 µA
ISB2 Standby Current VCC = 5.0V VIN = VCC or VSS 8.0 18.0 µA
ILI Input Leakage Current VIN = VCC or VSS 0.10 3.0 µA
ILO Output Leakage Current VOUT = VCC or VSS 0.05 3.0 µA
VIL Input Low Level(1) −0.6 VCC x 0.3V
VIH Input High Level(1) VCC x 0.7 VCC + 0.5 V
VOL Output Low Level VCC = 2.5V IOL = 3.0 mA 0.4 V
5
5192C–SEEPR–01/09
AT24HC02B/04B
Notes: 1. This parameter is characterized and is not 100% tested (TA = 25°C).
2. This parameter is ensured by characterization only.
Table 4-3. AC Characteristics
Applicable over recommended operating range from TA = −40°C to +125°C, VCC = +2.5V to +5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted)
Symbol Parameter Min Max Units
fSCL Clock Frequency, SCL 400 kHz
tLOW Clock Pulse Width Low 1.2 µs
tHIGH Clock Pulse Width High 0.6 µs
tINoise Suppression Time(1) 50 ns
tAA Clock Low to Data Out Valid 0.1 0.9 µs
tBUF
Time the bus must be free before
a new transmission can start(2) 1.2 µs
tHD.STA Start Hold Time 0.6 µs
tSU.STA Start Set-up Time 0.6 µs
tHD.DAT Data In Hold Time 0 µs
tSU.DAT Data In Set-up Time 100 ns
tRInputs Rise Time(2) 300 ns
tFInputs Fall Time(2) 300 ns
tSU.STO Stop Set-up Time 0.6 µs
tDH Data Out Hold Time 50 ns
tWR Write Cycle Time 5 ms
Endurance(2) 5.0V, 25°C, Page Mode 1M Write Cycles
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5192C–SEEPR–01/09
AT24HC02B/04B
5. Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device.
Data on the SDA pin may change only during SCL low time periods (see to Figure 7-2 on page
7). Data changes during SCL high periods will indicate a start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which
must precede any other command (see to Figure 7-3 on page 8).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a
read sequence, the stop command will place the EEPROM in a standby power mode (see Fig-
ure 7-3 on page 8).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a “0” to acknowledge that it has received each
word. This happens during the ninth clock cycle.
STANDBY MODE: The AT24HC02B/04B features a low-power standby mode which is enabled:
(a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal
operations.
SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any two-wire
part can be protocol reset by following these steps (a) Create a start bit condition. (b) Clock nine
cycles. (c) Create another start bit followed by stop bit condition as shown below. The device is
ready for next communication after above steps have been completed.
Figure 5-1. Software Reset Protocol
SCL
SDA
123 89
Start Bit Start Bit Stop Bit
Dummy Clock Cycles
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5192C–SEEPR–01/09
AT24HC02B/04B
6. Bus Timing
Figure 6-1. SCL: Serial Clock, SDA: Serial Data I/O
7. Write Cycle Timing
Figure 7-1. SCL: Serial Clock, SDA: Serial Data I/O
Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
Figure 7-2. Data Validity
twr
(1)
STOP
CONDITION
START
CONDITION
WORDn
ACK
8th BIT
SCL
SDA
8
5192C–SEEPR–01/09
AT24HC02B/04B
Figure 7-3. Start and Stop Definition
Figure 7-4. Output Acknowledge
8. Device Addressing
The 2Kand 4K EEPROM devices all require an 8-bit device address word following a start condi-
tion to enable the chip for a read or write operation (see to Figure 10-1 on page 10).
The device address word consists of a mandatory “1”, “0” sequence for the first four most signif-
icant bits as shown. This is common to all the Serial EEPROM devices.
The next 3 bits are the A2, A1 and A0 device address bits for the 2K EEPROM. These 3 bits
must compare to their corresponding hardwired input pins.
The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory
address bit (See Figure 10-1). The two device address bits must compare to their corresponding
hardwired input pins. The A0 pin is no-connect.
The eighth bit of the device address is the read/write operation select bit. A read operation is ini-
tiated if this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a “0”. If a compare is not made,
the chip will return to a standby state.
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5192C–SEEPR–01/09
AT24HC02B/04B
9. Write Operations
BYTE WRITE: A write operation requires an 8-bit data word address following the device
address word and acknowledgment. Upon receipt of this address, the EEPROM will again
respond with a “0” and then clock in the first 8-bit data word. Following receipt of the 8-bit data
word, the EEPROM will output a “0” and the addressing device, such as a microcontroller, must
terminate the write sequence with a stop condition. At this time the EEPROM enters an internally
timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle
and the EEPROM will not respond until the write is complete (see Figure 10-2 on page 10).
PAGE WRITE: The 2K EEPROM is capable of an 8-byte page write, and the 4K EEPROM
device is capable of 16-byte page writes.
A page write is initiated the same as a byte write, but the microcontroller does not send a stop
condition after the first data word is clocked in. Instead, after the EEPROM acknowledges
receipt of the first data word, the microcontroller can transmit up to seven (2K) or sixtenn (4K)
more data words. The EEPROM will respond with a “0” after each data word received. The
microcontroller must terminate the page write sequence with a stop condition (see Figure 10-3
on page 11).
The data word address lower three bits (2K) or four (4K) are internally incremented following the
receipt of each data word. The higher data word address bits are not incremented, retaining the
memory page row location. When the word address, internally generated, reaches the page
boundary, the following byte is placed at the beginning of the same page. If more than eight (2K)
or sixteen (4K) data words are transmitted to the EEPROM, the data word address will “roll over”
and previous data will be overwritten.
ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a
start condition followed by the device address word. The read/write bit is representative of the
operation desired. Only if the internal write cycle has completed will the EEPROM respond with
a “0”, allowing the read or write sequence to continue.
10
5192C–SEEPR–01/09
AT24HC02B/04B
10. Read Operations
Read operations are initiated the same way as write operations with the exception that the
read/write select bit in the device address word is set to “1”. There are three read operations:
current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last
address accessed during the last read or write operation, incremented by one. This address
stays valid between operations as long as the chip power is maintained. The address “roll over”
during read is from the last byte of the last memory page to the first byte of the first page. The
address “roll over” during write is from the last byte of the current page to the first byte of the
same page.
Once the device address with the read/write select bit set to “1” is clocked in and acknowledged
by the EEPROM, the current address data word is serially clocked out. The microcontroller does
not respond with an input “0” but does generate a following stop condition (see Figure 10-5 on
page 11).
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data
word address. Once the device address word and data word address are clocked in and
acknowledged by the EEPROM, the microcontroller must generate another start condition. The
microcontroller now initiates a current address read by sending a device address with the
read/write select bit high. The EEPROM acknowledges the device address and serially clocks
out the data word. The microcontroller does not respond with a “0” but does generate a following
stop condition (see Figure 10-4 on page 11).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a ran-
dom address read. After the microcontroller receives a data word, it responds with an
acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment
the data word address and serially clock out sequential data words. When the memory address
limit is reached, the data word address will “roll over” and the sequential read will continue. The
sequential read operation is terminated when the microcontroller does not respond with a “0” but
does generate a following stop condition (see Figure 10-6 on page 11).
Figure 10-1. Device Address
Figure 10-2. Byte Write
4K 1 0 1 0 A A P R/W
2K 1 0 1 0 A A A R/W
MSBLSB
LSBMSB
11
5192C–SEEPR–01/09
AT24HC02B/04B
Figure 10-3. Page Write
Figure 10-4. Current Address Read
Figure 10-5. Random Read
Figure 10-6. Sequential Read
12
5192C–SEEPR–01/09
AT24HC02B/04B
Notes: 1. “-B” denotes bulk.
2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP = 5K per reel.
11. AT24HC02B Ordering Information
Ordering Code Package Operation Range
AT24HC02BN-SP25-B(1)
AT24HC02BN-SP25-T(2)
AT24HC02B-TP25-B(1)
AT24HC02B-TP25-T(2)
8S1
8S1
8A2
8A2
Lead-free/Halogen-free/NiPdAu Lead
Finish/Automotive Temperature
(−40°C to 125°C)
Package Type
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
Options
−2.5 Low-voltage (2.5V to 5.5V)
13
5192C–SEEPR–01/09
AT24HC02B/04B
Notes: 1. “-B” denotes bulk.
2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP = 5K per reel.
12. AT24HC04B Ordering Information
Ordering Code Package Operation Range
AT24HC04BN-SP25-B(1)
AT24HC04BN-SP25-T(2)
AT24HC04B-TP25-B(1)
AT24HC04B-TP25-T(2)
8S1
8S1
8A2
8A2
Lead-free/Halogen-free/NiPdAu Lead
Finish/Automotive Temperature
(−40°C to 125°C)
Package Type
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
Options
−2.5 Low-voltage (2.5V to 5.5V)
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5192C–SEEPR–01/09
AT24HC02B/04B
13. Packaging Information
13.1 8A2 - TSSOP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
5/30/02
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
D 2.90 3.00 3.10 2, 5
E 6.40 BSC
E1 4.30 4.40 4.50 3, 5
A – – 1.20
A2 0.80 1.00 1.05
b 0.19 – 0.30 4
e 0.65 BSC
L 0.45 0.60 0.75
L1 1.00 REF
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
8A2 B
Side View
End View
Top View
A2
A
L
L1
D
123
E1
N
b
Pin 1 indicator
this corner
E
e
15
5192C–SEEPR–01/09
AT24HC02B/04B
13.2 8S1 – JEDEC SOIC
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE DRAWING NO.
R
REV.
Note:
10/7/03
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC) 8S1 B
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A1 0.10 – 0.25
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
A 1.35 – 1.75
b 0.31 – 0.51
C 0.17 – 0.25
D 4.80 – 5.00
E1 3.81 – 3.99
E 5.79 – 6.20
e 1.27 BSC
L 0.40 – 1.27
∅ 0˚ – 8˚
∅
Top View
End View
Side View
eB
D
A
A1
N
E
1
C
E1
L
16
5192C–SEEPR–01/09
AT24HC02B/04B
14. Revision History
Doc. Rev. Date Comments
5192C 1/2009 Removed Preliminary status.
5192B 3/2008 Added information for AT24HC04B.
Updated to new template.
5192A 1/2007 Initial document release.
5192C–SEEPR–01/09
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