NT5TU128M4AF-37A - Nanya Technology Corporation

NT5TU128M4AF

NT5TU64M8AF

NT5TU32MHAF

512Mb DDR2 SDRAM

REV 1.0

09/2004

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Features

CAS Latency and Frequency

• 1.8V ± 0.1V Power Supply Voltage

• 4 internal memory banks

• Programmable CAS Latency: 3, 4 and 5

• Programmable Additive Latency: 0, 1, 2, 3 and 4

• Write Latency = Read Latency -1

• Programmable Burst Length: 4 and 8

• Programmable Sequential / Interleave Burst

• OCD (Off-Chip Driver Impedance Adjustment)

• ODT (On-Die Termination)

• 4 bit prefetch architecture

• 1k page size for x 4 & x 8,

2k page size for x16

• Data-Strobes: Bidirectional, Differential

• Strong and Weak Strength Data-Output Driver

• Auto-Refresh and Self-Refresh

• Power Saving Power-Down modes

• 7.8 µs max. Average Periodic Refresh Interval

•Packages:

60 pin FBGA for x4 & x8 components

84 pin FBPA for x16 components

Description

The 512Mb Double-Data-Rate-2 (DDR2) DRAMs is a high-

speed CMOS Double Data Rate 2 SDRAM containing

536,870,912 bits. It is internally configured as a quad-bank

DRAM.

The 512Mb chip is organized as either 32Mbit x 4 I/O x 4

bank, 16Mbit x 8 I/O x 4 bank or 8Mbit x 16 I/O x 4 bank

device. These synchronous devices achieve high speed dou-

ble-data-rate transfer rates of up to 667 Mb/sec/pin for gen-

eral applications.

The chip is designed to comply with all key DDR2 DRAM key

features: (1) posted CAS with additive latency, (2) write

latency = read latency -1, (3) normal and weak strength data-

output driver, (4) variable data-output impedance adjustment

and (5) an ODT (On-Die Termination) function.

All of the control and address inputs are synchronized with a

pair of externally supplied differential clocks. Inputs are

latched at the cross point of differential clocks (CK rising and

CK falling). All I/Os are synchronized with a single ended

DQS or differential DQS pair in a source synchronous fash-

ion. A 16 bit address bus for x4 and x8 organised compo-

nents and a 15 bit address bus for x16 components is used to

convey row, column, and bank address devices.

These devices operate with a single 1.8V +/-0.1V power sup-

ply and are available in FBGA packages.

An Auto-Refresh and Self-Refresh mode is provided along

with various power-saving power-down modes.

Speed Sorts

-5

DDR2

-400

-3.7

DDR2

-533

-3

DDR2

-667

Units

Bin (CL-tRCD-TRP) 3-3-3 4-4-4 4-4-4 tck

max. Clock

Frequency 200 266 333 MHz

Data Rate 400 533 667 Mb/s/pin

CAS Latency 3 4 4 tck

tRCD 15 15 12 ns

tRP 15 15 12 ns

tRC 60 60 57 ns

NT5TU128M4AF

NT5TU64M8AF

NT5TU32MHAF

512Mb DDR2 SDRAM

REV 1.0

09/2004

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Pin Configuration - 60 balls 0.8mmx0.8mm Pitch WBGAPackage

See the balls through the package.

x 4

VDD

VDDQ

VDDL

VSS

VSSQ

DQ1

VSSQ

VREF

CKE

BA0

A10

A12

VSS

VDDQ

DQ3

VSS

BA1

NC,A14

3 7 8 9

VDD

VDDQ

VDD

DQS

VSSQ

DQ0

VSSQ

A13

VSSQ

DQS

VDDQ

DQ2

VSSDL

RAS

A11

NC,A15

VSS

RFU

ODT

CAS

VDD

DQ6

VDDQ

DQ4

VDDL

VSS

NU, RDQS

VSSQ

DQ1

VSSQ

VREF

CKE

BA0

A10

A12

VSS

DM,RDQS

VSSQ

VDDL

BA1

NC,A14

3 7 8 9

VDD

VDDQ

DQ7

VDDQ

DQ5

VDD

DQS

VSSQ

DQ0

VSSQ

A13

VSSQ

DQS

VDDQ

DQ2

VSSDL

RAS

CAS

A11

NC,A15

VSS

RFU

ODT

NT5TU128M4AF

NT5TU64M8AF

NT5TU32MHAF

512Mb DDR2 SDRAM

REV 1.0

09/2004

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Pin Configuration - 84 balls 0.8mmx0.8mm Pitch WBGA Package

See the balls through the package.

x 16

VDD

UDQ6

VDDQ

UDQ4

VDD

LDQ4

VSSQ

UDQ1

VSSQ

LDQ1

VSSQ

VREF

CKE

A10

VSS

UDM

VDDQ

DQ3

VSS

LDM

VDDQ

LDQ3

VSS

BA1

3 7 8 9

VDDQ

UDQ7

VDDQ

UDQ5

VDDQ

VDD

UDQS

VSSQ

UDQ0

VSSQ

LDQS

VSSQ

LDQ0

VSSQ

UDQS

VDDQ

UDQ2

VSSQ

LDQS

VDDQ

VSSDL

RAS

CAS

VDD

LDQ6

VDDQ

VDDL

A12VDD

BA0

NC,A14 NC,A15

A11

LDQ2

NC,A13

LDQ7

VDDQ

LDQ5

VSS

RFU

VSS

ODT

NT5TU128M4AF

NT5TU64M8AF

NT5TU32MHAF

512Mb DDR2 SDRAM

REV 1.0

09/2004

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Input/Output Functional Description

Symbol Type Function

CK, CK Input

Clock: CK and CK are differential clock inputs. All address and control input signals are sampled

on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is refer-

enced to the crossings of CK and CK (both directions of crossing).

CKE Input

Clock Enable: CKE high activates and CKE low deactivates internal clock signals and device

input buffers and output drivers. Taking CKE low provides Precharge Power-Down and Self-

Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is syn-

chronous for power down entry and exit and for Self-Refresh entry. CKE is asynchronous for Self-

Refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers,

excluding CK, CK, ODT and CKE are disabled during Power Down. Input buffers, excluding CKE

are disabled during Self-Refresh.

CS Input Chip Select: All command are masked when CS is registered high. CS provides for external rank

selection on systems with multiple memory ranks. CS is considered part of the command code.

RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.

DM, LDM, UDM Input

Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is

sampled high coincident with that input data during a Write access. DM is sampled on both edges

of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. LDM

and UDM are the input mask signals for x16 components and control the lower or upper bytes. For

x8 components the data mask function is disabled, when RDQS / RQDS are enabled by EMRS(1)

command.

BA0, BA1 Input

Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge

command is being applied. BA0 and BA1 also determines if the mode register or extended mode

A0 - A13 Input

Address Inputs: Provides the row address for Activate commands and the column address and

Auto-Precharge bit A10 (=AP) for Read/Write commands to select one location out of the memory

array in the respective bank. A10 (=AP) is sampled during a Precharge command to determine

whether the Precharge applies to one bank (A10=low) or all banks (A10=high). If only one bank is

to be precharged, the bank is selected by BA0 and BA1. The address inputs also provide the op-

code during Mode Register Set commands.

Row address A13 is used on x4 and x8 components only.

DQx,

LDQx,UDQx Input/Output Data Inputs/Output: Bi-directional data bus. DQ0~DQ3 for x4 components, DQ0~DQ7 for x8

components, LDQ0~LDQ7 and UDQ0~UDQ7 for x16 components

DQS, (DQS)

LDQS, (LDQS),

UDQS,(UDQS)

Input/Output

Data Strobe: output with read data, input with write data. Edge aligned with read data, centered

with write data. For the x16, LDQS corresponds to the data on LDQ0 - LDQ7; UDQS corresponds

to the data on UDQ0-UDQ7. The data strobes DQS, LDQS, UDQS may be used in single ended

mode or paired with the optional complementary signals DQS, LDQS, UDQS to provide differen-

tial pair signaling to the system during both reads and writes. An EMRS(1) control bit enables or

disables the complementary data strobe signals.

RDQS, (RDQS) Input/Output

Read Data Strobe: For the x8 components a RDQS, RDQS pair can be enabled via the EMRS(1)

for read timing. RDQS, RDQS is not supported on x4 and x16 components. RDQS, RDQS are

edge-aligned with read data. If RDQS, RDQS is enabled, the DM function is disabled on x8 com-

ponents.

ODT Input

On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2

SDRAM. When enabled, ODT is applied to each DQ, DQS, DQS and DM signal for x4 and DQ,

DQS, DQS, RDQS, RDQS and DM for x8 configurations. For x16 configuration ODT is applied to

each DQ, UDQS, UDQS, LDQS, LDQS, UDM and LDM signal. The ODT pin will be ignored if the

EMRS(1) is programmed to disable ODT.

NC No Connect: No internal electrical connection is present.

VDDQ Supply DQ Power Supply: 1.8V +/- 0.1V

VSSQ Supply DQ Ground

VDDL Supply DLL Power Supply: 1.8V +/- 0.1V

VSSDL Supply DLL Ground

VDD Supply Power Supply: 1.8V +/- 0.1V

VSS Supply Ground

NT5TU128M4AF

NT5TU64M8AF

NT5TU32MHAF

512Mb DDR2 SDRAM

REV 1.0

09/2004

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

VREF Supply SSTL_1.8 reference voltage

(BA2),

(A14~A15) -BA2, A14 ~ A15 are additional address pins for future generation DRAMs and are not connected on this

component.

Input/Output Functional Description

Symbol Type Function

NT5TU128M4AF

NT5TU64M8AF

NT5TU32MHAF

512Mb DDR2 SDRAM

REV 1.0

09/2004

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Ordering Information

Org. Part Number Package

Speed

Clock (MHz) CL-tRCD-tRP

128M x 4

NT5TU128M4AF-5A

60ball BGA

0.8mmx0.8mm

Pitch

200 3-3-3

NT5TU128M4AF-5B 200 4-4-4

NT5TU128M4AF-37A 266 3-3-3

NT5TU128M4AF-37B 266 4-4-4

NT5TU128M4AF-3B 333 4-4-4

NT5TU128M4AF-3C 333 5-5-5

64M x 8

NT5TU64M8AF-5A

60ball BGA

0.8mmx1.0mm

Pitch

200 3-3-3

NT5TU64M8AF-5B 200 4-4-4

NT5TU64M8AF-37A 266 3-3-3

NT5TU64M8AF-37B 266 4-4-4

NT5TU64M8AF-3B 333 4-4-4

NT5TU64M8AF-3C 333 5-5-5

32M x 16

NT5TU32MHAF-5A

84ball BGA

0.8mmx0.8mm

Pitch

200 3-3-3

NT5TU32MHAF-5B 200 4-4-4

NT5TU32MHAF-37A 266 3-3-3

NT5TU32MHAF-37B 266 4-4-4

NT5TU32MHAF-3B 333 4-4-4

NT5TU32MHAF-3C 333 5-5-5

Note:

NT5TU128M4AF

NT5TU64M8AF

NT5TU32MHAF

512Mb DDR2 SDRAM

REV 1.0

09/2004

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Block Diagram (128Mb x 4)

Receivers

DQS

CK, CK

DLL

RAS

CAS

Control Logic

Column-Address

Counter/Latch

Mode

Command

Decode

A0-A13,

BA0, BA1

CKE

I/O Gating

DM Mask Logic

Bank0

Memory

Array

(16384 x 512 x 16)

Sense Amplifiers

Bank1 Bank2 Bank3

Refresh Counter

Input

Data

Mask

Data

CK,

COL0,1

MUX

DQS

Generator

DQ0-DQ3,

DQS

Read Latch

Write

FIFO

Drivers

Column

Decoder

512

(x16)

Row-Address MUX

Registers

8192

Bank0

Row-Address Latch

& Decoder

16384

Address Register

Drivers

Bank Control Logic

DQS

Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of the

device; it does not represent an actual circuit implementation.

Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional

DQ and DQS signals.

NT5TU128M4AF

NT5TU64M8AF

NT5TU32MHAF

512Mb DDR2 SDRAM

REV 1.0

09/2004

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Block Diagram (64Mb x 8)

RAS

CAS

Control Logic

Column-Address

Counter/Latch

Mode

Command

Decode

A0-A13,

BA0, BA1

CKE

I/O Gating

DM Mask Logic

Bank0

Memory

Array

(16384 x256x32)

Sense Amplifiers

Bank1 Bank2 Bank3

Refresh Counter

COL0,1

DQ0-DQ7,

DQS

Column

Decoder

256

(x32)

Row-Address MUX

Registers

8192

Bank0

Row-Address Latch

& Decoder

16384

Address Register

Bank Control Logic

Receivers

DQS

CK, CK

DLL

Input

Data

Mask

Data

CK,

COL0,1

MUX

DQS

Generator

Read Latch

Write

FIFO

Drivers

DQS

Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of the

device; it does not represent an actual circuit implementation.

Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional

DQ and DQS signals.

NT5TU128M4AF

NT5TU64M8AF

NT5TU32MHAF

512Mb DDR2 SDRAM

REV 1.0

09/2004

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Block Diagram (32Mb x 16)

RAS

CAS

Control Logic

Column-Address

Counter/Latch

Mode

Command

Decode

A0-A12,

BA0, BA1

CKE

I/O Gating

DM Mask Logic

Bank0

Memory

Array

(8192 x 256 x 64)

Sense Amplifiers

Bank1 Bank2 Bank3

Refresh Counter

COL0

LDQ0-LDQ7

LDM

LDQS

Column

Decoder

256

(x64)

Row-Address MUX

Registers

16384

Bank0

Row-Address Latch

& Decoder

8192

Address Register

Bank Control Logic

Receivers

DQS

CK, CK

DLL

Input

Data

Mask

Data

CK,

COL0,1

MUX

DQS

Generator

Read Latch

Write

FIFO

Drivers

DQS

16 16

LDQS

UDQS

UDQ0-UDQ7

UDM

Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of the

device; it does not represent an actual circuit implementation.

Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirec-

tional DQ and DQS signals.

NT5TU128M4AF

NT5TU64M8AF

NT5TU32MHAF

512Mb DDR2 SDRAM

REV 1.0

09/2004

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Functional Description

The 512Mb DDR2 SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. The 512Mb

DDR SDRAM is internally configured as a quad-bank DRAM.

The 512Mb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data-rate archi-

tecture is essentially a 4n prefetch architecture, with an interface designed to transfer four data words per clock cycle at the I/O

pins. A single read or write access for the 512Mb DDR SDRAM consists of a single 4n-bit wide, one clock cycle data transfer at

the internal DRAM core and four corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins.

Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for the

burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Activate command, which is

followed by a Read or Write command. The address bits registered coincident with the activate command are used to select the

bank and row to be accesses (BA0 & BA1 select the banks, A0-A13 select the row for x4 and x8 components, A0~A12 select

the row for x16 components). The address bits registered coincident with the Read or Write command are used to select the

starting column location for the burst access and to determine if the Auto-Precharge command is to be issued.

Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information covering

device initialization, register definition, command description and device operation.

Initialization

DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified

may result in undefined operation. Power-Up and Initialization Sequence

The following sequence is required for POWER UP and Initialization.

1. Apply power and attempt to maintain CKE below 0.2 * VDDQ and ODT at a low state (all other inputs may be

undefined). To guarantee ODT off, VREF must be valid and a low level must be applied to the ODT pin.

- VDD,VDDL and VDDQ are driven from a signle power converter output, AND

- VTT is limited to 0.95 V max, AND

- VREF tracks VDDQ/2

- Apply VDD before or at the same time as VDDL,

- Apply VDDL before or at the same time as VDDQ.

- Apply VDDQ before or at the same time as VTT & VREF.

at least one of these two sets of conditions must be met.

2. Start clock (CK, CK) and maintain stable power and clock condition for a minimum of 200 µs.

3. Apply NOP or Deselect commands & take CKE high.

4. Wait minimum of 400ns, then issue a Precharge-all command.

5. Issue EMRS(2) command. (To issue EMRS(2) command, provide “low” to BA0 and BA2 and “high” to BA1)

6. Issue EMRS(3) command. (To issue EMRS(3) command, provide “low” to BA2 and “high” to BA0 and BA1)

7. Issue EMRS(1) command to enable DLL. (To issue “DLL Enable” command, provide “low” to A0 and

“high” to BA0 and “low” to BA1,BA2 and A13~A15)

8. Issue MRS command (Mode Register Set) for "DLL reset". (To issue DLL reset command, provide “high” to A8

and “low” to BA0 ~ BA2 and A13 ~ A15)

9. Issue Precharge-All command.

10. Issue 2 or more Auto-Refresh commands.

11. Issue a MRS command with low on A8 to initialize device operation. (i.e. to programm operating paramters with

out resetting the DLL)

12. At least 200 clocks after step 8, execute OCD Calibration (Off Chip Driver impedance adjustment). If OCD cali-

bration is not used, EMRS OCD Default command (A9=A8=A7=1) followed by EMRS(1) OCD Calibration Mode

Exit command (A9=A8=A7=0) must be issued with other parameters of EMRS(1).

13. The DDR2 SDRAM is now read for normal operation.

NT5TU128M4AF

NT5TU64M8AF

NT5TU32MHAF

512Mb DDR2 SDRAM

REV 1.0

09/2004

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Example

Programming the Mode Register and Extended Mode Registers

For application flexibility, burst length, burst type, CAS latency, DLL reset function, write recovery time (WR) are user defined

variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLL disable function, additive

CAS latency, driver impedance, ODT (On Die Termination), single-ended strobe and OCD (off chip driver impedance adjust-

ment) are also user defined variables and must be programmed with an Extended Mode Register Set (EMRS) command. Con-

tents of the Mode Register (MRS) and Extended Node Registers (EMRS(#)) can be altered by re-executing the MRS and EMRS

Commands. If the user chooses to modify only a subset of the MRS or EMRS variables, all variables must be redefined when

the MRS or EMRS commands are issued. Also any programmig of EMRS(2) or EMRS(3) must be followed by programming of

MRS and EMRS(1). After initial power up, all MRS and EMRS Commands must be issued before read or write cycles may

begin. All banks must be in a precharged state and CKE must be high at least one cycles before the Mode Register Set Com-

mand can be issued. Either MRS or EMRS Commands are activated by the low signals of CS, RAS, CAS and WE at the posi-

tive edge of the clock. When both bank addresses BA0 and BA1 are low, the DDR2 SDRAM enables the MRS command. When

the bank addresses BA0 is high and BA1 low, the DDR2 SDRAM enables the EMRS(1) command. The address input data dur-

ing this cycle defines the parameters to be set as shown in the MRS and EMRS table. A new command may be issued after the

mode register set command cycle time (tMRD). MRS, EMRS and DLL Reset do not affect array contents, which means reinitial-

izazion including those can be executed any time after power-up without affecting array contents.

Mode Register Set (MRS)

The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It programs CAS latency, burst

length, burst sequence, test mode, DLL reset, WR (write recovery) and various vendor specific options to make DDR2 SDRAM

useful for various applications. The default value of the mode register is not defined, therefore the mode register must be written

after power-up for proper operation. The mode register is written by asserting low on CS, RAS, CAS, WE, BA0 and BA1, while

controlling the state of address pins A0 ~ A13. The DDR2 SDRAM should be in all bank precharged (idle) mode with CKE

already high prior to writing into the mode register. The mode register set command cycle time (tMRD) is required to complete

the write operation to the mode register. The mode register contents can be changed using the same command and clock cycle

requirements during normal operation as long as all banks are in the precharged state. The mode register is divided into various

fields depending on functionality. Burst length is defined by A0 ~ A2 with options of 4 and 8 bit burst length. Burst address

sequence type is defined by A3 and CAS latency is defined by A4 ~ A6. A7 is used for test mode and must be set to low for

normal MRS operation. A8 is used for DLL reset. A9 ~ A11 are used for write recovery time (WR) definition for Auto-Precharge

mode. With address bit A12 two Power-Down modes can be selected, a “standard mode” and a “low-power” Power-Down

mode, where the DLL is disabled. Addess bit A13 and all “higher” address bits (including BA2) have to be set to “low” for com-

patibility with other DDR2 memory products with higher memory densities.

CK, CK

1st Auto

refresh

MRS

PRE

ALL

EMRS

CMD

2nd Auto

refresh

tRP tRP tRFC tRFC

Extended Mode

with DLL enable

Mode Register Set

with DLL reset

PRE

ALL

CMD

tMRS tMRS

min. 200 cycles

to lock the DLL

CKE

Command

400 ns

MRS

NOP

tMRS

EMRS

OCD

Follow OCD

flowchart

ODT "low"

NT5TU128M4AF

NT5TU64M8AF

NT5TU32MHAF

512Mb DDR2 SDRAM

REV 1.0

09/2004

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

MRS Mode Register Operation Table (Address Input For Mode Set)

A8 DLL Reset

0No

1 Yes

A12 Active Power-Down

Mode Select

0 Fast exit (use tXARD)

1 Slow exit (use tXARDS)

A11 A3A4 A2 A1 A0

A10 A9 A8 A7 A6 A5 Address Field

BT Burst LengthCAS Latency Mode

A6 A5 A4 Latency

000 Reserved

001 Reserved

0102

(optional) ***)

011 3

100 4

101 5

110 Reserved

111 Reserved

Burst Type

0 Sequential

1Interleave

BA1 BA0

A7 Mode

0Normal

1 Test

DLL

A11 A10 A9 WR **)

0 0 0 Reserved

001 2

010 3

011 4

100 5

101 6

1 1 0 Reserved

1 1 1 Reserved

A2 A1 A0 Burst Length

010 4

011 8

A13~ A12

0* 0*

BA1 BA0 MRS mode

00 MRS

01EMRS(1)

EMRS(2):

Reserved

EMRS(3):

Reserved

BA2

A15

*) Must be programmed to 0 when setting the mode register. A13 ~ A15 and BA2 are reserved for future use

and must be programmed to 0 when setting the mode register MRS

**) The programmability of WR (Write Recovery) is for Writes with Auto-Precharge only and defines the time

when the device starts precharge internally. WR must be programmed to fullfil the minimum reqirement for

the analogue tWR timing.

***) CAS Latency = 2 is implemented in this design, but functionality is not tested and guaranteed.

NT5TU128M4AF

NT5TU64M8AF

NT5TU32MHAF

512Mb DDR2 SDRAM

REV 1.0

09/2004

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Extended Mode Register Set (EMRS(1))

The extended mode register EMRS(1) stores the data for enabling or disabling the DLL, output driver strength, additive latency,

OCD program, ODT, DQS and output buffers disable, RQDS and RDQS enable. The default value of the extended mode regis-

ter EMRS(1) is not defined, therefore the extended mode register must be written after power-up for proper operation. The

extended mode register is written by asserting low on CS, RAS, CAS, WE, BA1 and high on BA0, while controlling the state of

the address pins.. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended

mode register. The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the

EMRS(1). Mode register contents can be changed using the same command and clock cycle requirements during normal oper-

ation as long as all banks are in precharge state.

EMRS(1) Extended Mode Register Operation Table (Address Input For Mode Set)

Address Field

RDQS

Extended Mode

DLL

D.I.C

BA1 BA0 A11 A10A9A8A7A6A5A4A3A2A1A0

Additive latency

A5 A4 A3 AdditiveLatency

000 0

001 1

010 2

011 3

100 4

1 0 1 Reserved

1 1 0 Reserved

1 1 1 Reserved

A9 A8 A7 OCD Calibration Program

000

OCD Cal. Mode Exit, maintain setting

001 Drive (1)

010 Drive (0)

100 Adjust mode

OCD program

DQS Rtt

A10

0 Enable

1 Disable

A0DLL Enable

0 Enable

1 Disable

Rtt

A6 Rtt (nom.)

0ODT disabled

175 ohm

150 ohm

Reserved

DQS,(RDQS) Disable

A12

A13~A15

0* Qoff

111

OCD Calibration default

*) must be programmed to 0 for compatibility with future DDR2 memory products.

A11

RDQS,(RQDS) Enable

0 Disable

1 Enable

A12 Qoff

Output buffers enabled

Output buffers disabled

BA2

BA0 MRS mode

0MRS

1EMRS(1)

BA1

EMRS(2):

Reserved

EMRS(3):

Reserved

a) When Adjust mode is issued, AL from previously set value must be applied

b) After setting to default, OCD mode needs to be exited by setting A9~A7 to 000.

Refer to the following 2.2.2.5 section for detailed information.

a) Disables DQ, DQS, DQS, RDQS, RDQS

A1 Output Driver

Impedence Control

Driver

Size

0 Normal 100%

1Weak 60%

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A0 is used for DLL enable or disable. A1 is used for enabling half-strength data-output driver. A2 and A6 enables ODT (On-Die

termination) and sets the Rtt value. A3~A5 are used for additive latency settings and A7 ~ A9 enables the OCD impedance

adjustment mode. A10 enables or disables the differential DQS and RDQS signals, A11 disables or enables RDQS. Address

bit A12 have to be set to “low” for normal operation. With A12 set to “high” the SDRAM outputs are disabled and in Hi-Z. “High”

on BA0 and “low” for BA1 have to be set to access the EMRS(1). A13 and all “higher” address bits (including BA2) have to be

set to “low” for compatibility with other DDR2 memory products with higher memory densities. Refer to the table for specific

codes on the previous page.

Single-ended and Differential Data Strobe Signals

The following table lists all possible combinations for DQS, DQS, RDQS, RQDS which can be programmed by A10 & A11

address bits in EMRS. RDQS and RDQS are available in x8 components only. If RDQS is enabled in x8 components, the DM

function is disabled. RDQS is active for reads and don’t care for writes :

DLL Enable/Disable

The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to nor-

mal operation after having the DLL disabled. The DLL is automatically disabled when entering Self-Refresh operation and is

automatically re-enabled and reset upon exit of Self-Refresh operation. Any time the DLL is reset, 200 clock cycles must occur

before a Read command can be issued to allow time for the internal clock to be synchronized with the external clock. Less clock

cycles may result in a violation of the tAC or tDQSCK parameters.

Output Disable (Qoff)

Under normal operation, the DRAM outputs are enabled during Read operation for driving data (Qoff bit in the EMRS(1) is set to

0). When the Qoff bit is set to 1, the DRAM outputs will be disabled. Disabling the DRAM outputs allows users to measure IDD

currents during Read operations, without including the output buffer current.

EMRS(2) and EMRS(3) Extended Mode Registers

The Extended Mode Registers EMRS(2) and EMRS(3) are reserved for future use and all bits except BA0 and BA1 must be

programmed to 0 when setting the mode register during initialization.

EMRS Stobe Function Matrix Signaling

A11

(RDQS Enable)

A10

(DQS Enable) RDQS/DM RDQS DQS DQS

0 (Disable) 0 (Enable) DM Hi-Z DQS DQS differential DQS signals

0 (Disable) 1 (Disable) DM Hi-Z DQS Hi-Z single-ended DQS signals

1 (Enable) 0 (Enable) RDQS RDQS DQS DQS differential DQS signals

1 (Enable) 1 (Disable) RDQS Hi-Z DQS Hi-Z single-ended DQS signals

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Off-Chip Driver (OCD) Impedance Adjustment

DDR2 SDRAM supports driver calibration feature and the flow chart below is an example of the sequence. Every

calibration mode command should be followed by “OCD calibration mode exit” before any other command being

issued. MRS should be set before entering OCD impedance adjustment and ODT (On Die Termination) should be

carefully controlled depending on system environment.

Start

EMRS: Drive (1)

DQ & DQS High; DQSLow

Test

EMRS :

Enter Adjus t Mode

BL=4 cod e inpu t to all DQs

Inc, Dec, or NOP

EMRS: Drive(0)

DQ & DQS Low; DQS High

Test

EMRS :

Enter Adjust Mode

BL=4 code input to all DQs

Inc, Dec, or NOP

EMRS: OCD calibration mode exit

End

ALL OK ALL OK

Need Calibration

EMRS: OCD calibration mode exit

MRS should be set before entering OCD impedance adjustment and ODT should

be carefully controlled depending on system environment

EMRS: OCD calibration mode exit

Need Calibration

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Extended Mode Register Set for OCD impedance adjustment

OCD impedance adjustment can be done using the following EMRS(1) mode. In drive mode all outputs are driven out by

DDR2 SDRAM and drive of RDQS is dependent on EMRS(1) bit enabling RDQS operation. In Drive(1) mode, all DQ, DQS

(and RDQS) signals are driven high and all DQS (and RDQS) signals are driven low. In Drive(0) mode, all DQ, DQS (and

RDQS) signals are driven low and all DQS (and RDQS) signals are driven high. In adjust mode, BL = 4 of operation code

data must be used. In case of OCD calibration default, output driver characteristics have a nominal impedance value of 18

Ohms during nominal temperature and voltage conditions. Output driver characteristics for OCD calibration default are speci-

fied in the following table. OCD applies only to normal full strength output drive setting defined by EMRS(1) and if half

strength is set, OCD default driver characteristics are not applicable. When OCD calibration adjust mode is used, OCD default

output driver characteristics are not applicable. After OCD calibration is completed or driver strength is set to default, subse-

quent EMRS(1) commands not intended to adjust OCD characteristics must specify A7~A9 as ’000’ in order to maintain the

default or calibrated value.

Off- Chip-Driver program

OCD impedance adjust

To adjust output driver impedance, controllers must issue the ADJUST EMRS(1) command along with a 4 bit burst code to

DDR2 SDRAM as in the following table. For this operation, Burst Length has to be set to BL = 4 via MRS command before

activating OCD and controllers must drive the burst code to all DQs at the same time. DT0 is the table means all DQ bits at bit

time 0, DT1 at bit time 1, and so forth. The driver output impedance is adjusted for all DDR2 SDRAM DQs simultaneously

and after OCD calibration, all DQs of a given DDR2 SDRAM will be adjusted to the same driver strength setting. The maxi-

mum step count for adjustment can be up to 16 and when the limit is reached, further increment or decrement code has no

effect. The default setting may be any step within the maximum step count range. When Adjust mode command is issued, AL

from previously set value must be applied.

Off- Chip-Driver Adjust Program

A9 A8 A7 Operation

000OCD calibration mode exit

001Drive(1) DQ, DQS, (RDQS) high and DQS, (RDQS) low

010Drive(0) DQ, DQS, (RDQS) low and DQS, (RDQS) high

100Adjust mode

111OCD calibration default

4 bit burst code inputs to all DQs Operation

DT0 DT1 DT2 DT3 Pull-up driver strength Pull-down driver strength

0000NOP (no operation) NOP (no operation)

0001Increase by 1 step NOP

0010Decrease by 1 step NOP

0100NOP Increase by 1 step

1000NOP Decrease by 1 step

0101Increase by 1 step Increase by 1 step

0110Decrease by 1 step Increase by 1 step

1001Increase by 1 step Decrease by 1 step

1010Decrease by 1 step Decrease by 1 step

Other Combinations Reserved Reserved

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For proper operation of adjust mode, WL = RL - 1 = AL + CL -1 clocks and tDS / tDH should be met as the following timing

diagram. Input data pattern for adjustment, DT0 - DT3 is fixed and not affected by MRS addressing mode (i.e. sequential or

interleave). Burst length of 4 have to be programmed in the MRS for OCD impedance adjustment.

Drive Mode

Drive mode, both Drive(1) and Drive(0), is used for controllers to measure DDR2 SDRAM Driver impedance before OCD

impedance adjustment. In this mode, all outputs are driven out tOIT after “enter drive mode” command and all output drivers

are turned-off tOIT after “OCD calibration mode exit” command as the following timing diagram.

NOP NOP NOP NOP

NOP

EMRS(1)

CMD

DQ_in

NOP

tWR

DQS_in

CK, CK

EMRS(1) NOP

DQS

OCD adjust mode OCD calibration

mode exit

tDS tDH

DT0 DT1 DT2 DT3

NOP NOP NOP

NOP

EMRS(1)

CMD

DQ_in

NOP

DQS_in

CK, CK

EMRS(1)

Enter Drive Mode OCD calibration

mode exit

NOP

DQS high & DQS low for Drive(1), DQS low & DQS high for Drive 0

DQS high for Drive(0)

DQS high for Drive(1)

tOIT tOIT

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On-Die Termination (ODT)

ODT (On-Die Termination) is a new feature on DDR2 components that allows a DRAM to turn on/off termination

resistance for each DQ, DQS, DQS and DM for x4 and DQ, DQS, DQS, DM, RDQS (DM and RDQS share the

same pin), and RDQS for x8 configuration via the ODT control pin, where DQS is terminated only when enabled

in the EMRS(1) by address bit A10 = 0. For x8 configuration RDQS is only terminated, when enabled in the

EMRS(1) by address bits A10 = 0 and A11 = 1.

For x16 configuration ODT is applied to each UDQ, LDQ, UDQS, UDQS, LDQS, LDQS, UDM and LDM signal via

the ODT control pin, where UDQS and LDQS are terminated only when enabled in the EMRS(1) by address bit

A10 = 0.

The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to

independently turn on/off termination resistance for any or all DRAM devices.

The ODT function can be used for all active and standby modes. ODT is turned off and not supported in Self-

Refresh mode.

Funtional Prepresentation of ODT

Switch sw1 or sw2 is enabled by the ODT pin. Selection between sw1 or sw2 is determined by “Rtt (nominal)” in EMRS(1)

address bits A6 & A2. Target Rtt = 0.5 * Rval1 or 0.5 * Rval2.

The ODT pin will be ignored if the Extended Mode Register (EMRS(1)) is programmed to disable ODT.

DRAM

Input

Buffer

Input

Rval1

Rval2

sw1

sw2

VDDQ VDDQ

VSSQ VSSQ

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ODT Truth Tables

The ODT Truth Table shows which of the input pins are terminated depending on the state of address bit A10 and A11 in the

EMRS(1) for all three device organisations (x4, x8 and x16). To activate termination of any of these pins, the ODT function

has to be enabled in the EMRS(1) by address bits A6 and A2.

Input Pin EMRS(1)

Adress Bit A10

EMRS(1)

Adress Bit A11

x4 components:

DQ0~DQ3 X X

DQS X X

DQS 0X

DM X X

x8 components:

DQ0~DQ7 X X

DQS X X

DQS 0X

RDQS X 1

RDQS 01

DM X 0

x16 components:

LDQ0~LDQ7 XX

UDQ0~UDQ7 XX

LDQS XX

LDQS 0X

UDQS XX

UDQS 0X

LDM XX

UDM XX

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ODT Timing for Active / Standby (Idle) Mode and Standard Active Power-Down Mode

ODT Timing for Precharge Power-Down and Low Power Power-Down Mode

1) Both ODT to Power Down Entry and Exit Latency timing parameter tANPD and tAXPD are met, therefore Non-Power Down Mode timings

have to be applied.

2) ODT turn-on time (tAON,min) is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time

max. (tAON,max) is when the ODT resistance is fully on. Both are measured from tAOND.

3) ODT turn off time min. ( tAOF,min) is when the device starts to turn off the ODT resistance.ODT turn off time max. (tAOF,max) is

when the bus is in high impedance. Both are measured from tAOFD.

CKE

ODT1

ODT

CK, CK

Rtt

tAON(min)

tAON(max) tAOF(max)

tAOF(min)

tAOND (2 tck) tAOFD (2.5 tck)

tANPD (>=3 tck)

tAXPD (>=6 tck)

T-3 T-1

T-2T-6 T-4

T-5

T-n

1) Both ODT to Power Down Entry and Exit Latencies tANPD and tAXPD are not met, therefore Power-Down Mode timings have to be applied.

CKE

ODT

ODT2

CK, CK

tAOFPD,min

Rtt

tAONPD,min

tAOFPD,max

tAONPD,max

tANPD < 3 tck

tAXPD < 6 tck

T0 T1

T-1T-2T-3

T-5 T-4

T-6T-7

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Bank Activate Command

The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the

clock. The bank addresses BA0 and BA1 are used to select the desired bank. The row addresses A0 through A13

are used to determine which row to activate in the selected bank for x4 and x8 organised components. For x16

components row addresses A0 through A12 have to be applied. The Bank Activate command must be applied

before any Read or Write operation can be executed. Immediately after the bank active command, the DDR2

SDRAM can accept a read or write command (with or without Auto-Precharge) on the following clock cycle. If a

R/W command is issued to a bank that has not satisfied the tRCDmin specification, then additive latency must be

programmed into the device to delay the R/W command which is internally issued to the device. The additive

latency value must be chosen to assure tRCDmin is satisfied. Additive latencies of 0, 1, 2, 3 and 4 are supported.

Once a bank has been activated it must be precharged before another Bank Activate command can be applied to

the same bank. The bank active and precharge times are defined as tRAS and tRP, respectively. The minimum

time interval between successive Bank Activate commands to the same bank is determined (tRC). The minimum

time interval between Bank Active commands, to any other bank, is the Bank A to Bank B delay time (tRRD).

Bank Activate Command Cycle: tRCD = 3, AL = 2, tRP = 3, tRRD = 2

Address

Command

T0 T2T1 T3 T4

Col. Addr.

Bank A

Row Addr.

Bank B

Col. Addr.

Bank B

Internal RAS-CAS delay tRCDmin.

Bank A to Bank B delay tRRD.

Activate

Bank B

Read A

Posted CAS

Activate

Bank A

Read B

Posted CAS

Read A

Begins

Row Addr.

Bank A

Addr.

Bank A

Precharge

Bank A

Addr.

Bank B

Precharge

Bank B

Row Addr.

Bank A

Activate

Bank A

tRP Row Precharge Time (Bank A)

tRC Row Cycle Time (Bank A)

Tn Tn+1 Tn+2 Tn+3

ACT

RAS-RAS delay tRRD.

tRAS Row Active Time (Bank A)

additive latency AL=2

CK, CK

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Read and Write Commands and Access Modes

After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS high,

CS and CAS low at the clock’s rising edge. WE must also be defined at this time to determine whether the access

cycle is a read operation (WE high) or a write operation (WE low). The DDR2 SDRAM provides a wide variety of

fast access modes. A single Read or Write Command will initiate a serial read or write operation on successive

clock cycles at data rates of up to 667Mb/sec/pin for main memory. The boundary of the burst cycle is restricted to

specific segments of the page length.

For example, the 32Mbit x 4 I/O x 4 Bank chip has a page length of 1 kByte (defined by CA0-CA9 & CA11).

In case of a 4-bit burst operation (burst length = 4) the page length of 1 kByte is divided into 512 uniquely address-

able segments (4-bits x 4 I/O each). The 4-bit burst operation will occur entirely within one of the 512 segments

(defined by CA0-CA8) beginning with the column address supplied to the device during the Read or Write Com-

mand (CA0-CA9 & A11). The second, third and fourth access will also occur within this segment, however, the

burst order is a function of the starting address, and the burst sequence.

In case of a 8-bit burst operation (burst length = 8) the page length of 1 kByte is divided into 256 uniquely address-

able double segments (8-bits x 4 I/O each). The 8-bit burst operation will occur entirely within one of the 256 double

segments (defined by CA0-CA7) beginning with the column address supplied to the deivce during the Read or

Write Command ( CA0-CA9 & CA11).

A new burst access must not interrupt the previous 4 bit burst operation in case of BL = 4 setting. Therefore the

minimum CAS to CAS delay (tCCD) is a minimum of 2 clocks for read or write cycles.

For 8 bit burst operation (BL = 8 ) the minimum CAS to CAS delay (tCCD) is 4 clocks for read or write cycles.

Burst interruption is allowed with 8 bit burst operation. For details see the “Burst Interrupt” - Section of this

datasheet.

Example:

Read Burst Timing Example : (CL = 3, AL = 0, RL = 3, BL = 4)

NOP NOP NOP NOP NOP

READ A

T0 T2T1 T3 T4 T5 T6 T7 T12

CMD

DQS,

DQS

READ B NOP

Dout A0 Dout A1 Dout A2 Dout A3 Dout B0 Dout B1 Dout B2 Dout B3 Dout C0 Dout C1 Dout C2 Dout C3

READ C

tCCD tCCD

CK, CK

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Posted CAS

Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2

SDRAM. In this operation, the DDR2 SDRAM allows a Read or Write command to be issued immediately after the

RAS bank activate command (or any time during the RAS to CAS delay time, tRCD, period). The command is held

for the time of the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is the sum of

AL and the CAS latency (CL). Therefore if a user chooses to issue a Read/Write command before the tRCDmin,

then AL greater than 0 must be written into the EMRS(1). The Write Latency (WL) is always defined as RL - 1

(Read Latency -1) where Read Latency is defined as the sum of Additive Latency plus CAS latency (RL=AL+CL). If

a user chooses to issue a Read command after the tRCDmin period, the Read Latency is also defined as RL = AL

+ CL.

Examples:

Read followed by a write to the same bank, Activate to Read delay < tRCDmin:

AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 4

Read followed by a write to the same bank, Activate to Read delay < tRCDmin:

AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 8

Dout0 Dout1 Dout2Dout3

CMD

0234 5 6 7 89101112-1 1

tRCD

AL = 2

" tRAC"

RL = AL + CL = 5

CL = 3

WL = RL -1 = 4

Din0 Din1 Din2 Din3

PostCAS1

DQS,

DQS

Activate Read Write

Bank A Bank A Bank A

CK, CK

CMD

0234 5 6 7 89101112

tRCD

AL = 2

" tRAC"

RL = AL + CL = 5

CL = 3

WL = RL -1 = 4

PostCAS3

DQS,

DQS

Activate Read

Bank A Bank A

Din0 Din1 Din2 Din3

Write

Bank A

Dout0 Dout1 Dout2 Dout 3 Dout0 Dout1 Dout2 Dout3

CK, CK

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Read followed by a write to the same bank, Activate to Read delay = tRCDmin:

AL = 0, CL = 3, RL = (AL + CL) = 3, WL = (RL -1) = 2, BL = 4

Read followed by a write to the same bank, Activate to Read delay > tRCDmin:

AL = 1, CL = 3, RL = 4, WL = 3, BL = 4

Activate

Bank A

0234 56 7 89101112-1 1

CMD

tRCD>tRCDmin.

"tRAC"

RL = 4

WL = 3

PostCAS5

DQS,

DQS

Read

Bank A

Din0 Din1 Din2 Din3

Dout 0 Dout1 Dout2 Dout 3

Write

Bank A

CK, CK

Activate

Bank A

0234 56 7 89101112-1 1

CMD

tRCD>tRCDmin.

"tRAC"

RL = 4

WL = 3

PostCAS5

DQS,

DQS

Read

Bank A

Din0 Din1 Din2 Din3

Dout 0 Dout1 Dout2 Dout 3

Write

Bank A

CK, CK

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Burst Mode Operation

Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory

locations (read cycle). The parameters that define how the burst mode will operate are burst sequence and burst

length. The DDR2 SDRAM supports 4 bit and 8 bit burst modes only. For 8 bit burst mode, full interleave address

ordering is supported, however, sequential address ordering is nibble based for ease of implementation. The burst

length is programmable and defined by the addresses A0 ~ A2 of the MRS. The burst type, either sequential or

interleaved, is programmable and defined by the address bit 3 (A3) of the MRS. Seamless burst read or write oper-

ations are supported. Interruption of a burst read or write operation is prohibited, when burst length = 4 is pro-

grammed. For burst interruption of a read or write burst when burst length = 8 is used, see the “Burst Interruption “

section of this datasheet. A Burst Stop command is not supported on DDR2 SDRAM devices.

Burst Length and Sequence

Burst Length Starting Address

(A2 A1 A0) Sequential Addressing (decimal) Interleave Addressing (decimal)

x 0 0 0, 1, 2, 3 0, 1, 2, 3

x 0 1 1, 2, 3, 0 1, 0, 3, 2

x 1 0 2, 3, 0, 1 2, 3, 0, 1

x 1 1 3, 0, 1, 2 3, 2, 1, 0

0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7

0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6

0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5

0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4

1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3

1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2

1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1

1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0

Note: 1) Page length is a function of I/O organization

128Mb X 4 organization (CA0-CA9, CA11); Page Length = 1 kByte

64Mb X 8 organization (CA0-CA9 ); Page Length = 1 kByte

32Mb X 16 organization (CA0-CA9); Page Length = 2 kByte

2) Order of burst access for sequential addressing is “nibble-based” and therefore different from SDR

or DDR components

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Burst Read Command

The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the

clock. The address inputs determine the starting column address for the burst. The delay from the start of the command until

the data from the first cell appears on the outputs is equal to the value of the read latency (RL). The data strobe output (DQS)

is driven low one clock cycle before valid data (DQ) is driven onto the data bus. The first bit of the burst is synchronized with

the rising edge of the data strobe (DQS). Each subsequent data-out appears on the DQ pin in phase with the DQS signal in a

source synchronous manner. The RL is equal to an additive latency (AL) plus CAS latency (CL). The CL is defined by the

Mode Register Set (MRS). The AL is defined by the Extended Mode Register Set (EMRS(1))

Basic Burst Read Timing

Examples:

Burst Read Operation: RL = 3 (AL = 0, CL = 3, BL = 8)

Burst Read Operation: RL = 5 (AL = 2, CL = 3, BL = 4)

DQS,

DQS

RPRE

DQSQmax

RPST

DQSCK

Dout Dout Dout Dout

CLK, CLK

CLK

DO-Read

DQSQmax

NOP NOP NOP NOP NOP NOP

NOP

READ A

T0 T2T1 T3 T4 T5 T6 T7 T8

Dout A0 Dout A1 Dout A2 Dout A3

RL = 5

AL = 2 CL = 3

NOP

<= tDQSCK

CMD

BRead523

DQS,

DQS

Post CAS

CK, CK

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Burst Read followed by Burst Write : RL = 5, WL = (RL-1) = 4, BL = 4

The minimum time from the burst read command to the burst write command is defined by a read-to-write turn-

around time, which is BL/2 + 2 clocks.

Seamless Burst Read Operation : RL = 5, AL = 2, CL = 3, BL = 4

CMD

NOP NOP NOP NOP NOP NOP

DQ's

NOP

READ A

T0 T2T1 T3 T4 T5 T6 T7 T8

Dout A0 Dout A1 Dout A2 Dout A3

RL = 3

CL = 3

NOP

<= tDQSCK

BRead303

DQS,

DQS

Dout A4 Dout A5 Dout A6 Dout A7

CK, CK

NOP Posted CAS

WRITE A NOP NOP NOP NOP

NOP

READ A

Posted CAS

T0 T1

Dout A0 Dout A1 Dout A2 Dout A3

RL = 5

NOP

CMD

BRBW514

T3 T4 T5 T6 T7 T8 T9

Din A0 Din A1 Din A2 Din A3

DQS,

DQS

WL = RL - 1 = 4

BL/2 + 2

CK, CK

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The seamless burst read operation is supported by enabling a read command at every BL / 2 number of clocks.

This operation is allowed regardless of same or different banks as long as the banks are activated.

Seamless Burst Read Operation : RL = 3, AL = 0, CL = 3, BL = 8 (non interrupting)

The seamless, non interrupting 8-bit burst read operation is supported by enabling a read command at every BL / 2

number of clocks. This operation is allowed regardless of same or different banks as long as the banks are acti-

vated.

NOP NOP NOP NOP NOP NOP

NOP

READ A

Post CAS

READ B

Post CAS

T0 T2T1 T3 T4 T5 T6 T7 T8

Dout A0 Dout A1 Dout A2 Dout A3 Dout B0 Dout B1 Dout B2 Dout B3

RL = 5

AL = 2 CL = 3

SBR523

CMD

DQS,

DQS

CK, CK

NOP NOP

NOP

READ A

Post CAS

T0 T2T1 T3 T4 T5 T6 T7 T8

Dout A0 Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A4 Dout A7

RL = 3

CL = 3

SBR_BL8

CMD

DQS,

DQS

READ B

Post CAS

Dout B0 Dout B1 Dout B2 Dout B3 Do

NOP NOP NOP NOP N

CK, CK

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Burst Write Command

The Burst Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising edge of

the clock. The address inputs determine the starting column address. Write latency (WL) is defined by a read

latency (RL) minus one and is equal to (AL + CL -1). A data strobe signal (DQS) has to be driven low (preamble) a

time tWPRE prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising

edge of the DQS following the preamble. The tDQSS specification must be satisfied for write cycles. The subse-

quent burst bit data are issued on successive edges of the DQS until the burst length is completed. When the burst

has finished, any additional data supplied to the DQ pins will be ignored. The DQ signal is ignored after the burst

write operation is complete. The time from the completion of the burst write to bank precharge is named “write

recovery time” (tWR) and is the time needed to store the write data into the memory array. tWR is an analog timing

parameter (see the AC table in this specification) and is not the programmed value for WR in the MRS.

Basic Burst Write Timing

Example:.

Burst Write Operation : RL = 5 (AL = 2, CL = 3), WL = 4, BL = 4

DQS,

DQS DQS

DQS

DQSH

DQSL

WPRE WPST

Din Din Din Din

NOP NOP NOP NOP NOP Precharge

NOP

WRITE A

Post CAS

T0 T2T1 T3 T4 T5 T6 T7 T9

WL = RL-1 = 4

CMD

NOP

DIN A0 DIN A1 DIN A2 DIN A3

<= tDQSS

tWR

Completion of

the Burst Write

DQS,

DQS

CK, CK

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Burst Write Operation : RL = 3 (AL = 0, CL = 3), WL = 2, BL = 4

Burst Write followed by Burst Read : RL = 5 (AL = 2, CL = 3), WL = 4, tWTR = 2, BL = 4

The minimum number of clocks from the burst write command to the burst read command is (CL - 1) +BL/2 +

tWTR where tWTR is the write-to-read turn-around time tWTR expressed in clock cycles. The tWTR is not a write

recovery time (tWR) but the time required to transfer 4 bit write data from the input buffer into sense amplifiers in

the array.

NOP NOP NOP NOP

NOP

WRITE A

Post CAS

T0 T2T1 T3 T4 T5 T6 T7 T9

WL = RL-1 = 2

BW322

CMD

NOP

DIN A0 DIN A1 DIN A2 DIN A3

tWR

Completion of

the Burst Write

<= tDQSS

Precharge Bank A

Activate

tRP

DQS,

DQS

CK, CK

NOP NOP NOP NOP

NOP READ A

Post CAS

BWBR

CMD

NOP

DIN A0 DIN A1 DIN A2 DIN A3

AL=2 CL=3

NOP NOP

tWTR

T0 T2T1 T3 T4 T5 T6 T7 T8 T9

Write to Read = (CL - 1)+ BL/2 +tWTR(2) = 6

DQS,

DQS

WL = RL - 1 = 4

RL=5

CK, CK

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Seamless Burst Write Operation : RL = 5, WL = 4, BL = 4

The seamless burst write operation is supported by enabling a write command every BL / 2 number of clocks. This

operation is allowed regardless of same or different banks as long as the banks are activated.

Seamless

Burst Write Operation : RL = 3, WL = 2, BL = 8, non interrupting

The seamless, non interrupting 8-bit burst write operation is supported by enabling a write command at every BL /

2 number of clocks. This operation is allowed regardless of same or different banks as long as the banks are acti-

vated.

NOP NOP NOP NOP NOP NOP

NOP

DIN A0 DIN A1 DIN A2 DIN A3

WRITE A

Post CAS

WL = RL - 1 = 4

WRITE B

Post CAS

DIN B0 DIN B1 DIN B2 DIN B3

T0 T2T1 T3 T4 T5 T6 T7 T8

CMD

SBR

DQS,

DQS

CK, CK

WRITE

WL = RL - 1 =

T0 T2T1 T3 T4 T5 T6 T7 T8

SBW_BL8

DQS,

DQS

WRITE

DIN A0 DIN A1 DIN A2 DIN A3 DIN A4 DIN A5 DIN A5 DIN A7 DIN B0 DIN B1 DIN B2 DIN B3 DIN B4 DIN B5

CK, CK

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Write Data Mask

One write data mask input (DM) for x4 and x8 components and two write data mask inputs (LDM, UDM) for x16

components are supported on DDR2 SDRAMs, consistent with the implementation on DDR SDRAMs. It has iden-

tical timings on write operations as the data bits, and though used in a uni-directional manner, is internally loaded

identically to data bits to insure matched system timing. Data mask is not used during read cycles. If DM is high

during a write burst coincident with the write data, the write data bit is not written to the memory. For x8 compo-

nents the DM function is disabled, when RDQS / RDQS are enabled by EMRS(1).

Write Data

Mask Timing

Burst Write Operation with Data Mask : RL = 3 (AL = 0, CL = 3), WL = 2, tWR = 3 , BL = 4

DQS,

DQS DQS

DQS

DQSH

DQSL

WPRE WPST

DQ Din Din Din Din

DS DH

don't care

NOP NOP NOP NOP

NOP

WRITE A

T0 T2T1 T3 T4 T5 T6 T7 T9

WL = RL-1 = 2

CMD

NOP

tWR

<= tDQSS

Precharge Bank A

Activate

tRP

DQS,

DQS

DIN A0 DIN A1 DIN A3

DIN A2

CK, CK

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Burst Interruption

Interruption of a read or write burst is prohibited for burst length of 4 and only allowed for burst length of 8 under the follow-

ing conditions:

1. A Read Burst of 8 can only be interrupted by another Read command. Read burst interruption by a Write or Precharge Command is pro-

hibited.

2. A Write Burst of 8 can only be interrupted by another Write command. Write burst interruption by a Read or Precharge Command is

prohibited.

3. Read burst interrupt must occur exactly two clocks after the previous Read command. Any other Read burst interrupt timings are prohib-

ited.

4. Write burst interrupt must occur exactly two clocks after the previous Write command. Any other Read burst interrupt timings are prohib-

ited.

5. Read or Write burst interruption is allowed to any bank inside the DDR2 SDRAM.

6. Read or Write burst with Auto-Precharge enabled is not allowed to be interrupted.

7. Read burst interruption is allowed by a Read with Auto-Precharge command.

8. Write burst interruption is allowed by a Write with Auto-Precharge command.

9. All command timings are referenced to burst length set in the mode register. They are not referenced to the actual burst. For example,

Minimum Read to Precharge timing is AL + BL/2 where BL is the burst length set in the mode register and not the actual burst (which is

shorter because of interrupt). Minimum Write to Precharge timing is WL + BL/ 2 + tWR, where tWR starts with the rising clock after the

un-interrupted burst end and not form the end of the actual burst end.

Examples:

Read Burst Interrupt Timing Example : (CL = 3, AL = 0, RL = 3, BL = 8)

NOP NOP NOP NOP NOP

NOP

READ A

T0 T2T1 T3 T4 T5 T6 T7 T8

CMD

RBI

DQS,

DQS

READ B NOP

Dout A0 Dout A1 Dout A2 Dout A3 Dout B0 Dout B1 Dout B2 Dout B3 Dout B4 Dout B5 Dout B6

CK, CK

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Write Burst Interrupt Timing Example : ( CL = 3, AL = 0, WL = 2, BL = 8)

NOP NOP NOP NOP

NOP

WRITE A

T0 T2T1 T3 T4 T5 T6 T7 T8

CMD

WBI

DQS,

DQS

NOP

Din A0 Din A1 Din A2 Din A3 Din B0 Din B1 Din B2 Din B3 Dout B4 Din B5 Din B6 Din B7

WRITE B

CK, CK

NOP

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Precharge Command

The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Com-

mand is triggered when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The Pre-charge

Command can be used to precharge each bank independently or all banks simultaneously. Three address bits

A10, BA0 and BA1 are used to define which bank to precharge when the command is issued

Bank Selection for Precharge by Address Bit

Burst Read Operation Followed by a Precharge

The following rules apply as long as the tRTP timing parameter - Internal Read to Precharge Command delay time

- is less or equal two clocks, which is the case for operating frequencies less or equal 266 Mhz (DDR2 400 and 533

speed sorts):

Minimum Read to Precharge command spacing to the same bank = AL + BL/2 clocks. For the earliest possible

precharge, the Precharge command may be issued on the rising edge which is “Additive Latency (AL) + BL/2

clocks” after a Read Command, as long as the minimum tRAS timing is satisfied.

A new bank active command may be issued to the same bank if the following two conditions are satisfied simulta-

neously:

(1) The RAS precharge time (tRP) has been satisfied from the clock at which the precharge begins.

(2) The RAS cycle time (tRCmin) from the previous bank activation has been satisfied.

For operating frequencies higher than 266 MHz, tRTP becomes > 2 clocks and one additional clock cycle has to

be added for the minimum Read to Precharge command spacing, which now becomes AL + BL/2 + 1 clocks.

A10 BA0 BA1 Precharge

Bank(s)

LOW LOW LOW Bank 0 only

LOW LOW HIGH Bank 1 only

LOW HIGH LOW Bank 2 only

LOW HIGH HIGH Bank 3 only

HIGH Don’t Care Don’t Care all banks

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Examples:

Burst Read Operation Followed by Precharge: RL = 4 (AL = 1, CL = 3), BL = 4, tRTP <= 2 clocks

Burst Read Operation Followed by Precharge: RL = 4 (AL = 1, CL = 3), BL = 8, tRTP <= 2 clocks

NOP Precharge NOP Bank A

Activate NOP

NOP

READ A

Post CAS

T0 T2T1 T3 T4 T5 T6 T7 T8

CMD

NOP

AL + BL/2 clks

Dout A0 Dout A1 Dout A2 Dout A3

AL = 1 CL = 3

RL = 4

>=tRAS CL = 3

tRP

DQS,

DQS

NOP

>=tRC

>=tRTP

CK, CK

NOP NOP NOP

READ A

Post CAS

T0 T2T1 T3 T4 T5 T6 T7 T8

CMD

BR-P413(8)

NOP

AL + BL/2 clks

Dout A0 Dout A1 Dout A2 Dout A3

AL = 1 CL = 3

RL = 4

>=tRAS CL = 3

tRP

DQS,

DQS

NOP

>=tRC

>=tRTP

Dout A4 Dout A5 Dout A6 Dout A7

Precharge NOP Bank A

Activate

first 4-bit prefetch second 4-bit prefetch

CK, CK

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Burst Read Operation Followed by Precharge: RL = 5 (AL = 2, CL = 3), BL = 4, tRTP <= 2 clocks

Burst Read Operation Followed by Precharge: RL = 6, (AL = 2, CL = 4), BL = 4, tRTP <= 2 clocks

NOP NOP NOP Bank A

Activate NOP

NOP

READ A

Post CAS

T0 T2T1 T3 T4 T5 T6 T7 T8

CMD

BR-P523

NOP

AL + BL/2 clks

Dout A0 Dout A1 Dout A2 Dout A3

AL = 2 CL = 3

RL = 5

>=tRAS CL = 3

tRP

Precharge

DQS,

DQS

>=tRC

>=tRTP

CK, CK

NOP NOP

NOP

READ A

Post CAS

T0 T2T1 T3 T4 T5 T6 T7 T8

CMD

BR-P624

NOP

AL + BL/2 clocks

Dout A0 Dout A1 Dout A2 Dout A3

AL = 2

CL = 4

RL = 6

>=tRAS CL = 4

tRP

Precharge

Bank A

Activate

DQS,

DQS

NOP NOP

>=tRC

>=tRTP

CK, CK

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Burst Read Operation Followed by Precharge: RL = 4, (AL = 0, CL = 4), BL = 8, tRTP > 2 clocks

NOP NOP NOP

READ A

T0 T2T1 T3 T4 T5 T6 T7 T8

CMD

BR-P404(8)

NOP

AL + BL/2 clks + 1

Dout A0 Dout A1 Dout A2 Dout A3

CL = 4

RL = 4

>=tRAS

tRP

DQS,

DQS

NOP

>=tRTP

Dout A4 Dout A5 Dout A6 Dout A7

Precharge NOP Bank A

Activate

first 4-bit prefetch second 4-bit prefetch

CK, CK

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Burst Write followed by Precharge

Minimum Write to Precharge command spacing to the same bank = WL + BL/2 + tWR. For write cycles, a delay must be sat-

isfied from the completion of the last burst write cycle until the Precharge command can be issued. This delay is known as a

write recovery time (t WR ) referenced from the completion of the burst write to the Precharge command. No Precharge com-

mand should be issued prior to the tWR delay, as DDR2 SDRAM does not support any burst interrupt by a Precharge com-

mand. tWR is an analog timing parameter (see the AC table in this datasheet) and is not the programmed value for tWR in the

MRS.

Examples:

Burst Write

followed by Precharge : WL = (RL - 1) = 3, BL = 4, tWR = 3

Burst Write followed by Precharge : WL = (RL - 1) = 4, BL = 4, tWR = 3

NOP NOP NOP NOP

NOP

WRITE A

Post CAS

T0 T2T1 T3 T4 T5 T6 T7 T8

WL = 3

BW-P3

CMD

NOP

DIN A0 DIN A1 DIN A2 DIN A3

tWR

Completion of

the Burst Write

Precharge

NOP

DQS,

DQS

CK, CK

NOP NOP NOP NOP

NOP

WRITE A

Post CAS

T0 T2T1 T3 T4 T5 T6 T7 T9

WL = 4

BW-P4

CMD

NOP

DIN A0 DIN A1 DIN A2 DIN A3

tWR

Completion of

the Burst Write

Precharge

NOP

DQS,

DQS

CK, CK

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Auto-Precharge Operation

Before a new row in an active bank can be opened, the active bank must be precharged using either the Pre-

charge Command or the Auto-Precharge function. When a Read or a Write Command is given to the DDR2

SDRAM, the CAS timing accepts one extra address, column address A10, to allow the active bank to auto-mati-

cally begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is low when the

Read or Write Command is issued, then normal Read or Write burst operation is executed and the bank remains

active at the completion of the burst sequence. If A10 is high when the Read or Write Com-mand is issued, then

the Auto-Precharge function is enabled. During Auto-Precharge, a Read Command will execute as normal with the

exception that the active bank will begin to precharge internally on the rising edge which is CAS Latency (CL) clock

cycles before the end of the read burst. Auto-Precharge is also implemented for Write Commands.The precharge

operation engaged by the Auto-Precharge command will not begin until the last data of the write burst sequence is

properly stored in the memory array. This feature allows the precharge operation to be partially or completely hid-

den during burst read cycles (dependent upon CAS Latency) thus improving system performance for random data

access. The RAS lockout circuit internally delays thepprecharge operation until the array restore operation has

been completed so that the Auto-Precharge command may be issued with any read or write command.

Burst Read with Auto-Precharge

If A10 is high when a Read Command is issued, the Read with Auto-Precharge function is engaged. The DDR2

SDRAM starts an Auto-Precharge operation on the rising edge which is (AL + BL/2) cycles later from the Read

with AP command if tRAS(min) and tRTP are satisfied. If tRAS(min) is not satisfied at the edge, the start point of

Auto-Precharge operation will be delayed until tRAS(min) is satisfied. If tRTP(min) is not satisfied at the edge, the

start point of Auto-Precharge operation will be delayed until tRTP(min) is satisfied.

In case the internal precharge is pushed out by tRTP, tRP starts at the point where the internal precharge happens

(not at the next rising clock edge after this event). So for BL = 4 the minimum time from Read with Auto-Precharge

to the next Activate command becomes AL + tRTP + tRP. For BL = 8 the time from Read with Auto-Precharge to

the next Activate command is AL + 2 + tRTP + tRP. Note that both parameters tRTP and tRP have to be rounded

up to the next integer value. In any event internal precharge does not start earlier than two clocks after the last 4-bit

prefetch.

A new bank active (command) may be issued to the same bank if the following two conditions are satisfied simulta-

neously:

(1) The RAS precharge time (tRP) has been satisfied from the clock at which the Auto-Precharge begins.

(2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.

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Examples:

Burst Read with Auto-Precharge followed by an activation to the Same Bank (tRC Limit)

RL = 5 (AL = 2, CL = 3), BL = 4, tRTP <= 2 clocks

Burst Read with Auto-Precharge followed by an Activation to the Same Bank (tRAS Limit):

RL = 5 ( AL = 2, CL = 3), BL = 4, tRTP <= 2 clocks

NOP NOP NOP NOP Bank

Activate

NOP

READ w/AP

Posted CAS

T0 T2T1 T3 T4 T5 T6 T7 T8

Dout A0 Dout A1 Dout A2 Dout A3

RL = 5

AL = 2 CL = 3

NOP

CMD

BR-AP5231

A10 ="high"

tRP

Auto-Precharge Begins

DQS,

DQS

tRAS

tRCmin.

NOP

AL + BL/2

CK, CK

NOP NOP NOP NOP Bank

Activate

NOP

READ w/AP

Posted CAS

T0 T2T1 T3 T4 T5 T6 T7 T8

Dout A0 Dout A1 Dout A2 Dout A3

RL = 5

AL = 2 CL = 3

NOP

CMD

BR-AP5232

A10 ="high"

tRP

Auto-Precharge Begins

DQS,

DQS

tRC

tRAS(min)

NOP

CK, CK

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Burst Read with Auto-Precharge followed by an Activation to the Same Bank:

RL = 4 ( AL = 1, CL = 3), BL = 8, tRTP <= 2 clocks

Burst Read with Auto-Precharge followed by an Activation to the Same Bank:

RL = 4 ( AL = 1, CL = 3), BL = 4, tRTP > 2 clocks

NOP NOP NOP NOP Bank

Activate

NOP

READ w/AP

Posted CAS

T0 T2T1 T3 T4 T5 T6 T7 T8

Dout A0 Dout A1 Dout A2 Dout A3

RL = 4

AL = 1 CL = 3

NOP

CMD

BR-AP413(8)2

A10 ="high" tRP

Auto-Precharge Begins

DQS,

DQS

NOP

Dout A4 Dout A5 Dout A6 Dout A7

first 4-bit prefetch second 4-bit prefetch

>= tRTP

AL + BL/2

CK, CK

NOP NOP NOP NOP Bank

Activate

NOP

READ w/AP

Posted CAS

T0 T2T1 T3 T4 T5 T6 T7 T8

Dout A0 Dout A1 Dout A2 Dout A3

RL = 4

AL = 1 CL = 3

NOP

CMD

BR-AP4133

A10 ="high"

Auto-Precharge Begins

DQS,

DQS

NOP

first 4-bit prefetch

tRTP

AL + tRTP + tRP

tRP

CK, CK

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Burst Write with Auto-Precharge

If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is engaged. The DDR2

SDRAM automatically begins precharge operation after the completion of the write burst plus the write recovery

time delay (WR), programmed in the MRS register, as long as tRAS is satisfied. The bank undergoing Auto-Pre-

charge from the completion of the write burst may be reactivated if the following two conditions are satisfied.

(1) The last data-in to bank activate delay time (tDAL = WR + tRP) has been satisfied.

(2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.

In DDR2 SDRAMs the write recovery time delay (WR ) has to be programmed into the MRS mode register. As

long as the analog twr timing parameter is not violated, WR can be programmed between 2 and 6 clock cycles.

Minimum Write to Activate command spacing to the same bank = WL + BL/2 + tDAL.

Examples:

Burst Write with Auto-Precharge (tRC Limit) : WL = 2, tDAL = 6 (WR = 3, tRP = 3) , BL = 4

NOP NOP NOP NOP NOP Bank A

Activate

NOP

WRITE

w/AP

T0 T2T1 T3 T4 T5 T6 T7

NOP

CMD

BW-AP223

A10 ="high"

tRP

Auto-Precharge Begins

DIN A0 DIN A1 DIN A2 DIN A3

WL = RL-1 = 2 WR

tRCmin.

DQS,

DQS

Completion of the Burst Write

tDAL

>=tRASmin.

CK, CK

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Burst Write with Auto-Precharge (WR + tRP Limit) : WL = 4, tDAL = 6 (WR = 3, tRP = 3), BL = 4

Concurrent Auto-Precharge

DDR2 devices support the “Concurrent Auto-Precharge” feature. A Read with Auto-Precharge enabled, or a Write with Auto-

Precharge enabled, may be followed by any command to the other bank, as long as that command does not interrupt the read or

write data transfer, and all other related limitations (e.g. contention between Read data and Write data must be avoided exter-

nally and on the internal data bus.

The minimum delay from a Read or Write command with Auto-Precharge enabled, to a command to a different bank, is sum-

marized in the table below. As defined, the WL = RL - 1 for DDR2 devices which allows the command gap and corresponding

data gaps to be minimized.

From Command

To Command

(different bank,

non-interrupting command)

Minimum Delay with Con-

current Auto-Precharge

Support

Units Note

WRITE w/AP

Read or Read w/AP (CL -1) + (BL/2) + tWTR tCK

Write ot Write w/AP BL/2 tCK

Precharge or Activate 1 tCK 1)

Read w/AP

Read or Read w/AP BL/2 tCK

Write or Write w/AP BL/2 + 2 tCK

Precharge or Activate 1 tCK 1)

Note:

1) This rule only applies to a selective Precharge command to another banks, a Precharge-All command is

illegal

NOP NOP NOP NOP NOP Bank A

Activate

NOP

WRITE w/AP

Posted CAS

T0 T3 T4 T5 T6 T7 T12

NOP

CMD

BW-AP423

A10 ="high"

tRP

Auto-Precharge Begins

DIN A0 DIN A1 DIN A2 DIN A3

WL = RL-1 = 4 WR

>=tRC

Completion of the Burst Write

DQS,

DQS

tDAL

>=tRAS

CK, CK

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Refresh

SDRAMs require a refresh of all rows in any rolling 64 ms interval. Each refresh is generated in one of two ways :

by an explicit Auto-Refresh command, or by an internally timed event in Self-Refresh mode. Dividing the number of

device rows into the rolling 64 ms interval defined the average refresh interval tREFI, which is a guideline to con-

trolles for distributed refresh timing. For example, a 512Mbit DDR2 SDRAM has 8192 rows resulting in a tREFI of

7,8 µs.

Auto-Refresh Command

Auto-Refresh is used during normal operation of the DDR2 SDRAMs. This command is nonpersistent, so it must

be issued each time a refresh is required. The refresh addressing is generated by the internal refresh controller.

This makes the address bits ”Don’t Care” during an Auto-Refresh command. The DDR2 SDRAM requires Auto-

Refresh cycles at an average periodic interval of tREFI (maximum).

When CS, RAS and CAS are held low and WE high at the rising edge of the clock, the chip enters the Auto-

Refresh mode. All banks of the SDRAM must be precharged and idle for a minimum of the precharge time (tRP)

before the Auto-Refresh Command can be applied. An internal address counter supplies the addresses during the

refresh cycle. No control of the external address bus is required once this cycle has started.

When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay

between the Auto-Refresh Command and the next Activate Command or subsequent Auto-Refresh Command

must be greater than or equal to the Auto-Refresh cycle time (tRFC).

To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh

interval is provided. A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM,

meaning that the maximum absolute interval between any Auto-Refresh command and the next Auto-Refresh

command is 9 * tREFI.

T0 T2T1 T3

CK, CK

CMD

Precharge

> = t

NOP AUTO

REFRESH ANYNOP

> = t

RFC

> = t

RFC

AUTO

REFRESH

NOP NOP NOP

CKE

"high"

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Self-Refresh Command

The Self-Refresh command can be used to retain data, even if the rest of the system is powered down. When in

the Self-Refresh mode, the DDR2 SDRAM retains data without external clocking.

The DDR2 SDRAM device has a built-in timer to accommodate Self-Refresh operation. The Self-Refresh Com-

mand is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. ODT

must be turned off before issuing Self Refresh command, by either driving ODT pin low or using EMRS(1) com-

mand. Once the command is registered, CKE must be held low to keep the device in Self-Refresh mode. When the

DDR2 SDRAM has entered Self-Refresh mode all of the external control signals, except CKE, are disabled. The

clock is internally disabled during Self-Refresh Operation to save power. The user may change the external clock

frequency or halt the external clock one clock after Self-Refresh entry is registered, however, the clock must be

restarted and stable before the device can exit Self-Refresh operation. Once Self-Refresh Exit command is regis-

tered, a delay equal or longer than the tXSNR or tXSRD must be satisfied before a valid command can be issued

to the device. CKE must remain high for the entire Self-Refresh exit period (tXSNR or tXSRD) for proper operation.

NOP or DESELECT commands must be registered on each positive clock edge during the Self-Refresh exit inter-

val. Since the ODT function is not supported during Self-Refresh operation, ODT has to be turned off tAOFD before

entering Self-Refresh Mode and can be turned on again when the tXSRD timing is satisfied.

Power-Down

* = Device must be in the “All banks idle” state to entering Self Refresh mode.

ODT must be turned off prior to entering Self Refresh mode.

tXSRD (>=200 tCK) has to be satisfied for a Read or a Read with Auto-Precharge command.

tXSNR has to be satisfied for any command except a Read or a Read with Auto-Precharge command,

CK/CK

T1 T3T2

CK/CK may

be halted

CK/CK must

be stable

CKE >=tXSRD

>= tXSNR

Tn Tr

TmT5

tRP*

tis

tAOFD

CMD

Self Refresh

Entry NOP Non-Read

Command

Read

Command

tis

ODT

where tXSNR is defined as tRFC + 10ns.

The miminum CKE low time is defined by the tCKEmin. timing parameter.

Since CKE is an SSTL input, VREF must be maintained during Self Refresh.

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Power-down is synchronously entered when CKE is registered low, along with NOP or Deselect command. CKE is

not allowed to go low while mode register or extended mode register command time, or read or write operation is in

progress. CKE is allowed to go low while any other operation such as row activation, Precharge, Auto-Precharge

or Auto-Refresh is in progress, but power-down IDD specification will not be applied until finishing those opera-

tions.

The DLL should be in a locked state when power-down is entered. Otherwise DLL should be reset after exiting

power-down mode for proper read operation.

If power-down occurs when all banks are precharged, this mode is referred to as Precharge Power-down; if power-

down occurs when there is a row active in any bank, this mode is referred to as Active Power-down. For Active

Power-down two different power saving modes can be selected within the MRS register, address bit A12. When

A12 is set to “low” this mode is referred as “standard active power-down mode” and a fast power-down exit timing

defined by the tXARD timing parameter can be used. When A12 is set to “high” this mode is referred as a power

saving “low power active power-down mode”. This mode takes longer to exit from the power-down mode and the

tXARDS timing parameter has to be satisfied.

Entering power-down deactivates the input and output buffers, excluding CK, CK, ODT and CKE. Also the DLL is

disabled upon entering Precharge Power-down or slow exit active power-down, but the DLL is kept enabled during

fast exit active power-down. In power-down mode, CKE low and a stable clock signal must be maintained at the

inputs of the DDR2 SDRAM, and all other input signals are “Don’t Care”. Power-down duration is limited by 9 times

tREFI of the device.

The power-down state is synchronously exited when CKE is registered high (along with a NOP or Deselect com-

mand). A valid, executable command can be applied with power-down exit latency, tXP, tXARD or tXARDS, after

CKE goes high. Power-down exit latencies are defined in the AC spec table of this data sheet.

Power-Down Entry

Active Power-down mode can be entered after an activate command. Precharge Power-down mode can be

entered after a precharge, Precharge-All or internal precharge command. It is also allowed to enter power-mode

after an Auto-Refresh command or MRS / EMRS(1) command when tMRD is satisfied.

Active Power-down mode entry is prohibited as long as a Read Burst is in progress, meaning CKE should be kept

high until the burst operation is finished. Therefore Active Power-Down mode entry after a Read or Read with Auto-

Precharge command is allowed after RL + BL/2 is satisfied.

Active Power-down mode entry is prohibited as long as a Write Burst and the internal write recovery is in progress.

In case of a write command, active power-down mode entry is allowed when WL + BL/2 + tWTR is satisfied.

In case of a write command with Auto-Precharge, Power-down mode entry is allowed after the internal precharge

command has been executed, which is WL + BL/2 + WR starting from the write with Auto-Precharge command. In

case the DDR2 SDRAM enters the Precharge Power-down mode.

Examples:

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Active Power-Down Mode Entry and Exit after an Activate Command

Active Power-Down Mode Entry and Exit after a Read Burst: RL = 4 (AL = 1, CL =3), BL = 4

Active Power-Down Mode Entry and Exit after a Write Burst: WL = 2, tWTR = 2, BL = 4

note: Active Power-Down mode exit timing tXARD (“fast exit”) or tXARDS (“slow exit”) depends on the programmed

state in the MRS, address bit A12.

NOP NOP

Activate

T0 T2T1

CMD

NOP

Tn Tn+1

CKE

Active

Power-Down

Entry

NOP NOP

Act.PD 0

tIS

Tn+2

tIS

Active

Power-Down

Exit

Valid

Command

tXARD or

tXARDS *)

CK, CK

note: Active Power-Down mode exit timing tXARD (“fast exit”) or tXARDS (“slow exit”) depends on the programmed

state in the MRS, address bit A12.

NOP NOP

READ

T0 T2T1 T3 T4 T5 T6 T7 T8

Dout A0 Dout A1 Dout A2 Dout A3

RL = 4

CL = 3

CMD

DQS,

DQS

NOP NOP NOP NOP NOP NOP

Tn Tn+1

CKE

AL = 1

Active

Power-Down

Entry

RL + BL/2

NOP NOP

Act.PD 1

tIS

Tn+2

tIS

Active

Power-Down

Exit

Valid

Command

tXARD or

tXARDS *)

CK, CK

READ w/AP

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Precharge Power Down Mode Entry and Exit

note: Active Power-Down mode exit timing tXARD (“fast exit”) or tXARDS (“slow exit”) depends on the programmed

state in the MRS, address bit A12.

WRIT

T0 T2T1 T3 T4 T5 T6 T7

DQS,

DQS

Tn Tn+1

CKE

WL = RL - 1 = 2

Active

Power-Down

Entry

WL + BL/2 + tWTR

Act.PD 2

tWTR

tIS

Tn+2

tIS

Valid

Command

Active

Power-Down

Exit

tXARD or

tXARDS *)

CK, CK

DIN A0 DIN A1 DIN A2 DIN A3

tXP

NOP NOP

Precharge

T0 T2T1

CMD

NOP NOP

Tn Tn+1

CKE

Precharge

Power-Down

Entry

NOP NOP

PrePD

tIS

Tn+2

tIS

Precharge

Power-Down

Exit

Valid

Command

tRP

NOP

*) "Precharge" may be an external command or an internal

precharge following Write with AP.

CK, CK

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No Operation Command

The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state. The purpose of

the No Operation Command is to prevent the SDRAM from registering any unwanted commands between opera-

tions. A No Operation Command is registered when CS is low with RAS, CAS, and WE held high at the rising edge

of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a

burst read or write cycle.

Deselect Command

The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs

when CS is brought high, the RAS, CAS, and WE signals become don’t care.

Input Clock Frequency Change

During operation the DRAM input clock frequency can be changed under the following conditions:

a) During Self-Refresh operation

b) DRAM is in Precharge Power-down mode and ODT is completely turned off.

The DDR2-SDRAM has to be in Precharged Power-down mode and idle. ODT must be allready turned off and CKE must be

at a logic “low” state. After a minimum of two clock cycles after tRP and tAOFD have been satisfied the input clock frequency

can be changed. A stable new clock frequency has to be provided, before CKE can be changed to a “high” logic level again.

After tXP has been satisfied a DLL RESET command via EMRS(1) has to be issued. During the following DLL re-lock period

of 200 clock cycles, ODT must remain off. After the DLL-re-lock period the DRAM is ready to operate with the new clock

frequency.

Example:

Input frequency change during Precharge Power-Down mode

NOP NOP

T0 T2T1 T3 T4 Tx Tx+1 Ty

NOP NOP NOP NOP NOP DLL

RESET

Ty+2 Ty+3

Frequency Change

occurs here

NOP NOP

Frequ.Ch.

tXP

Stable new clock

before power-down exit

tRP

tAOFD

Minimum 2 clocks

required before

changing the frequency

Ty+1

NOP Valid

Command

200 clocks

ODT is off during

DLL RESET

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Asynchronous CKE Low Event

DRAM requires CKE to be maintained “high” for all valid operations as defined in this data sheet. If CKE asynchronously

drops “low” during any valid operation DRAM is not guaranteed to preserve the contents of the memory array. If this event

occurs, the memory controller must satisfy a time delay ( tdelay ) before turning off the clocks. Stable clocks must exist at the

input of DRAM before CKE is raised “high” again. The DRAM must be fully re-initialized as described the the initialization

sequence (section 2.2.1, step 4 thru 13). DRAM is ready for normal operation after the initialization sequence. See AC timing

parametric table for tdelay specification.

Asynchronous CKE Low Event

CKE

CKE drops low due to an

asynchronous reset event

Clocks can be turned off after

this point

tdelay

CK, CK

stable clocks

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Truth Table

Command Truth Table

Function

CKE

CS RAS CAS WE BA0

BA1 A13-A11 A10 A9 - A0 Notes

Cycle

Current

Cycle

(Extended) Mode Register Set H H LLLLBA OP Code 1, 2

Auto-Refresh HHLLLHXXXX1

Self-Refresh Entry HLLLLHXXXX1

Self-Refresh Exit L H HXXXX X X X 1

Single Bank Precharge HHLLHLBAXLX1,2

Precharge all Banks HHLLHLXXHX1

Bank Activate H H L L H H BA Row Address 1, 2

Write H H L H L L BA Column L Column 1,2,3

Write with Auto-Precharge H H L H L L BA Column H Column 1,2,3

Read H H LHLHBAColumnLColumn1,2,3

Read with Auto-Precharge H H LHLHBAColumnHColumn1,2,3

No Operation HXLHHHXXXX1

Device Deselect H X HXXXX X X X 1

Power Down Entry HL

HXXX

XXXX 1,4

LHHH

Power Down Exit LH

HXXX

XXXX 1,4

LHHH

1. All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS, and CKE at the rising edge of the clock.

2. Bank addresses (BAx) determine which bank is to be operated upon. For (E)MRS BxA selects an (Extended) Mode

3. Burst reads or writes at BL = 4 cannot be terminated. See sections “Reads interrupted by a Read” and “Writes inter-

rupted by a Write” insection 2.4.6 for details.

4. The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by

the refresh requirements outlined in section 2.7.

5. The state of ODT does not affect the states decribed in this table. The ODT function is not available during Self

Refresh.

6. “X” means “H or L (but a defined logic level)”.

7. Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be pow-

ered down and then restartet through the specified initialization sequence before normal operation can continue.

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Clock Enable (CKE) Truth Table for Synchronous Transistions

Data Mask (DM) Truth Table

Current State2

CKE

Command (N) 3,12

RAS, CAS, WE, CS

Action (N) 3Notes

Cycle 1

(N-1)

Current

Cycle 1

(N)

Power-Down

LL X Maintain Power-Down 11, 13, 15

L H DESELECT or NOP Power-Down Exit 4, 8, 11, 13

Self Refresh

LL X Maintain Self Refresh 11, 15

L H DESELECT or NOP Self Refresh Exit 4, 5, 9

Bank(s)

Active H L DESELECT or NOP Active Power-Down Entry 4,8,10,11, 13

All Banks Idle

H L DESELECT or NOP Precharge Power-Down Entry 4,8,10,11

H L AUTOREFRESH Self Refresh Entry 6, 9, 11, 13

Any State other

than listed above HH Refer to the Command Truth Table 7

1. CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.

2. Current state is the state of the DDR2 SDRAM immediately prior to clock edge N.

3. Command (N) is the command registered at clock edge N, and Action (N) is a result of Command (N).

4. All states and sequences not shown are illegal or reserved unless explicitely described elsewhere in this document.

5. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occuring during the tXSNR period.

Read commands may be issued only after tXSRD (200 clocks) is satisfied.

6. Self Refresh mode can only be entered from the All Banks Idle state.

7. Must be a legal command as defined in the Command Truth Table.

8. Valid commands for Power-Down Entry and Exit are NOP and DESELECT only.

9. Valid commands for Self Refresh Exit are NOP and DESELCT only.

10. Power-Down and Self Refresh can not be entered while Read or Write operations, (Extended) mode Register operations, Precharge or

Refresh operations are in progress. See section 2.8 “Power Down” and section 2.7.2 “Self Refresh Command” for a detailed list of

restrictions.

11. Minimum CKE high time is 3 clocks, minimum CKE low time is 3 clocks.

12. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.

13. The Power-Down Mode does not perform any refresh operations. The duration of Power-Down Mode is therefor limited by the refresh

requirements.

14. CKE must be maintained high while the device is in OCD calibration mode.

15. “X” means “don’t care (including floating around VREF)” in Self Refresh and Power Down. However ODT must be driven high or

low in Power Down if the ODT function is enabled (Bit A2 or A6 set to “1” in EMRS(1)).

16. Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered

down and then restartet through the specified initialization sequence before normal operation can continue.

Name (Function) DM DQs Notes

Write Enable L Valid 1

Write Inhibit H X 1

1. Used to mask write data; provided coincident with the corresponding data.

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Operating Conditions

Absolute Maximum Ratings

DRAM Component Operating Temperature Range

Symbol Parameter Rating Units Notes

VDD Voltage on VDD pin relative to VSS -1.0 to + 2.3 V 1

VDDQ Voltage on VDDQ pin relative to VSS -0.5 to + 2.3 V 1

VDDL Voltage on VDDL pin relative to VSS -0.5 to + 2.3 V 1

VIN, VOUT Voltage on any pin relative to VSS -0.5 to + 2.3 V 1

TSTG Storage Temperature -55 to + 100 °C 1, 2

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is

not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to

JESD51-2 standard.

Symbol Parameter Rating Units Notes

TOPER Operating Temperature 0 to 85 oC 1, 2

1. Operating Temperature is the case surface temperature on the center / top side of the DRAM. For measurement conditions, please refer to the

JEDEC document JESD51-2.

2. The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case

temperature must be maintained between 0 - 85oC under all other specifcation parameters.

3. Outside of this temperature range, even it is still within the limit of stress condition, some deviation on portion of operation specification may

be required.

4. Some application may require to operate the DRAM up to 95oC case temperature. In this case above 85oC case temperature the Auto-Refresh

command frequency has to be reduced to tREFI = 3.9 µs and some AC timing parameter will reach or exceed their specified limit values.

5. Self-Refresh period is hard-coded in the chip and therefore it is imperative that the system ensures the DRAM is below 85oC case temperature

before initiating self-refresh operation.

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AC & DC Operating Conditions

DC Operating Conditions

Recommended DC Operating Conditions (SSTL_18)

ODT DC Electrical Characteristrics:

Symbol Parameter

Rating

Units Notes

Min. Typ. Max.

VDD Supply Voltage 1.7 1.8 1.9 V 1

VDDDL Supply Voltage for DLL 1.7 1.8 1.9 V 1

VDDQ Supply Voltage for Output 1.7 1.8 1.9 V 1

VREF Input Reference Voltage 0.49 * VDDQ 0.5 * VDDQ 0.51 * VDDQ V 2, 3

VTT Termination Voltage VREF - 0.04 VREF VREF + 0.04 V 4

1. VDDQ tracks with VDD, VDDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together.

2. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is

expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.

3. Peak to peak ac noise on VREF may not exceed +/- 2% VREF (dc).

4. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF

and must track variations in die dc level of VREF.

Parameter / Condition Symbol min. nom. max. Units Notes

Rtt eff. impedance value for EMRS(1)(A6,A2)=0,1; 75 ohm Rtt1(eff) 60 75 90 Ω1

Rtt eff. impedance value for EMRS(1)(A6,A2)=0,1; 150 ohm Rtt2(eff) 120 150 180 Ω1

Deviation of VM with respect to VDDQ / 2 delta VM - 3.75 + 3.75 % 2

1) Measurement Definition for Rtt(eff):

Apply VIHac and VILac to test pin seperately, then measure current I(VIHac) and I(VILac) respectively.

Rtt(eff) = (VIHac - VILac) /( I(VIHac) - I(VILac))

2) Measurement Defintion for VM:

Measure voltage (VM) at test pin (midpoint) with no load:

delta VM =(( 2* VM / VDDQ) - 1 ) x 100%

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DC & AC Logic Input Levels

DDR2 SDRAM pin timing are specified for either single ended or differential mode depending on the setting of the

EMRS(1) “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The

method by which the DDR2 SDRAM pin timing are measured is mode dependent. In single ended mode, timing

relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode,

these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinc-

tion in timing methods is guaranteed by design and characterisation. In single ended mode, the DQS (and RDQS)

signals are internally disabled and don’t care.

Single-ended DC & AC Logic Input Levels

Single-ended AC Input Test Conditions

Symbol Parameter Min. Max. Units

VIH (dc) DC input logic high VREF + 0.125 VDDQ + 0.3 V

VIL (dc) DC input low - 0.3 VREF - 0.125 V

VIH (ac) AC input logic high VREF + 0.250 - V

VIL (ac) AC input low - VREF - 0.250 V

Symbol Condition Value Units Notes

VREF Input reference voltage 0.5 * VDDQ V 1, 2

VSWING(max) Input signal maximum peak to peak swing 1.0 V 1, 2

SLEW Input signal minimum slew rate 1.0 V / ns 3, 4

1. This timing and slew rate definition is valid for all single-ended signls execpt tis, tih, tds, tdh.

2. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test.

3. The input signal minimum slew rate is to be maintained over the range from VIL(dc)max to VIH(ac)min for rising edges and the range

from VIH(dc)min to VIL(ac)max for falling edges as shown in the below figure.

4. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to

VIL(ac) on the negative transitions.

DDQ

IH(ac)

min

IH(dc)

min

REF

IL(dc)

max

IL(ac)

max

SWING(MAX)

delta TRdelta TF

Start of Falling Edge Input Timing Start of Rising Edge Input Timing

IH(dc)

min - V

IL(ac)

max

delta TF

Falling Slew = Rising Slew = V

IH(ac)

min - V

IL(dc)

max

delta TR

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Differential DC and AC Input and Output Logic Levels

Symbol Parameter min. max. Units Notes

VIN(dc) DC input signal voltage -0.3 VDDQ + 0.3 1

VID(dc) DC differential input voltage 0.25 VDDQ + 0.6 2

VID(ac) AC differential input voltage 0.5 VDDQ + 0.6 V 3

VIX(ac) AC differential cross point input voltage 0.5 * VDDQ - 0.175 0.5 * VDDQ + 0.175 V 4

VOX(ac) AC differential cross point output voltage 0.5 * VDDQ - 0.125 0.5 * VDDQ + 0.125 V 5

notes:

1) VIN(dc) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS,etc.

2) VID(dc) specifies the input differential voltage VTR - VCP required for switching. The minimum value is equal to VIH(dc) - VIL(dc).

3) VID(ac) specifies the input differential voltage VTR - VCP required for switching. The minimum value is equal to VIH(ac) - VIL(ac).

4) The value of VIX(ac) is expected to equal 0.5 x VDDQ of the transmitting device and VIX(ac) is expected to track variations in VDDQ.

VIX(ac) indicates the voltage at which differential input signals must cross.

5) The value of VOX(ac) is expected to equal 0.5 x VDDQ of the transmitting device and VOX(ac) is expected to track variations in

VDDQ. VOX(ac) indicates the voltage at which differential input signals must cross.

Crossing Point

VDDQ

VSSQ

VID

VIX or VOX

VTR

VCP

SSTL18_3

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Output Buffer Levels

Output AC Test Conditions

Output DC Current Drive

OCD Default Setting Table

Symbol Parameter SSTL_18 Class II Units Notes

VOH Minimum Required Output Pull-up under AC Test Load VTT + 0.603 V

VOL Maximum Required Output Pull-down under AC Test Load VTT – 0.603 V

VOTR Output Timing Measurement Reference Level 0.5 * VDDQ V1

1. The VDDQ of the device under test is referenced.

Symbol Parameter Class II Units Notes

IOH Output Minimum Source DC Current, nominal -13.4 mA 1, 3, 4

IOL Output Minimum Sink DC Current, nominal 13.4 mA 2, 3, 4

1. VDDQ = 1.7 V ; VOUT = 1.42 V. (VOUT-VDDQ) / IOH must be less than 21 ohm for values of VOUT between VDDQ and VDDQ - 280

mV.

2. VDDQ = 1.7 V ; VOUT = 280 mV. VOUT / IOL must be less than 21 ohm for values of VOUT between 0V and 280 mV.

3. The dc value of VREF applied to the receiving device is set to VTT

4. The values of IOH(dc) and IOL(dc) are based on the conditions given in note 1 and 2. They are used to test drive current capability to

ensure VIHmin. plus a noise margin and VILmax. minus a noise margin are delivered to an SSTL_18 receiver. The actual current values

are derived by shifting the desired driver operating points along 21 ohm load line to define a convenient current for measurement.

Symbol Description min. nominal max. Unit Notes

tbd. Output Impedance 12.6 18 23.4 Ohms 1,2

tbd. Pull-up / Pull down mismatch 0 - 4 Ohms 1,2, 3

tbd. Output Impedance step size for OCD cali-

bration

0tbd. Ohms 6

tbd. Output Slew Rate 1.5 - 6 V / ns 1, 4, 5

1) Absolute Specification: 0 °C ≤ TCASE ≤ 85 °C ; VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V.

2) Impedance measurement condition for output source dc current : VDDQ = 1.7V, VOUT = 1420 mV;

(VOUT-VDDQ)/IOH must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ-280mV. Impedance measurement

condition for output sink dc current : VDDQ = 1.7 V; VOUT = -280mV; VOUT / IOL must be less than 23.4 ohms for values of VOUT

between 0V and 280 mV.

3) Mismatch is absolute value between pull-up and pull-down, both are measured at same

temperature and voltage.

4) Slew rates measured from Vil(AC) to Vih(AC) with the load specified in Section 8.2.

5) The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This

is guaranteed by design and characterisation.

6) This represents the step size when the OCD is near 18 ohms at nominal conditions across all process parameters and represents only the

DRAM uncertainty. A 0 Ohm value (no calibration) can only be achieved if the OCD impedance is 18 +/- 0.75 ohms under nominal con-

ditions.

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Default Output V-I Characteristics

DDR2 SDRAM output driver characteristics are defined for full strength default operation as selected by the EMRS(1) bits

A7~A9 = ’111’. Figures in Section 5.3.5 and 5.3.6 show the driver characteristics graphically and the tables sow the same data

suitable for input into simulation tools.

Full Strength Default Pullup Driver Characteristics

Voltage (V) Minimum

(23.4 Ohms)

Nomal Default low

(18 Ohms)

Nomal Default high

(18 Ohms)

Maximum

(12.6 Ohms)

0.2 -8.5 -11.1 -11.8 -15.9

0.3 -12.1 -16.0 -17.0 -23.8

0.4 -14.7 -20.3 -22.2 -31.8

0.5 -16.4 -24.0 -27.5 -39.7

0.6 -17.8 -27.2 -32.4 -47.7

0.7 -18.6 -29.8 -36.9 -55.0

0.8 -19.0 -31.9 -40.8 -62.3

0.9 -19.3 -33.4 -44.5 -69.4

1.0 -19.7 -34.6 -47.7 -75.3

1.1 -19.9 -35.5 -50.4 -80.5

1.2 -20.0 -36.2 -52.5 -84.6

1.3 -20.1 -36.8 -54.2 -87.7

1.4 -20.2 -37.2 -55.9 -90.8

1.5 -20.3 -37.7 -57.1 -92.9

1.6 -20.4 -38.0 -58.4 -94.9

1.7 -20.6 -38.4 -59.6 -97.0

1.8 -38.6 -60.8 -99.1

1.9 -101.1

The driver characteristics evaluetion conditions are:

Nominal Default 25oC (Tcase) , VDDQ = 1.8 V, typical process

Minimum tbd. oC (Tcase), VDDQ = 1.7V, slow-slow process

Maximum 0 oC (Tcase). VDDQ = 1.9 V, fast-fast process

-120

-100

-80

-60

-40

-20

0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2

VDDQ to VOUT (V)

Pullup current (mA)

Minimum

Nominal Default Low

Nominal Default High

Maximum

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Full Strength Default Pulldown Driver Characteristics

Voltage (V) Minimum

(23.4 Ohms)

Nomal Default low

(18 Ohms)

Nomal Default high

(18 Ohms)

Maximum

(12.6 Ohms)

0.2 8.5 11.3 11.8 15.9

0.3 12.1 16.5 16.8 23.8

0.4 14.7 21.2 22.1 31.8

0.5 16.4 25.0 27.6 39.7

0.6 17.8 28.3 32.4 47.7

0.7 18.6 30.9 36.9 55.0

0.8 19.0 33.0 40.9 62.3

0.9 19.3 34.5 44.6 69.4

1.0 19.7 35.5 47.7 75.3

1.1 19.9 36.1 50.4 80.5

1.2 20.0 36.6 52.6 84.6

1.3 20.1 36.9 54.2 87.7

1.4 20.2 37.1 55.9 90.8

1.5 20.3 37.4 57.1 92.9

1.6 20.4 37.6 58.4 94.9

1.7 20.6 37.7 59.6 97.0

1.8 37.9 60.9 99.1

1.9 101.1

The driver characteristics evaluetion conditions are:

Nominal Default 25oC (Tcase) , VDDQ = 1.8 V, typical process

Minimum tbd. oC (Tcase), VDDQ = 1.7V, slow-slow process

Maximum 0 oC (Tcase). VDDQ = 1.9 V, fast-fast process

100

120

0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2

VOUT to VSSQ (V)

Pulldown current (mA)

Minimum

Nominal Default Low

Nominal Default High

Maximum

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Calibrated Output Driver V-I Characteristics

DDR2 SDRAM output driver characteristics are defined for full strength calibrated operation as selected by the procedure out-

lined in the Off-Chip Driver (OCD) Impedance Adjustment. The following tables show the data in tabular format suitable for

input into simulation tools. The nominal points represent a device at exactly 18 ohms. The nominal low and nominal high val-

ues represent the range that can be achieved with a maximum 1.5 ohms step size with no calibration error at the exact nominal

conditions only (i.e. perfect calibration procedire, 1.5 ohm maximum step size guarantedd by specification). Real system cali-

bration error needs to be added to these values. It must be understodd that these V-I curves are represented here or in supplier

IBIS models need to be adjusted to a wider range as a result of any system calibration error. Since this a system specific phe-

nomena, it cannot be quantified here. the values in the calibrated tables represent just the DRAM portion of uncertainty while

looking at one DQ only. If the calibration procedure is used, it is possible to cause the device to operate outside the bounds of

the default device characterisitcs tables and figure. in such a situation, the timing paramters in the specification cannot be guar-

anteed. It is solely up to the system application to ensure that the device is calibrated between the minimum and maximum

default values at all times. If this can’t be guaranteed by the system calibration procedure, re-calibration policy and uncertainty

with DQ to DQ variation, the it is recommende that only the default values to be used. The nominal maximum ad minmum

values represent the change in impedance from nominal low and high as a result of voltage and temperature change from the

nominal condition to the maximum and minimum conditions. If calibrated at an extreme condition, the amount of variation

could be as much as from the nominal minimum to the nominal maximum or vice versa.

Full Strength Calibrated Pulldown Driver Characteristics

Full Strength Calibrated Pullup Driver Characteristics

Voltage ( V ) Nominal Minimum

(21 Ohms)

Nomal Low

(18.75 Ohms)

Nominal

(18 ohms)

Nomal High

(17.25 Ohms)

Nominal Maximum

(15 Ohms)

0.2 9.5 10.7 11.5 11.8 13.3

0.3 14.3 16.0 16.6 17.4 20.0

0.4 18.7 21.0 21.6 23.0 27.0

The driver characteristics evaluetion conditions are:

Nominal 25oC (Tcase) , VDDQ = 1.8 V, typical process

Nominal Low and Nominal High 25oC (Tcase), VDDQ = 1.8V, any process

Nominal Minimum tbd. oC (Tcase). VDDQ = 1.7 V, any process

Nominal Maximum 0oC (Tcase), VDDQ = 1.9 V, any process

Voltage ( V ) Nominal Minimum

(21 Ohms)

Nomal Low

(18.75 Ohms)

Nominal

(18 ohms)

Nomal High

(17.25 Ohms)

Nominal Maximum

(15 Ohms)

0.2 -9.5 -10.7 -11.4 -11.8 -13.3

0.3 -14.3 -16.0 -16.5 -17.4 -20.0

0.4 -18.3 -21.0 -21.2 -23.0 -27.0

The driver characteristics evaluetion conditions are:

Nominal 25oC (Tcase) , VDDQ = 1.8 V, typical process

Nominal Low and Nominal High 25oC (Tcase), VDDQ = 1.8V, any process

Nominal Minimum tbd. oC (Tcase). VDDQ = 1.7 V, any process

Nominal Maximum 0oC (Tcase), VDDQ = 1.9 V, any process

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Input / Output Capacitance

Power & Ground Clamp V-I Characteristics

Power and Ground clamps are provided on address (A0~A13, BA0, BA1), RAS, CAS, CS, WE, CKE and ODT

pins. The V-I characterisitcs for pins with clamps is shown in the following table :

Symbol Parameter min. max. Units

CCK Input capacitance, CK and CK 1.0 2.0 pF

CDCK Input capacitance delta, CK and CK -0.25pF

CI Input capacitance, all other input-only pins 1.0 2.0 pF

CDI Input capacitance delta, all other input-only pins - 0.25 pF

CIO Input/output capacitance,

DQ, DM, DQS, DQS, RDQS, RDQS 3.0 4.0 pF

CDIO Input/output capacitance delta,

DQ, DM, DQS, DQS, RDQS, RDQS -0.5pF

Voltage across clamp (V)

Minimum Power Clamp

Current (mA)

Minimum Ground

Clamp Current (mA)

0.0 0 0

0.1 0 0

0.2 0 0

0.3 0 0

0.4 0 0

0.5 0 0

0.6 0 0

0.7 0 0

0.8 0.1 0.1

0.9 1.0 1.0

1.0 2.5 2.5

1.1 4.7 4.7

1.2 6.8 6.8

1.3 9.1 9.1

1.4 11.0 11.0

1.5 13.5 13.5

1.6 16.0 16.0

1.7 18.2 18.2

1.8 21.0 21.0

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IDD Specifications and Measurement Conditions

IDD Specifications

( VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V)

Symbol Parameter/Condition I/O

-5

DDR2 -400

-3.7

DDR2 -533

-3

DDR2 - 667 Unit Notes

typ. max. typ. max. typ. max.

IDD0 Operating Current x4/ x8

x16

75 TBD TBD mA 1, 2

IDD1 Operating Current x4/ x8

x16

90 TBD TBD mA 1, 2

IDD2P Precharge Power-Down Current all 2 3 3 4 TBD TBD mA 1, 2

IDD2N Precharge Standby Current all 24 28 30 36 TBD TBD mA 1, 2

IDD2Q Precharge Quiet Standby Current: all 14 19 18 25 TBD TBD mA 1, 2

IDD3P

Active Power-Down

Standby

Current

MRS(12)=0 all 8 11 10 15 TBD TBD mA 1, 2

MRS(12)=1 all 3 5 3 5 TBD TBD mA 1, 2

IDD3N Active Standby Current x4/x8

x16

42 TBD TBD mA 1, 2

IDD4R Operating Current Burst Read x 4 / x 8

x16

110 TBD TBD mA 1, 2

IDD4W Operating Current Burst Write x 4 / x 8

x16

110 TBD TBD mA 1, 2

IDD5B Burst Auto-Refresh Current

(tRFC=tRFCmin)

x 4 / x 8

x16

105

110

125

130

110

115

135

150 TBD TBD mA 1, 2

IDD5D Distributed Auto-Refresh Current

(tRFC=tREFI) all 2.6 5.5 2.6 5.5 TBD TBD mA 1, 2

IDD6 Self-Refresh Current for standard

products

x 4 / x 8

x16 2323TBDTBD

mA 1, 2

IDD7 Operating Current x4/ x8

x16

150

180

175

200

160

190

185

210 TBD TBD mA 1

1. IDD specifications are tested after the device is properly initialized. IDD parameters are specified with ODT disabled.

2. Input slew rate = 1 V/ns.

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IDD Measurement Conditions

( VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V)

Symbol Parameter/Condition

IDD0

Operating Current - One bank Active - Precharge

tCK =tCKmin.; tRC = tRCmin; tRAS = tRASmin; CKE is HIGH, CS is HIGH between valid commands.

Address and control inputs are SWITCHING; Data bus inputs are SWITCHING;

IDD1

Operating Current - One bank Active - Read - Precharge

IOUT = 0 mA; BL = 4, tCK = tCKmin, tRC = tRCmin; tRAS = tRASmin; tRCD = tRCDmin, CL = CLmin.;AL = 0;

CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCHING,Data bus inputs are SWITCHING;

IDD2P

Precharge Power-Down Current: All banks idle; CKE is LOW; tCK = tCKmin.; Other control and address inputs are STABLE,

Data Bus inputs are FLOATING.

IDD2N

Precharge Standby Current: All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and address bus inputs

are SWICHTING; Data bus inputs are SWITCHING.

IDD2Q

Precharge Quiet Standby Current:All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and address bus

inputs are STABLE; Data bus inputs are FLOATING.

IDD3P(0)

Active Power-Down Current: All banks open; tCK = tCKmin.;CKE is LOW; Other control and address inputs are STABLE;

Data Bus inputs are FLOATING. MRS A12 bit is set to “0”( Fast Power-down Exit);

IDD3P(1)

Active Power-Down Current: All banks open; tCK = tCKmin.;CKE is LOW; Other control and address inputs are STABLE;

Data Bus inputs are FLOATING. MRS A12 bit is set to “1”( Slow Power-down Exit);

IDD3N

Active Standby Current: All banks open; tCK = tCKmin.; tRAS = tRASmax.; tRP = tRPmin., CKE is HIGH; CS is HIGH

between valid commands; Other control and address inputs are SWITCHING; Data Bus inputs are SWITCHING.

IDD4R

Operating Current - Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.;

tRAS = tRASmax., tRP = tRPmin., CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data

bus inputs are SWITCHING; IOUT = 0mA.

IDD4W

Operating Current - Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.;

tRAS = tRASmax., tRP = tRPmin.;CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data

Bus inputs are SWITCHING.

IDD5B Burst Auto-Refresh Current: tCK = tCKmin.; Refresh command every tRFC = tRFCmin interval; CKE is HIGH, CS is HIGH

between valid commands; Other control and adress inputs are SWITCHING; Data bus inputs are SWITCHING.

IDD5D Distributed Auto-Refresh Current: tCK = tCKmin.; Refresh command every tREFI interval; CKE is HIGH, CS is HIGH

between valid commands; Other control and adress inputs are SWITCHING; Data bus inputs are SWITCHING

IDD6 Self-Refresh Current: CKE ≤ 0.2V; external clock off, CK and CK at 0V; Other control and address inputs are FLOATING;

Data Bus inputs are FLOATING.

IDD7

Operating Bank Interleave Read Current:

1. All bank interleaving reads; IOUT = 0 mA, BL =4, CL = CLmin., AL = tRCDmin. - 1*tCK; tCK = tCKmin., tRC = TRCmin.;

tRRD = tRRDmin; tRCD = 1*tCK, CKE = HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE

during DESELECTS.

2. Timing pattern:

- DDR2 -400 : A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D

- DDR2 -533 : A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D

- DDR2 -667 : A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D

3. Legend : A=Activate, RA=Read with Auto-Precharge, D=DESELECT

1. IDD specifications are tested after the device is properly initialized.

2. IDD parameter are specified with ODT disabled.

3. Data Bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS and UDQS.

4. Definitions for IDD :

LOW is defined as VIN <= VILAC(max.); HIGH is defined as VIN >= VIHAC(min.);

STABLE is defined as inputs are stable at a HIGH or LOW level

FLOATING is defined as inputs are VREF = VDDQ / 2

SWITCHING is defined as:

Inputs are changing between HIGH and LOW every other clock (once per two clocks) for adress and control signals, and

inputs changing between HIGH and LOW every other clock (once per two clocks) for DQ signals not including mask or strobes

5. Timing parameter minimum and maximum values for IDD current measurements are defined in the following table.

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IDD Measurement Conditions (cont’d)

For testing the IDD parameters, the following timing parameters are used:

ODT (On Die Termination) Current

The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS(1).

Depending on address bits A6 & A2 in the EMRS(1) a “week” or “strong” termination can be selected. The current

consumption for any terminated input pin, depends on the input pin is in tri-strate or driving “0” or “1”, as long a

ODT is enabled during a given period of time.

ODT current per terminated input pin :

Parameter Symbol

-5

DDR2 -400

-3.7

DDR2 -533

-3

DDR2 - 667 Unit

3-3-3 4-4-4 4-4-4

CAS Latency CLmin 3 4 4 tCK

Clock Cycle Time tCKmin 3 3.75 5 ns

Active to Read or Write delay tRCDmin 15 15 12 ns

Active to Active / Auto-Refresh command

period tRCmin 60 60 57 ns

Active bank A to Active bank

B command delay

x4 & x8 tRRDmin 7.5 7.5 7.5 ns

x16 tRRDmin 10 10 10 ns

Active to Precharge Command tRASmin 45 45 45 ns

tRASmax 70000 70000 70000 ns

Precharge Command Period tRPmin 15 15 12 ns

Auto-Refresh to Active / Auto-Refresh com-

mand period tRFCmin 105 105 105 ns

Average periodic Refresh interval tREFI 7.8 7.8 7.8 µs

EMRS(1) State min. typ. max. Unit

Enabled ODT current per DQ

added IDDQ current for ODT enabled;

ODT is HIGH; Data Bus inputs are FLOATING

IODTO

A6 = 0, A2 = 1 5 6 7.5 mA/DQ

A6 = 1, A2 = 0 2.5 3 3.75 mA/DQ

Active ODT current per DQ

added IDDQ current for ODT enabled;

ODT is HIGH; worst case of Data Bus inputs are

STABLE or SWITCHING.

IODTT

A6 = 0, A2 = 1 10 12 15 mA/DQ

A6 = 1, A2 = 0 5 6 7.5 mA/DQ

note: For power consumption calculations the ODT duty cycle has to be taken into account

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Electrical Characteristics & AC Timing - Absolute Specification

Timing Parameter by Speed Grade

( VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V) (notes 1-4)

Symbol Parameter

-5

DDR2 -400

-3.7

DDR2 -533

-3

DDR2 -667 Unit Notes

min max min max min max

tAC DQ output access time from CK / CK - 600 + 600 -500 +500 tbd tbd ps

tDQSCK DQS output access time from CK / CK - 500 + 500 -450 +450 tbd tbd ps

tCH CK, CK high-level width 0.45 0.55 0.45 0.55 0.45 0.55 tCK

tCL CK, CK low-level width 0.45 0.55 0.45 0.55 0.45 0.55 tCK

tHP Clock half period min (tCL, tCH) min (tCL, tCH) min (tCL, tCH) 5

tCK Clock cycle time

CL = 3 5000 8000 5000 8000 5000 8000 ps 6

CL = 4 & 5 5000 8000 3750 8000 3000 8000 ps 6

tIS Address and control input setup time 350 - 250 - tbd - ps 7

tIH Address and control input hold time 475 - 375 - tbd - ps 7

tDH DQ and DM input hold time 150 - 100 - tbd - ps 8

tDS DQ and DM input setup time 275 - 225 - tbd - ps 8

tIPW

Address and control input pulse width

(each input) 0.6 - 0.6 - 0.6 - tCK

tDIPW DQ and DM input pulse width (each input) 0.35 - 0.35 - 0.35 - tCK

tHZ Data-out high-impedence time from CK / CK -tACmax-tACmax-tACmaxps 9

tLZ Data-out low-impedence time from CK / CK tACmin tACmax tACmin tACmax tACmin tACmax ps 9

tDQSQ

DQS-DQ skew

(for DQS & associated DQ signals) - 350 - 300 - tbd ps

tQHS Data hold skew factor - 450 - 400 - tbd ps

tQH Data output hold time from DQS tHP-tQHS -t

HP-tQHS -t

HP-tQHS -

tDQSS Write command to 1st DQS latching transition WL

-0.25

+0.25

-0.25

+0.25

-0.25

+0.25 tCK

tDQSL,H DQS input low (high) pulse width (write cycle) 0.35 - 0.35 - 0.35 - tCK

tDSS DQS falling edge to CK setup time (write cycle) 0.2 - 0.2 - 0.2 - tCK

tDSH DQS falling edge hold time from CK (write cycle) 0.2 - 0.2 - 0.2 - tCK

tMRD Mode register set command cycle time 2 - 2 - 2 - tCK

tWPRES Write preamble setup time 0 - 0 - 0 - ps

tWPRE Write preamble 0.25 - 0.25 - 0.25 - tCK

tWPST Write postamble 0.40 0.60 0.40 0.60 0.40 0.60 tCK 10

tRPRE Read preamble 0.9 1.1 0.9 1.1 0.9 1.1 tCK 9

tRPST Read postamble 0.40 0.60 0.40 0.60 0.40 0.60 tCK 9

tRAS Active to Precharge command 45 70000 45 70000 45 70000 ns 11

tRC Active to Active/Auto-Refresh command period 60 - 60 - 57 - ns

tRFC

Auto-Refresh to Active/Auto-Refresh command

period 105 - 105 - 105 - ns 12

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tRCD

Active to Read or Write

(with and without Auto-Precharge) delay 15 - 15 - 12 - ns 13

tRP Precharge command period 15 - 15 - 12 - ns

tRRD

Active bank A to Active bank

B command period

x4 & x8

(1k page size) 7.5 - 7.5 - 7.5 - ns

x16 (2k page size) 10 - 10 - 10 ns

tCCD CAS A to CAS B command period 2 2 2 tCK

tWR Write recovery time 15 - 15 - 12 - ns

tDAL Auto-Precharge write recovery + precharge time WR+tRP - WR+tRP - WR+tRP - tCK 14

tWTR Internal Write to Read command delay 10 - 7.5 - 7.5 - ns 15

tRTP Internal Read to Precharge command delay 7.5 - 7.5 - 7.5 - ns

tXARD

Exit power down to any valid command

(other than NOP or Deselect) 2-2-2-t

CK 16

tXARDS

Exit active power-down mode to Read command

(slow exit, lower power) 6 - AL - 6 - AL - 6 - AL - tCK 16

tXP

Exit precharge power-down to any valid com-

mand (other than NOP or Deselect) 2-2-2-t

tXSRD Exit Self-Refresh to Read command 200 - 200 - 200 - tCK

tXSNR Exit Self-Refresh to non-Read command tRFC+10 - tRFC+10 tRFC+10 - ns

tCKE CKE minimum high and low pulse width 3 - 3 - 3 - tCK

tREFI Average periodic refresh Interval - 7.8 - 7.8 - 7.8 µs

tOIT OCD drive mode output delay 0 12 0 12 0 12 ns

tDELAY

Minimum time clocks remain ON after CKE

asynchronously drops LOW

tIS+tCK

+tIH -tIS+tCK

+tIH -ns17

Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then

restartet through the specified initialization sequence before normal operation can continue.

Symbol Parameter

-5

DDR2 -400

-3.7

DDR2 -533

-3

DDR2 -667 Unit Notes

min max min max min max

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ODT AC Electrical Characteristics and Operating Conditions (all speed bins)

Symbol Parameter / Condition min. max. Units Notes

tAOND ODT turn-on delay 2 2 tCK

tAON ODT turn-on tAC(min) tAC(max) + 1ns ns 18

tAONPD ODT turn-on (Power-Down Modes) tAC(min) + 2ns 2 tCK + tAC(max) + 1ns ns

tAOFD ODT turn-off delay 2.5 2.5 tCK

tAOF ODT turn-off tAC(min) tAC(max) + 0.6ns ns 19

tAOFPD ODT turn-off (Power-Down Modes) tAC(min) + 2ns 2.5 tCK + tAC(max) + 1ns ns

tANPD ODT to Power Down Mode Entry Latency 3 - tCK

tAXPD ODT Power Down Exit Latency 8 - tCK

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Notes for Electrical Characteristics & AC Timing

1. Timings are guaranteed with CK/CK differential slew rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential slew

rate of 2.0 V/ns in differential strobe mode and a slew rate of 1 V/ns in single ended mode. For other slew rates see Section 8 of this

datasheet.

2. The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross.

The DQS / DQS,RDQS/ RDQS, input reference level is the crosspoint when in differential strobe mode;

The input reference level for signals other than CK/CK, DQS / DQS, RDQS / RDQS, tIS, tiH,tDS, tDH is VREF.

For tIS, tiH, tDS, tDH input reference levels see section 8.3 of this datasheet

3. Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized

as LOW.

4. The output timing reference voltage level is VTT. See section 8 for the reference load for timing measurements.

5. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value

can be greater than the minimum specification limits for tCL and tCH.

6. For input frequency change during DRAM operation, see the 2.11 section of this datasheet.

7. For timing definition, slew rate and slew rate derating see Section 8.3

8. For timing definition, slew rate and slew rate derating see Section 8.3

9. The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no

longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid

data transitions.These parameters are guaranteed by design and characterisation, but are not tested on each device.

10. The maximum limit for this parameter is not a device limit. The device operate with a greater value for this parameter, but system per-

formance (bus turnaround) degrades accordingly.

11. tRAS(max) is calculated from the maximum amount of time a DDR2 device can operate without a Refresh command which is equal to

9 * tREFI

12. A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.

13. The tRCD timing parameter is valid for both activate command to read or write command with and without Auto-Precharge. Therefore

a separate parameter tRAP for activate command to read or write command with Auto-Precharge is not neccessary anymore.

14. For each of the terms, if not allready an integer, round to the next highest integer. tCK refers to the application clock period. WR refers

to the WR parameter stored in the MRS.

15. tWTR is at least two clocks independent of operation frequency.

16. User can choose two different active power-down modes for additional power saving via MRS address bit A12.

In “standard active power-down mode” (MRS, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-

down mode” (MRS, A12 =”1”) a slow power-down exit timing tXARDS has to be satisfied.

17. The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock frequency change

during power-down, a specific procedure is required as describes in section 2.12.

18. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.

ODT turn on time max is when the ODT resistance is fully on. Both are measure from tAOND.

19. ODT turn off time min is when the device starts to turn off ODT resistance

ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.

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Reference Loads, Setup & Hold Timing Definition and Slew Rate Derating

Reference Load for Timing Measurements

The figure represents the timing reference load used in defining the relevant timing parameters of the device. It is

not intended to either a precise representation of the typical system environment nor a depiction of the actual load

presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing

reference load to a system environment. Manufacturers correlate to their production test conditions, generally a

coaxial transmission line terminated at the tester electronics. This reference load is also used for output slew rate

characterisation.

The output timing reference voltage level for single ended signals is the crosspoint with VTT.

The output timing reference voltage level for differential signals is the crosspoint of the true ( e.g. DQS) and the

complement (e.g. DQS) signal.

Slewrate Measurements

Output Slewrate

With the reference load for timing measurements output slew rate for falling and rising edges is measured between

VTT - 250 mV and VTT + 250 mV for single ended signals.For differential signals (e.g. DQS / DQS) output slew

rate is measured between DQS - DQS = - 500 mV and DQS - DQS = + 500 mV. Output slew rate is guaranteed by

design, but is not necessarily tested on each device.

Input Slewrate - Differential signals

Input slewrate for differential signals ( CK / CK, DQS / DQS, RDQS / RDQS) for rising edges are measured from

f.e. CK - CK = -250 mV to CK - CK = + 500 mV and from CK - CK = +250 mV to CK - CK = - 500mV for falling

edges.

Input Slewrate - Single ended signals

Input slew rate for single ended signals (other than tis, tih, tds and tdh) are measured from dc-level to ac-level:

VREF -125 mV to VREF + 250 mV for rising edges and from VREF + 125 mV to VREF - 250 mV for falling edges.

For slew rate definition of the input and data setup and hold parameters see section 8.3 of this datasheet.

25 Ohm Vtt = VDDQ / 2

CK, CK

DUT

Timing Reference Points

VDDQ

DQS

RDQS

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Input and Data Setup and Hold Time

Timing Definition for Input Setup (tIS) and Hold Time (tIH)

Address and control input setup time (tIS) is referenced from the input signal crossing at the VIH(ac) level for a rising signal

and VIL(ac) for a falling signal applied to the device under test. Address and control input hold time (tIH) is referenced from

the input signal crossing at the VIL(dc) level for a rising signal and VIH(dc) for a falling signal applied to the device under test

Timing Definition for Data Setup (tDS) and Hold Time (tDH)

1. Data input setup time with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the VIH(ac) level

to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL(ac) level tothe differential data

strobe crosspoint for a falling signal applied to the device under test. Input waveform timing with single-endeddata strobe enabled

MR[bit10]=1, is referenced from the input signal crossing at the VIH(ac) level to the data strobe crossing Vref for a rising signal, and

from the input signal crossing at the VIL(ac) level to the single-ended data strobe crossing Vref for a falling signal applied to the device

under test.

2. Data input hold time with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the VIL(dc) level to

the differential data strobe crosspoint for a rising signal and VIH(dc) to the differential data strobe crosspoint for a falling signal applied

to the device under test. Input waveform timing with single-ended data strobe enabled MR[bit10]=1, is referenced from the input signal

crossing at the VIL(dc) level to the single-ended data strobe crossing Vref for a rising signal and VIH(dc) to the single-ended data strobe

crossing Vref for a falling signal applied to the device under test

DDQ

IH(ac)

min

IH(dc)

min

REF

IL(dc)

max

IL(ac)

max

tIS tIH

DDQ

IH(ac)

min

IH(dc)

min

REF

IL(dc)

max

IL(ac)

max

tDS tDH

tDS

REF

tDH

DQS

Differential Input

Waveform

Single-ended Input

Waveform

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Slew Rate Definition for Input and Data Setup and Hold Times

Setup (tIS & tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIH(dc)min and

the first crossing of VIH(ac)min. Setup (tIS & tDS) nominal slew rate for a falling signal is defined as the slew rate between

the last crossing of VIL(dc)max and the first crossing of VIL(ac)max, (fig. A) If the actual signal is always earlier than the

nominal slew rate line between shaded ‘dc to ac region’, use nominal slew rate for derating value. If the actual signal is later

than the nominal slew rate line anywhere between shaded ‘dc to ac region’, the slew rate of a tangent line to the actual signal

from the ac level to dc level is used for derating value.(fig.B)

Hold (tIH & tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and

the first crossing of Vref. Hold (tIH & tDH) nominal slew rate for a falling signal is defined as the slew rate between the last

crossing of VIH(dc)min and the first crossing of Vref.(fig. A). If the actual signal is always later than the nominal slew rate

line between shaded ‘dc to Vref region’, use nominal slew rate for derating value. If the actual signal is earlier than the nomi-

nal slew rate line anywhere between shaded ‘dc to Vref region’, the slew rate of a tangent line to the actual signal from the dc

level to Vref level is used for derating value.(fig.B)

Setup Slew Rate =

VIL(dc)max - VIL(ac)max

Delta TFS falling signal

Setup Slew Rate =

VIH(dc)min - VIL(ac)min

Delta TRS rising signal

Hold Slew Rate =

VREF - VIL(dc)max

Delta TRH rising signal

Hold Slew Rate =

VIH(dc)min - VREF

Delta TFH falling signal

Setup Slew Rate =

VIL(dc)max - VIL(ac)max

Delta TFS falling signal

Setup Slew Rate =

VIH(dc)min - VIL(ac)min

Delta TRS rising signal

Hold Slew Rate =

VREF - VIL(dc)max

Delta TRH rising signal

Hold Slew Rate =

VIH(dc)min - VREF

Delta TFH falling signal

Setup Slew Rate =

tangent line [VIL(dc)max - VIL(ac)max]

Delta TFS

Setup Slew Rate =

tangent line [VIH(dc)min - VIL(ac)min]

Delta TRS

Hold Slew Rate =

tangent line [REF - VIL(dc)max]

Delta TRH

Hold Slew Rate =

tangent line [VIH(dc)min - VREF]

Delta TFH

falling

signal

falling

signal

rising

signal

rising

signal

IL(ac)

max

IL(dc)

max

REF

IH(dc)

min

DDQ

IH(ac)

min

Delta TFS Delta TRH Delta TFH

Delta TRS

tStH

dc to ac

region

dc to ac

region

dc to Vref

region

dc to Vref

region

fig. A fig. B

IL(ac)

max

IL(dc)

max

REF

IH(dc)

min

DDQ

IH(ac)

min

Delta TFS Delta TRH Delta TFH

Delta TRS

tStH

dc to ac

region

dc to ac

region

dc to Vref

region

dc to Vref

region

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Input Setup (tIS) and Hold (tIH) Time DeratingTable

Data Setup (tDS) and Hold Time (tDH) Derating Table

CK, CK Differential Slew Rate

2.0 V/ns 1.5 V/ns 1.0 V/ns

∆ tIS ∆ tIH ∆ tIS ∆ tIH ∆ tIS ∆ tIH

Command / Address

Slew rate

4.0 188 94 TBD TBD TBD TBD

3.5 179 89 TBD TBD TBD TBD

3.0 167 83 TBD TBD TBD TBD

2.5 150 75 TBD TBD TBD TBD

2.0 125 45 TBD TBD TBD TBD

1.5 83 21 TBD TBD TBD TBD

1.0 0 0 TBD TBD TBD TBD

0.5 0 0 TBD TBD TBD TBD

0.4 0 0 TBD TBD TBD TBD

0.3 0 0 TBD TBD TBD TBD

0.2 -50 -75 TBD TBD TBD TBD

0.15 -150 -175 TBD TBD TBD TBD

0.1 -250 -475 TBD TBD TBD TBD

1. All units in ps.

2. For all input signals the total tIS (input setup time) and tIH (input hold time) required is calculated by adding the

individual datasheet value to the derating value listed in the previous table.

DQS, DQS Differential Slew Rate

4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns

∆

tDS

∆

tDH ∆

tDS ∆

tDH ∆

tDS ∆

tDH ∆

tDS ∆

tDH ∆

tDS ∆

tDH ∆

tDS ∆

tDH ∆

tDS ∆

tDH ∆

tDS ∆

tDH ∆

tDS ∆

tDH

DQ Slewrate (V/ns)

2.0 TBDTBDTBDTBDTBDTBD------------

1.5 TBDTBDTBDTBDTBDTBDTBDTBD----------

1.0 TBD TBD TBD TBD 00

TBDTBDTBDTBD--------

0.9 - - TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD - - - - - -

0.8 - - - - TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD - - - -

0.7 ------TBDTBDTBDTBDTBDTBDTBDTBDTBDTBD--

0.6 --------TBDTBDTBDTBDTBDTBDTBDTBDTBDTBD

0.5 ----------TBDTBDTBDTBDTBDTBDTBDTBD

0.4 ------------TBDTBDTBDTBDTBDTBD

1. All units in ps.

2. For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the individual datasheet value to

the derating value listed in the previous table.

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Overshoot and Undershoot Specification

AC Overshoot / Undershoot Specification for Address and Control Pins

AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins

Parameter DDR2

-400

DDR2

-533

DDR2

-667 Units

Maximum peak amplitude allowed for overshoot area 0.9 0.9 0.9 V

Maximum peak amplitude allowed for undershoot area 0.9 0.9 0.9 V

Maximum overshoot area above VDD 0.75 0.56 0.45 V.ns

Maximum undershoot area below VSS 0.75 0.56 0.45 V.ns

Parameter DDR2

-400

DDR2

-533

DDR2

-667 Units

Maximum peak amplitude allowed for overshoot area 0.9 0.9 0.9 V

Maximum peak amplitude allowed for undershoot area 0.9 0.9 0.9 V

Maximum overshoot area above VDDQ 0.38 0.28 0.23 V.ns

Maximum undershoot area below VSSQ 0.38 0.28 0.23 V.ns

VDD

VSS

Overshoot Area

Undershoot Area

Maximum Amplitude

Time (ns)

Volts (V)

VDDQ

VSSQ

Overshoot Area

Undershoot Area

Maximum Amplitude

Time (ns)

Volts (V)

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Package Dimensions (x4/x8; 60 balls; 0.8mmx0.8mm Pitch; CSP Package)

0.80

10.0

0.80

8.0

12.5

0.10 0.35

1.15

Dia.

0.40

Note : All dimensions are typical unless otherwise stated.

Unit : Millimeters

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Package Dimensions (x16; 84 balls; 0.8mmx0.8mm Pitch; CSP Package)

0.80

10.0

0.80

11.2

12.5

0.10

0.35

1.15

Dia.

0.40

Note : All dimensions are typical unless otherwise stated.

Unit : Millimeters

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Revision Log

Rev Date Modification

0.1 08/2003 Preliminary Release

1.0 09/2004 Added Idd to specification

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Nanya Technology Corporation.

Printed in Taiwan, R.O.C., 2004

The following are trademarks of NANYA TECHNOLOGY CORPORATION in R.O.C, or other countries, or both.

NANYA NANYA logo

Other company, product and service names may be trademarks or service marks of others.

NANYA TECHNOLOGY CORPORATION (NTC) reserves the right to make changes without notice. NTC warrants performance

of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with NTC’s

standard warranty. Testing and other quality control techniques are utilize to the extent NTC deems necessary to support this

warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government

requirements.

Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or

environmental damage (“Critical Applications”).

NTC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTEND, AUTHORIZED, OR WARRANTED TO BE SUITABLE

FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.

Inclusion of NTC products in such applications is understood to be fully at the risk of the customer. Use of NTC products in such

applications requires the written approval of an appropriate NTC officer. Question concerning potential risk applications should

be directed to NTC through a local sales office.

In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards should be

provided by customer to minimize the inherent or procedural hazards.

NTC assumes no liability of applications assistance, customer product design, software performance, or infringement of patents

or services described herein. Nor does NTC warrant or represent that any license, either express or implied, is granted under

any patent right, copyright, mask work right, or other intellectual property right of NTC covering or relating to any combination,

machine, or process in which such semiconductor products or services might be or are used.

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The NANYA TECHNOLOGY CORPORATION

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