LMH6733MQX/NOPB - NATIONAL SEMICONDUCTOR

LMH6733

LMH6733 Single Supply, 1.0 GHz, Triple Operational Amplifier

Literature Number: SNOSAW0C

LMH6733

July 6, 2011

Single Supply, 1.0 GHz, Triple Operational Amplifier

General Description

The LMH6733 is a triple, wideband, operational amplifier de-

signed specifically for use where high speed and low power

are required. Input voltage range and output voltage swing

are optimized for operation on supplies as low as 3V and up

to ±6V. Benefiting from National’s current feedback architec-

ture, the LMH6733 offers a gain range of ±1 to ±10 while

providing stable operation without external compensation,

even at unity gain. These amplifiers provide 650 MHz small

signal bandwidth at a gain of 2 V/V , a low 2.1 nV/ input

referred noise and only consume 5.5 mA (per amplifier) from

a single 5V supply.

The LMH6733 is offered in a 16-Pin SSOP package with flow

through pinout for ease of layout and is also pin compatible

with the LMH6738. Each amplifier has an individual shutdown

pin.

Features

■Supply range 3 to 12V single supply

■Supply range ±1.5V to ±6V split supply

■1.0 GHz −3 dB small signal bandwidth

(AV = +1, VS = ±5V)

■650 MHz −3 dB small signal bandwidth

(AV = +2, VS = 5V)

■Low supply current (5.5 mA per op amp, VS = 5V)

■2.1 nV/ input noise voltage

■3750 V/μs slew rate

■70 mA linear output current

■CMIR and output swing to 1V from each supply rail

Applications

■HDTV component video driver

■High resolution projectors

■Flash A/D driver

■D/A transimpedance buffer

■Wide dynamic range IF amp

■Radar/communication receivers

■DDS post-amps

■Wideband inverting summer

■Line driver

Connection Diagram

16-Pin SSOP

20199110

Top View

Ordering Information

Package Part Number Package Marking Transport Media NSC Drawing

16-pin SSOP LMH6733MQ LH6733MQ 95 Units/Rail MQA16

LMH6733MQX 2.5k Units Tape and Reel

VIP10™ is a trademark of National Semiconductor Corporation.

LMH6733 Single Supply, 1.0 GHz, Triple Operational Amplifier

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

ESD Tolerance (Note 2)

Human Body Model 2000V

Machine Model 200V

Supply Voltage (V+ - V–)13.2V

IOUT (Note 3)

Common Mode Input Voltage ±VCC

Maximum Junction Temperature +150°C

Storage Temperature Range −65°C to +150°C

Soldering Information

Infrared or Convection (20 sec.) 235°C

Wave Soldering (10 sec.) 260°C

Storage Temperature Range −65°C to +150°C

Operating Ratings (Note 1)

Thermal Resistance

Package (θJC) (θJA)

16-Pin SSOP 36°C/W 120°C/W

Temperature Range (Note 4) −40°C +85°C

Supply Voltage (V+ - V–) 3V to 12V

5V Electrical Characteristics (Note 5)

AV = +2, VCC = 5V, RL = 100Ω, RF = 340Ω; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

Frequency Domain Performance

UGBW −3 dB Bandwidth Unity Gain, VOUT = 200 mVPP 870 MHz

SSBW −3 dB Bandwidth VOUT = 200 mVPP, RL = 100Ω 650

MHz

SSBW VOUT = 200 mVPP, RL = 150Ω 685

LSBW VOUT = 2 VPP 480

0.1 dB

0.1 dB Gain Flatness VOUT = 200 mVPP 320 MHz

Time Domain Response

TRS Rise and Fall Time

(10% to 90%)

2V Step 0.8 ns

SR Slew Rate 2V Step 1900 V/µs

tsSettling Time to 0.1% 2V Step 10 ns

teEnable Time From Disable = Rising Edge 10 ns

tdDisable Time From Disable = Falling Edge 15 ns

Distortion

HD2L 2nd Harmonic Distortion 2 VPP, 10 MHz −63 dBc

HD3L 3rd Harmonic Distortion 2 VPP, 10 MHz −73 dBc

Equivalent Input Noise

VN Non-Inverting Voltage >10 MHz 2.1 nV/

ICN Inverting Current >10 MHz 18.6 pA/

NCN Non-Inverting Current >10 MHz 26.9 pA/

Video Performance

DG Differential Gain 4.43 MHz, RL = 150Ω 0.03 %

DP Differential Phase 4.43 MHz, RL = 150Ω 0.025 deg

Static, DC Performance

VIO Input Offset Voltage (Note 7) 0.4 2.0

2.5 mV

IBN Input Bias Current (Note 7) Non-Inverting 2 16.7 28

32 µA

IBI Input Bias Current (Note 7) Inverting 1.0 17

19 μA

PSRR Power Supply Rejection Ratio

(Note 7)

+PSRR 59

−PSRR 58

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LMH6733

Symbol Parameter Conditions Min Typ Max Units

CMRR Common Mode Rejection Ratio

(Note 7)

51.5

54.5 dB

XTLK Crosstalk Input Referred, f = 10 MHz, Drive

Channels A,C Measure Channel B

−80 dB

ICC Supply Current (Note 7) All Three Amps Enabled, No Load 16.7 18 mA

Supply Current Disabled V+RL = ∞ 1.54 1.8 mA

Supply Current Disabled V−RL = ∞ 0.75 1.8 mA

Miscellaneous Performance

RIN+ Non-Inverting Input Resistance 200 kΩ

CIN+ Non-Inverting Input Capacitance 1 pF

RIN− Inverting Input Impedance Output Impedance of Input Buffer. 27 Ω

ROOutput Impedance DC 0.05 Ω

VOOutput Voltage Range (Note 7)RL = 100Ω 1.25-3.75

1.3-3.7 1.12-3.88

RL = ∞1.11-3.89

1.15-3.85

1.03-3.97

CMIR Common Mode Input Range

(Note 7)

CMRR > 40 dB 1.1-3.9

1.2-3.8

1.0–4.0 V

IOLinear Output Current

(Note 3, Note 7)

VIN = 0V, VOUT < ±42 mV ±50 ±60 mA

ISC Short Circuit Current (Note 6) VIN = 2V Output Shorted to Ground 170 mA

IIH Disable Pin Bias Current High Disable Pin = V+ −72 μA

IIL Disable Pin Bias Current Low Disable Pin = 0V −360 μA

VDMAX Voltage for Disable Disable Pin ≤ VDMAX 3.2 V

VDMIM Voltage for Enable Disable Pin ≥ VDMIN 3.6 V

±5V Electrical Characteristics (Note 5)

AV = +2, VCC = ±5V, RL = 100Ω, RF = 383Ω; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

Frequency Domain Performance

UGBW −3 dB Bandwidth Unity Gain, VOUT = 200 mVPP 1000 MHz

SSBW −3 dB Bandwidth VOUT = 200 mVPP, RL = 100Ω 830

MHz

SSBW VOUT = 200 mVPP, RL = 150Ω 950

LSBW VOUT = 2 VPP 600

0.1 dB BW 0.1 dB Gain Flatness VOUT = 200 mVPP 350 MHz

Time Domain Response

TRS Rise and Fall Time

(10% to 90%)

2V Step 0.7 ns

TRL 5V Step 0.8

SR Slew Rate 4V Step 3750 V/µs

tsSettling Time to 0.1% 2V Step 10 ns

teEnable Time From Disable = Rising Edge 10 ns

tdDisable Time From Disable = Falling Edge 15 ns

Distortion

HD2L 2nd Harmonic Distortion 2 VPP, 10 MHz −72 dBc

HD3L 3rd Harmonic Distortion 2 VPP, 10 MHz −63 dBc

Equivalent Input Noise

VN Non-Inverting Voltage >10 MHz 2.1 nV/

ICN Inverting Current >10 MHz 18.6 pA/

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LMH6733

Symbol Parameter Conditions Min Typ Max Units

NCN Non-Inverting Current >10 MHz 26.9 pA/

Video Performance

DG Differential Gain 4.43 MHz, RL = 150Ω 0.03 %

DP Differential Phase 4.43 MHz, RL = 150Ω 0.03 Deg

Static, DC Performance

VIO Input Offset Voltage (Note 7) 0.6 2.2

2.5 mV

IBN Input Bias Current (Note 7) Non-Inverting −14

−19

3.5 19

24 µA

IBI Input Bias Current (Note 7) Inverting 5 23

26 μA

PSRR Power Supply Rejection Ratio

(Note 7)

+PSRR 59 61.5 dB

−PSRR 58 61

CMRR Common Mode Rejection Ratio

(Note 7)

52.5

55 dB

XTLK Crosstalk Input Referred, f = 10 MHz, Drive

Channels A,C Measure Channel B

−80 dB

ICC Supply Current (Note 7) All Three Amps Enabled, No Load 19.5 20.8

22.0 mA

Supply Current Disabled V+RL = ∞ 1.54 1.8 mA

Supply Current Disabled V−RL = ∞ 0.75 1.8 mA

Miscellaneous Performance

RIN+ Non-Inverting Input Resistance 200 kΩ

CIN+ Non-Inverting Input Capacitance 1 pF

RIN− Inverting Input Impedance Output Impedance of Input Buffer 30 Ω

ROOutput Impedance DC 0.05 Ω

VOOutput Voltage Range (Note 7)RL = 100Ω ±3.55

±3.5 ±3.7

RL = ∞±3.85 ±4.0

CMIR Common Mode Input Range

(Note 7)

CMRR > 43 dB ±3.9

±3.8

±4.0 V

IOLinear Output Current

(Note 3, Note 7)

VIN = 0V, VOUT < ±42 mV 70 ±80 mA

ISC Short Circuit Current (Note 6) VIN = 2V Output Shorted to Ground 237 mA

IIH Disable Pin Bias Current High Disable Pin = V+ −72 μA

IIL Disable Pin Bias Current Low Disable Pin = 0V −360 μA

VDMAX Voltage for Disable Disable Pin ≤ VDMAX 3.2 V

VDMIM Voltage for Enable Disable Pin ≥ VDMIN 3.6 V

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

intended to be functional, but specific performance is not guaranteed. For guaranteed specifications, see the Electrical Characteristics tables.

Note 2: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC)

Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).

Note 3: The maximum output current (IOUT) is determined by device power dissipation limitations. See the Power Dissipation section of the Applications Information

for more details.

Note 4: The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is

PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.

Note 5: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating

of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where

TJ > TA.

Note 6: Short circuit current should be limited in duration to no more than 10 seconds. See the Power Dissipation section of the Application Section for more

details.

Note 7: Parameter 100% production tested at 25° C.

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LMH6733

Typical Performance Characteristics AV = +2, VCC = 5V, RL = 100Ω, RF = 340Ω; unless otherwise

specified).

Large Signal Frequency Response

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Large Signal Frequency Response

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Small Signal Frequency Response

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Frequency Response vs. VOUT

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Frequency Response vs. Supply Voltage

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Gain Flatness

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LMH6733

Pulse Response

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Crosstalk vs. Frequency

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Distortion vs. Frequency

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Distortion vs. Output Voltage

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Small Signal Frequency Response vs. RL

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Frequency Response vs. Capacitive Load

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LMH6733

Series Output Resistance vs. Capacitive Load

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PSRR vs. Frequency

20199138

CMRR vs. Frequency

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Closed Loop Output Impedance |Z|

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Disabled Channel Isolation vs. Frequency

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Disable Timing

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LMH6733

DC Errors vs. Temperature

20199143

Open Loop Transimpedance

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Input Noise vs. Frequency

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LMH6733

Typical Performance Characteristics AV = +2, VCC = ±5V, RL = 100Ω, RF = 383Ω; unless otherwise

specified).

Large Signal Frequency Response

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Large Signal Frequency Response

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Small Signal Frequency Response

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Frequency Response vs. VOUT

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Frequency Response vs. Supply Voltage

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Gain Flatness

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LMH6733

Pulse Response

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Crosstalk vs. Frequency

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Distortion vs. Output Voltage

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Distortion vs. Frequency

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DC Errors vs. Temperature

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LMH6733

Application Information

20199105

FIGURE 1. Recommended Non-Inverting Gain Circuit

20199106

FIGURE 2. Recommended Inverting Gain Circuit

GENERAL INFORMATION

The LMH6733 is a high speed current feedback amplifier, op-

timized for very high speed and low distortion. The LMH6733

has no internal ground reference so single or split supply con-

figurations are both equally useful.

FEEDBACK RESISTOR SELECTION

One of the key benefits of a current feedback operational am-

plifier is the ability to maintain optimum frequency response

independent of gain by using the appropriate values for the

feedback resistor (RF). The Electrical Characteristics and

Typical Performance plots specify an RF of 340Ω, a gain of

+2 V/V and ±2.5V power supplies (unless otherwise speci-

fied). Generally, lowering RF from its recommended value will

peak the frequency response and extend the bandwidth while

increasing the value of RF will cause the frequency response

to roll off faster. Reducing the value of RF too far below its

recommended value will cause overshoot, ringing and, even-

tually, oscillation.

20199103

FIGURE 3. Recommended RF vs. Gain

See Figure 3 for selecting a feedback resistor value for gains

of ±1 to ±10. Since each application is slightly different it is

worth some experimentation to find the optimal RF for a given

circuit. In general a value of RF that produces about 0.1 dB of

peaking is the best compromise between stability and maxi-

mal bandwidth. Note that it is not possible to use a current

feedback amplifier with the output shorted directly to the in-

verting input. The buffer configuration of the LMH6733 re-

quires a 324Ω feedback resistor for stable operation.

The LMH6733 has been optimized for high speed operation.

As shown in Figure 3 the suggested value for RF decreases

for higher gains. Due to the impedance of the input buffer

there is a practical limit for how small RF can go, based on the

lowest practical value of RG. This limitation applies to both

inverting and non-inverting configurations. For the LMH6733

the input resistance of the inverting input is approximately

30Ω and 20Ω is a practical (but not hard and fast) lower limit

for RG. The LMH6733 begins to operate in a gain bandwidth

limited fashion in the region where RG is nearly equal to the

input buffer impedance. Note that the amplifier will operate

with RG values well below 20Ω, however results may be sub-

stantially different than predicted from ideal models. In par-

ticular the voltage potential between the inverting and non-

inverting inputs cannot be expected to remain small.

Inverting gain applications that require impedance matched

inputs may limit gain flexibility somewhat (especially if maxi-

mum bandwidth is required). The impedance seen by the

source is RG || RT (RT is optional). The value of RG is RF /gain.

Thus for an inverting gain of −5 V/V and an optimal value for

RF the input impedance is equal to 55Ω. Using a termination

resistor this can be brought down to match a 25Ω source;

however, a 150Ω source cannot be matched. To match a

150Ω source would require using a 1050Ω feedback resistor

and would result in reduced bandwidth.

For more information see Application Note OA-13 which de-

scribes the relationship between RF and closed-loop frequen-

cy response for current feedback operational amplifiers. The

value for the inverting input impedance for the LMH6733 is

approximately 30Ω. The LMH6733 is designed for optimum

performance at gains of +1 to +10 V/V and −1 to −9 V/V.

Higher gain configurations are still useful; however, the band-

width will fall as gain is increased, much like a typical voltage

feedback amplifier.

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LMH6733

ACTIVE FILTER

The choice of reactive components requires much attention

when using any current feedback operational amplifier as an

active filter. Reducing the feedback impedance, especially at

higher frequencies, will almost certainly cause stability prob-

lems. Likewise capacitance on the inverting input should be

avoided. See Application Notes OA-7 and OA-26 for more in-

formation on Active Filter applications for Current Feedback

Op Amps.

When using the LMH6733 as a low pass filter the value of

RF can be substantially reduced from the value recommended

in the RF vs. Gain charts. The benefit of reducing RF is in-

creased gain at higher frequencies, which improves attenua-

tion in the stop band. Stability problems are avoided because

in the stop band additional device bandwidth is used to cancel

the input signal rather than amplify it. The benefit of this

change depends on the particulars of the circuit design. With

a high pass filter configuration reducing RF will likely result in

device instability and is not recommended.

20199107

FIGURE 4. Typical Video Application

20199108

FIGURE 5. Decoupling Capacitive Loads

DRIVING CAPACITIVE LOADS

Capacitive output loading applications will benefit from the

use of a series output resistor ROUT. shows the use of a series

output resistor, ROUT, to stabilize the amplifier output under

capacitive loading. Capacitive loads of 5 to 120 pF are the

most critical, causing ringing, frequency response peaking

and possible oscillation. The chart “Frequency Response vs.

Capacitive Load” give a recommended value for selecting a

series output resistor for mitigating capacitive loads. The val-

ues suggested in the charts are selected for .5 dB or less of

peaking in the frequency response. This gives a good com-

promise between settling time and bandwidth. For applica-

tions where maximum frequency response is needed and

some peaking is tolerable, the value of ROUT can be reduced

slightly from the recommended values.

CAT5 HIGH DEFINITION VIDEO TRANSMISSION

The LMH6733 can be used to send component 1080i High

Definition (HD) video over CAT5 twisted-pairs. As shown Fig-

ure 6 , the LMH6733 can be utilized to perform all three video

transmitter, video receiver, and equalization circuitry. The

equalization circuitry enhances the video signal to accomo-

date for the CAT5 attenuation over various cable lengths.

Refer to application note AN-1822 for more details regarding

this application.

20199152

FIGURE 6. CAT5 High Definition Video Transmission

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LMH6733

20199132

FIGURE 7. AC Coupled Single Supply Video Amplifier

AC-COUPLED VIDEO

The LMH6733 can be used as an AC-coupled single supply

video amplifier for driving 75Ω coax with a gain of 2. The input

signal is nominally 0.7V or 1.0V for component YPRPB and

RGB, depending on the presence of a sync. R1, R2, and R3

simply set the input to the center of the input linear range while

CIN AC couples the video onto the op amp’s input.

As can be seen in , Figure 7 amplifier U1 is used in a positive

gain configuration set for a closed loop gain of 2. The feed-

back resistor RF is 340Ω. The gain resistor is created from the

parallel combination of RG and R4, giving a Thevenin equiv-

alent of 340Ω connected to 2.5V.

The 75Ω back termination resistor RO divides the signal such

that VOUT equals a buffered version of VIN. The back termi-

nation will eliminate any reflection of the signal that comes

from the load. The input termination resistor, RT, is optional –

it is used only if matching of the incoming line is necessary.

In some applications, it is recommended that a small valued

ceramic capacitor be used in parallel with CO which is itself

electrolytic because of its rather large value. The ceramic cap

will tend to shunt the inductive behavior of this electrolytic cap,

CO, at higher frequencies for an improved overall, low-

impedance output.

INVERTING INPUT PARASITIC CAPACITANCE

Parasitic capacitance is any capacitance in a circuit that was

not intentionally added. It comes about from electrical inter-

action between conductors. Parasitic capacitance can be

reduced but never entirely eliminated. Most parasitic capaci-

tances that cause problems are related to board layout or lack

of termination on transmission lines. Please see the section

on Layout Considerations for hints on reducing problems due

to parasitic capacitances on board traces. Transmission lines

should be terminated in their characteristic impedance at both

ends.

High speed amplifiers are sensitive to capacitance between

the inverting input and ground or power supplies. This shows

up as gain peaking at high frequency. The capacitor raises

device gain at high frequencies by making RG appear smaller.

Capacitive output loading will exaggerate this effect. In gen-

eral, avoid introducing unnecessary parasitic capacitance at

both the inverting input and the output.

One possible remedy for this effect is to slightly increase the

value of the feedback (and gain set) resistor. This will tend to

offset the high frequency gain peaking while leaving other

parameters relatively unchanged. If the device has a capaci-

tive load as well as inverting input capacitance using a series

output resistor as described in the section on “Driving Capac-

itive Loads” will help.

LAYOUT CONSIDERATIONS

Whenever questions about layout arise, use the evaluation

board as a guide. The LMH730275 is the evaluation board

supplied with samples of the LMH6733.

To reduce parasitic capacitances ground and power planes

should be removed near the input and output pins. Compo-

nents in the feedback loop should be placed as close to the

device as possible. For long signal paths controlled

impedance lines should be used, along with impedance

matching elements at both ends.

Bypass capacitors should be placed as close to the device as

possible. Bypass capacitors from each rail to ground are ap-

plied in pairs. The larger electrolytic bypass capacitors can be

located farther from the device, the smaller ceramic capaci-

tors should be placed as close to the device as possible. The

LMH6733 has multiple power and ground pins for enhanced

supply bypassing. Every pin should ideally have a separate

bypass capacitor. Sharing bypass capacitors may slightly de-

grade second order harmonic performance, especially if the

supply traces are thin and /or long. In Figure 1 and Figure 2

CSS is optional, but is recommended for best second harmon-

ic distortion. Another option to using CSS is to use pairs of .01

μF and .1 μF ceramic capacitors for each supply bypass.

VIDEO PERFORMANCE

The LMH6733 has been designed to provide excellent per-

formance with production quality video signals in a wide va-

riety of formats such as HDTV and High Resolution VGA.

NTSC and PAL performance is nearly flawless. Best perfor-

mance will be obtained with back terminated loads. The back

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LMH6733

termination reduces reflections from the transmission line and

effectively masks transmission line and other parasitic ca-

pacitances from the amplifier output stage. Figure 4 shows a

typical configuration for driving a 75Ω cable. The amplifier is

configured for a gain of two to make up for the 6 dB of loss in

ROUT.

20199102

FIGURE 8. Maximum Power Dissipation

POWER DISSIPATION

The LMH6733 is optimized for maximum speed and perfor-

mance in the small form factor of the standard SSOP-16

package. To achieve its high level of performance, the

LMH6733 consumes an appreciable amount of quiescent

current which cannot be neglected when considering the total

package power dissipation limit. The quiescent current con-

tributes to about 40° C rise in junction temperature when no

additional heat sink is used (VS = ±5V, all 3 channels on).

Therefore, it is easy to see that proper precautions need to

be taken in order to make sure the junction temperature’s ab-

solute maximum rating of 150°C is not violated.

To ensure maximum output drive and highest performance,

thermal shutdown is not provided. Therefore, it is of utmost

importance to make sure that the TJMAX is never exceeded

due to the overall power dissipation (all 3 channels).

With the LMH6733 used in a back-terminated 75Ω RGB ana-

log video system (with 2 VPP output voltage), the total power

dissipation is around 305 mW of which 220 mW is due to the

quiescent device dissipation (output black level at 0V). With

no additional heat sink used, that puts the junction tempera-

ture to about 120° C when operated at 85°C ambient.

To reduce the junction temperature many options are avail-

able. Forced air cooling is the easiest option. An external add-

on heat-sink can be added to the SSOP-16 package, or

alternatively, additional board metal (copper) area can be uti-

lized as heat-sink.

An effective way to reduce the junction temperature for the

SSOP-16 package (and other plastic packages) is to use the

copper board area to conduct heat. With no enhancement the

major heat flow path in this package is from the die through

the metal lead frame (inside the package) and onto the sur-

rounding copper through the interconnecting leads. Since

high frequency performance requires limited metal near the

device pins the best way to use board copper to remove heat

is through the bottom of the package. A gap filler with high

thermal conductivity can be used to conduct heat from the

bottom of the package to copper on the circuit board. Vias to

a ground or power plane on the back side of the circuit board

will provide additional heat dissipation. A combination of front

side copper and vias to the back side can be combined as

well.

Follow these steps to determine the maximum power dissi-

pation for the LMH6733:

1. Calculate the quiescent (no-load) power: PAMP = ICC X

(VS), where VS = V+-V−

2. Calculate the RMS power dissipated in the output stage:

PD (rms) = rms ((VS - VOUT) X IOUT) where VOUT and

IOUT are the voltage and the current across the external

load and VS is the total supply voltage

3. Calculate the total RMS power: PT = PAMP+PD

The maximum power that the LMH6733, package can dissi-

pate at a given temperature can be derived with the following

equation (See Figure 8):

PMAX = (150°C/W– TAMB)/ θJA, where TAMB = ambient tem-

perature (°C) and θJA = thermal resistance, from junction to

ambient, for a given package (°C/W). For the SSOP package

θJA is 120°C/W.

ESD PROTECTION

The LMH6733 is protected against electrostatic discharge

(ESD) on all pins. The LMH6733 will survive 2000V Human

Body Model and 200V Machine Model events.

Under closed loop operation the ESD diodes have no affect

on circuit performance. There are occasions, however, when

the ESD diodes will be evident. If the LMH6733 is driven by

a large signal while the device is powered down the ESD

diodes will conduct.

The current that flows through the ESD diodes will either exit

the chip through the supply pins or will flow through the de-

vice, hence it is possible to power up a chip with a large signal

applied to the input pins. Shorting the power pins to each other

will prevent the chip from being powered up through the input.

EVALUATION BOARDS

National Semiconductor provides the following evaluation

boards as a guide for high frequency layout and as an aid in

device testing and characterization. Many of the datasheet

plots were measured with these boards.

Device Package Evaluation Board

Part Number

LMH6733MQ SSOP LMH730275

A bare evaluation board can be ordered when a sample re-

quest is placed with National Semiconductor.

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LMH6733

Physical Dimensions inches (millimeters) unless otherwise noted

16-Pin SSOP

NS Package Number MQA16

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LMH6733

Notes

LMH6733 Single Supply, 1.0 GHz, Triple Operational Amplifier

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