v4.0.1 ACTTM 2 Family FPGAs Fe a t ur es * Datapath Performance at 105 MHz * Up to 8000 Gate Array Gates (20,000 PLD equivalent gates) * 16-Bit Accumulator Performance to 39 MHz * Replaces up to 200 TTL Packages * Replaces up to eighty 20-Pin PAL * Two In-Circuit Diagnostic Probe Pins Support Speed Analysis to 50 MHz * Design Library with over 500 Macro Functions * Two High-Speed, Low-Skew Clock Networks * Single-Module Sequential Functions * I/O Drive to 10 mA * Wide-Input Combinatorial Functions * Nonvolatile, User Programmable * Up to 1232 Programmable Logic Modules * Logic Fully Tested Prior to Shipment * Up to 998 Flip-Flops * 1.0-micron CMOS Technology (R) Packages Pr od uc t F am i l y P r o f i l e Device A1225A A1240A A1280A Capacity Gate Array Equivalent Gates PLD Equivalent Gates TTL Equivalent Packages 20-Pin PAL Equivalent Packages 2,500 6,250 63 25 4,000 10,000 100 40 8,000 20,000 200 80 Logic Modules S-Modules C-Modules 451 231 220 684 348 336 1,232 624 608 Flip-Flops (maximum) 382 568 998 Routing Resources Horizontal Tracks/Channel Vertical Tracks/Channel PLICE Antifuse Elements 36 15 250,000 36 15 400,000 36 15 750,000 User I/Os (maximum) 83 104 140 100 CPGA 100 PQFP 100 VQFP 84 PLCC 132 CPGA 144 PQFP 176 TQFP 84 PLCC 176 CPGA 160 PQFP 176 TQFP 84 PLCC 172 CQFP 105 MHz 70 MHz 39 MHz 100 MHz 69 MHz 38 MHz 85 MHz 67 MHz 36 MHz 1 Packages Performance2 16-Bit Prescaled Counters 16-Bit Loadable Counters 16-Bit Accumulators Notes: 1. See the "Product Plan" on page 3 for package availability. 2. Performance is based on `-2' speed devices at commercial worst-case operating conditions using PREP Benchmarks, Suite #1, Version 1.2, dated 3-28-93, any analysis is not endorsed by PREP. D e ce m b e r 2 0 0 0 (c) 2000 Actel Corporation 1 A C T TM 2 F a m il y F P GA s D es cr i p t i o n technology. This revolutionary architecture offers gate array design flexibility, high performance, and fast The ACTTM 2 family represents Actel's second generation of field programmable gate arrays (FPGAs). The ACT 2 family presents a two-module architecture, consisting of C-modules and S-modules. These modules are optimized for both combinatorial and sequential designs. Based on Actel's patented channeled array architecture, the ACT 2 family provides significant enhancements to gate density and performance while maintaining downward compatibility with the ACT 1 design environment and upward compatibility with the ACT 3 design environment. The devices are implemented in silicon gate, 1.0-m, two-level metal CMOS, and employ Actel's PLICE(R) antifuse time-to-production with user programming. The ACT 2 family is supported by the Designer and Designer Advantage Systems, which offers automatic pin assignment, validation of electrical and design rules, automatic placement and routing, timing analysis, user programming, and diagnostic probe capabilities. The systems are supported on the following platforms: 386/486TM PC, SunTM, and HPTM workstations. The systems provide CAE interfaces to the following design environments: Cadence, Viewlogic(R), Mentor Graphics(R), and OrCADTM. O r d e r i n g I nf o r m a t i o n A1280 A - 1 PG 176 C Application (Temperature Range) C = Commercial (0 to +70C) I = Industrial (-40 to +85C) M = Military (-55 to +125C) B = MIL-STD-883 Package Lead Count Package Type PL = Plastic J-Leaded Chip Carrier PQ = Plastic Quad Flat Pack CQ = Ceramic Quad Flat Pack PG = Ceramic Pin Grid Array TQ = Thin (1.4 mm) Quad Flat Pack VQ = Very Thin (1.0 mm) Quad Flat Pack Speed Grade Blank = Standard Speed -1 = Approximately 15% faster than Standard -2 = Approximately 25% faster than Standard Die Revision A = 1.0-m CMOS process Part Number A1225 = 2500 Gates A1240 = 4000 Gates A1280 = 8000 Gates 2 v4.0 A C T TM 2 F a m il y F PG A s Pr od uc t P l a n Speed Grade* Application Std -1 -2 C I M B A1225A Device -- -- -- 100-pin Plastic Quad Flat Pack (PQ) 100-pin Very Thin (1.0 mm) Quad Flat Pack (VQ) -- -- -- -- -- -- -- -- -- -- -- -- 100-pin Ceramic Pin Grid Array (PG) 84-pin Plastic Leaded Chip Carrier (PL) A1240A Device 132-pin Ceramic Pin Grid Array (PG) 176-pin Thin (1.4 mm) Quad Flat Pack (TQ) 144-pin Plastic Quad Flat Pack (PQ) 84-pin Plastic Leaded Chip Carrier (PL) -- -- -- -- -- -- -- -- -- -- A1280A Device 176-pin Ceramic Pin Grid Array (PG) 176-pin Thin (1.4 mm) Quad Flat Pack (TQ) 160-pin Plastic Quad Flat Pack (PQ) 172-pin Ceramic Quad Flat Pack (CQ) Contact your Actel sales representatives for product availability. Applications: C = Commercial Availability: = Available *Speed Grade: I = Industrial P = Planned M = Military -- = Not Planned B = MIL-STD-883 -1 = Approx. 15% faster than Standard -2 = Approx. 25% faster than Standard D ev i ce R es ou r c es User I/Os Device Series CPGA PQFP PLCC CQFP TQFP VQFP Logic Modules Gates 176-pin 132-pin 100-pin 160-pin 144-pin 100-pin 84-pin 172-pin 176-pin 100-pin A1225A 451 2500 -- -- 83 -- -- 83 72 -- -- 83 A1240A 684 4000 -- 104 -- -- 104 -- 72 -- 104 -- A1280A 1232 8000 140 -- -- 125 -- -- 72 140 140 -- . v4.0 3 A C T TM 2 F a m il y F P GA s O pe r a t i ng C on d i t i on s Abs ol ut e M axim u m Ra ti ngs 1 R ecom m en ded Oper at ing C ondi ti ons Free air temperature range Symbol VCC Parameter DC Supply Voltage Limits Units -0.5 to +7.0 V VI Input Voltage -0.5 to VCC +0.5 V VO Output Voltage -0.5 to VCC +0.5 V IIO I/O Source/Sink Current2 20 mA TSTG Storage Temperature -65 to +150 Parameter Temperature Range1 Commercia Industria l l Military Units 0 to +70 -40 to +85 -55 to +125 C 5 10 10 %VCC Power Supply Tolerance Note: 1. Ambient temperature (TA) is used for commercial and industrial; case temperature (TC) is used for military. C Notes: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Device should not be operated outside the Recommended Operating Conditions. 2. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater than VCC + 0.5 V or less than GND - 0.5 V, the internal protection diode will be forward biased and can draw excessive current. E lect r ica l Sp eci ficat i ons Commercial Symbol Parameter VOH1 Min. Max. Max. 3.84 V 3.7 2 VIH Input Transition Time tR, tF 3.7 V 0.5 V 0.33 0.40 0.40 V -0.3 0.8 -0.3 0.8 -0.3 0.8 V 2.0 VCC + 0.3 2.0 VCC + 0.3 2.0 VCC + 0.3 V 2 500 500 500 ns 2, 3 10 10 10 pF 4 2 10 20 mA 10 A Standby Current, ICC (typical = 1 mA) -10 10 -10 10 -10 Notes: 1. Only one output tested at a time. VCC = min. 2. Not tested, for information only. 3. Includes worst-case 176 CPGA package capacitance. VOUT = 0 V, f = 1 MHz. 4. All outputs unloaded. All inputs = VCC or GND, typical ICC = 1 mA. ICC limit includes IPP and ISV during normal operation. 5. VOUT , VIN = VCC or GND. 4 Units (IOH = -6 mA) VIL Leakage Current Min. V (IOL = 6 mA) 5 Max. 2.4 (IOL = 10 mA) CIO I/O Capacitance Min. Military (IOH = -10 mA) 2 (IOH = -4 mA) VOL1 Industrial v4.0 A C T TM 2 F a m il y F PG A s Pa c ka ge T he r m a l C ha r a ct e r i s t i c s Maximum junction temperature is 150C. The device junction to case thermal characteristic is jc, and the junction to ambient air characteristic is ja. The thermal characteristics for ja are shown with two different air flow rates. A sample calculation of the absolute maximum power dissipation allowed for a PQFP 160-pin package at commercial temperature is as follows: Max. junction temp. (C) - Max. commercial temp.150C - 70C ---------------------------------------------------------------------------------------------------------------------------= --------------------------------- = 2.4 W ja (C/W) 33C/W Pin Count jc ja Still Air ja 300 ft/min Units Ceramic Pin Grid Array 100 132 176 5 5 8 35 30 23 17 15 12 C/W C/W C/W Ceramic Quad Flat Pack 172 8 25 15 C/W 100 144 160 13 15 15 48 40 38 40 32 30 C/W C/W C/W 84 12 37 28 C/W 100 12 43 35 C/W 176 15 32 25 C/W Package Type 1 Plastic Quad Flat Pack Plastic Leaded Chip Carrier2 Very Thin Quad Flat Pack Thin Quad Flat Pack 3 4 Notes:(Maximum Power in Still Air) 1. Maximum Power Dissipation for PQFP packages are 1.9 Watts (100-pin), 2.3 Watts (144-pin), and 2.4 Watts (160-pin). 2. Maximum Power Dissipation for PLCC packages is 2.7 Watts. 3. Maximum Power Dissipation for VQFP packages is 2.3 Watts. 4. Maximum Power Dissipation for TQFP packages is 3.1 Watts. Po w e r D i ss i pa t i o n P = [ICCstandby + ICCactive] * VCC + IOL * VOL * N + IOH * (VCC - VOH) * M Where: ICC standby is the current flowing when no inputs or outputs are changing. greater reduction in board-level power dissipation can be achieved. The power due to standby current is typically a small component of the overall power. Standby power is calculated below for commercial, worst case conditions. ICC VCC Power ICC active is the current flowing due to CMOS switching. 2 mA 5.25V 10.5 mW IOL, IOH are TTL sink/source currents. The static power dissipated by TTL loads depends on the number of outputs driving high or low and the DC load current. Again, this value is typically small. For instance, a 32-bit bus sinking 4 mA at 0.33 V will generate 42 mW with all outputs driving low, and 140 mW with all outputs driving high. The actual dissipation will average somewhere between as I/Os switch states with time. VOL, VOH are TTL level output voltages. N equals the number of outputs driving TTL loads to VOL. M equals the number of outputs driving TTL loads to VOH. An accurate determination of N and M is problematical because their values depend on the family type, design details, and on the system I/O. The power can be divided into two components: static and active. S tat i c P ow er Co m ponen t Actel FPGAs have small static power components that result in lower power dissipation than PALs or PLDs. By integrating multiple PALs/PLDs into one FPGA, an even Ac ti ve P ower Com po nent Power dissipation in CMOS devices is usually dominated by the active (dynamic) power dissipation. This component is frequency dependent, a function of the logic and the external I/O. Active power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module inputs, and module outputs, plus external capacitance due to PC board traces v4.0 5 A C T TM 2 F a m il y F P GA s and load device inputs. An additional component of the active power dissipation is the totem-pole current in CMOS transistor pairs. The net effect can be associated with an equivalent capacitance that can be combined with frequency and voltage to represent active power dissipation. r2 = Fixed capacitance due to second routed array clock CEQM = Equivalent capacitance of logic modules in pF CEQI = Equivalent capacitance of input buffers in pF E quiv al ent C apac it ance CEQO = Equivalent capacitance of output buffers in pF The power dissipated by a CMOS circuit can be expressed by the Equation 1. CEQCR = Equivalent capacitance of routed array clock in pF Power (W) = CEQ * VCC2 * F CL = Output lead capacitance in pF Where: fm = Average logic module switching rate in MHz CEQ is the equivalent capacitance expressed in pF. fn = Average input buffer switching rate in MHz VCC is the power supply in volts. fp = Average output buffer switching rate in MHz F is the switching frequency in MHz. fq1 = Average first routed array clock rate in MHz Equivalent capacitance is calculated by measuring ICC active at a specified frequency and voltage for each circuit component of interest. Measurements have been made over a range of frequencies at a fixed value of VCC. Equivalent capacitance is frequency independent so that the results may be used over a wide range of operating conditions. Equivalent capacitance values are shown below. fq2 = Average second routed array clock rate in MHz (1) C E Q Va lues f or Ac tel F PG A s Modules (CEQM) 5.8 Input Buffers (CEQI) 12.9 Output Buffers (CEQO) 23.8 Routed Array Clock Buffer Loads (CEQCR) 3.9 To calculate the active power dissipated from the complete design, the switching frequency of each part of the logic must be known. Equation 2 shows a piece-wise linear summation over all components. Fi xed Ca paci ta nce Val ues fo r Act el FP GA s (pF ) Device Type r1 routed_Clk1 r2 routed_Clk2 A1225A A1240A A1280A 106 134 168 106.0 134.2 167.8 D et erm i nin g A ve ra ge S wi t chi ng F re quenc y To determine the switching frequency for a design, you must have a detailed understanding of the data input values to the circuit. The following guidelines are meant to represent worst-case scenarios so that they can be generally used to predict the upper limits of power dissipation. These guidelines are as follows: Power = VCC2 * [(m * CEQM* fm)modules +(n * CEQI* fn)inputs + (p * (CEQO+ CL) * fp)outputs + 0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 * fq1)routed_Clk1 + 0.5 * (q2 * CEQCR * fq2)routed_Clk2 (2) + (r2 * fq2)routed_Clk2] Where: Logic Modules (m) 80% of modules Inputs switching (n) # inputs/4 Outputs switching (p) # outputs/4 First routed array clock loads (q1) 40%of sequential modules Second routed array clock loads (q2) 40%of sequential modules m = Number of logic modules switching at fm n = Number of input buffers switching at fn Load capacitance (CL) 35 pF p = Number of output buffers switching at fp Average logic module switching rate (fm) F/10 q1 = Number of clock loads on the first routed array clock Average input switching rate (fn) F/5 Average output switching rate (fp) F/10 q2 = Number of clock loads on the second routed array clock Average first routed array clock rate (fq1) F r1 = Fixed capacitance due to first routed array clock 6 Average second routed array clock rate F/2 (fq2) v4.0 A C T TM 2 F a m il y F PG A s A CT 2 Ti m i n g M od el * Input Delays Internal Delays Predicted Routing Delays Combinatorial I/O Module Logic Module tINYL = 2.6 ns t IRD2 = 4.8 ns Output Delays I/O Module tDLH = 8.0 ns D Q tRD1 = 1.4 ns tRD2 = 1.7 ns tRD4 = 3.1 ns tRD8 = 4.7 ns tPD = 3.8 ns G Sequential Logic Module tINH = 2.0 ns tINSU = 4.0 ns tINGL = 4.7 ns Combinatorial Logic included in tSUD ARRAY CLOCKS tCKH = 11.8 ns FO = 256 D I/O Module tDLH = 8.0 ns D Q Q tRD1 = 1.4 ns tENHZ = 7.1 ns G tSUD = 0.4 ns tHD = 0.0 ns tCO = 3.8 ns tOUTH = 0.0 ns tOUTSU = 0.4 ns tGLH = 9.0 ns FMAX = 100 MHz *Values shown for A1240A-2 at worst-case commercial conditions. Input Module Predicted Routing Delay v4.0 7 A C T TM 2 F a m il y F P GA s P ar am e t e r M ea s ur e m e nt O ut put Buf f e r De lay s E D VCC In 50% PAD VOL GND 50% VOH E 1.5 V 1.5 V TRIBUFF PAD To AC test loads (shown below) VCC VCC 50% VCC 50% GND 1.5 V PAD E PAD GND 10% VOL tDLH tENZL tDHL tENLZ GND 50% VOH 50% 90% 1.5 V tENZH tENHZ A C T es t Lo ads Load 1 (Used to measure propagation delay) Load 2 (Used to measure rising/falling edges) VCC GND To the output under test 50 pF R to VCC for tPLZ/tPZL R to GND for tPHZ/tPZH R = 1 k To the output under test 50 pF Inp ut Bu ffer D ela ys PAD Modu le Del ay s S A B Y INBUF Y VCC S, A or B 50% 50% VCC Y GND 50% 3V PAD 1.5 V 1.5 V VCC Y GND 50% 50% tINYH 8 0V tPLH GND 50% tPHL VCC Y 50% tPHL tINYL v4.0 GND tPLH 50% A C T TM 2 F a m il y F PG A s S eq u en t i a l M od ul e T i m i ng C ha r a ct er i st i c s Fl ip- Fl ops and La tch es D E CLK Y PRE CLR (Positive edge triggered) tHD D1 tSUD tA tWCLKA G, CLK tSUENA tWCLKI tHENA E tCO Q tRS PRE, CLR tWASYN Note: D represents all data functions involving A, B, and S for multiplexed flip-flops. v4.0 9 A C T TM 2 F a m il y F P GA s Se q ue nt i al T i m i n g C h ar ac t er i st i c s (continued) Inpu t Buffe r Lat che s PAD DATA IBDL G PAD CLK CLKBUF DATA tINH G tINSU tHEXT CLK tSUEXT Out put B uffer L at ches D PAD OBDLHS G D tOUTSU G tOUTH 10 v4.0 A C T TM 2 F a m il y F PG A s Ti m i n g D er a t i n g F a ct o r ( T e m p e r a t u r e a n d V o l t a g e ) Industrial (Commercial Minimum/Maximum Specification) x Military Min. Max. Min. Max. 0.69 1.11 0.67 1.23 Ti m i ng D er a t i n g F a ct o r f o r D e si g ns at Ty pi c a l Te m p er a t u r e ( T J = 25 C ) an d V ol t a g e ( 5 . 0 V) (Commercial Maximum Specification) x 0.85 Te m p er a t u r e an d Vo l t a ge D er at i n g Fa ct or s ( n or m a l i z ed t o W or s t - C a se Co m m e r c i al , T J = 4 . 7 5 V , 7 0 C ) -55 -40 0 25 70 85 125 4.50 0.75 0.79 0.86 0.92 1.06 1.11 1.23 4.75 0.71 0.75 0.82 0.87 1.00 1.05 1.16 5.00 0.69 0.72 0.80 0.85 0.97 1.02 1.13 5.25 0.68 0.69 0.77 0.82 0.95 0.98 1.09 5.50 0.67 0.69 0.76 0.81 0.93 0.97 1.08 Junction Temperature and Voltage Derating Curves (normalized to Worst-Case Commercial, T J = 4.75V, 70C) 1.3 Derating Factor 1.2 1.1 125C 1.0 85C 70C 0.9 25C 0.8 0C -40C -55C 0.7 0.6 4.50 4.75 5.00 5.25 5.50 Voltage (V) Note: This derating factor applies to all routing and propagation delays. v4.0 11 A C T TM 2 F a m il y F P GA s A 12 25 A Ti m i ng Ch a r ac t e r i s t i cs (Worst-Case Commercial Conditions, V CC = 4.75 V, T J = 70C) Logic Module Propagation Delays1 `-2' Speed Parameter Description Max. tPD1 Single Module 3.8 tCO Sequential Clk to Q tGO tRS Min. Max. `Std' Speed Max. Units 4.3 5.0 ns 3.8 4.3 5.0 ns Latch G to Q 3.8 4.3 5.0 ns Flip-Flop (Latch) Reset to Q 3.8 4.3 5.0 ns Predicted Routing Delays Min. `-1' Speed Min. 2 tRD1 FO=1 Routing Delay 1.1 1.2 1.4 ns tRD2 FO=2 Routing Delay 1.7 1.9 2.2 ns tRD3 FO=3 Routing Delay 2.3 2.6 3.0 ns tRD4 FO=4 Routing Delay 2.8 3.1 3.7 ns tRD8 FO=8 Routing Delay 4.4 4.9 5.8 ns Sequential Timing Characteristics 3,4 tSUD Flip-Flop (Latch) Data Input Setup 0.4 0.4 0.5 ns tHD Flip-Flop (Latch) Data Input Hold 0.0 0.0 0.0 ns tSUENA Flip-Flop (Latch) Enable Setup 0.8 0.9 1.0 ns tHENA Flip-Flop (Latch) Enable Hold 0.0 0.0 0.0 ns tWCLKA Flip-Flop (Latch) Clock Active Pulse Width 4.5 5.0 6.0 ns tWASYN Flip-Flop (Latch) Asynchronous Pulse Width 4.5 5.0 6.0 ns tA Flip-Flop Clock Input Period 9.4 11.0 13.0 ns tINH Input Buffer Latch Hold 0.0 0.0 0.0 ns tINSU Input Buffer Latch Setup 0.4 0.4 0.5 ns tOUTH Output Buffer Latch Hold 0.0 0.0 0.0 ns tOUTSU Output Buffer Latch Setup 0.4 0.4 0.5 ns fMAX Flip-Flop (Latch) Clock Frequency 105.0 90.0 75.0 MHz Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the DirectTime Analyzer utility. 4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 12 v4.0 A C T TM 2 F a m il y F PG A s A 12 25 A Ti m i ng Ch a r ac t e r i s t i cs (continued) ( W or st -C as e C om m er cia l Cond it ion s) Input Module Propagation Delays `-2' Speed `Std' Speed Max. Unit s 3.3 3.8 ns 2.6 3.0 3.5 ns 5.0 5.7 6.6 ns 4.7 5.4 6.3 ns Parameter Description tINYH Pad to Y High 2.9 tINYL Pad to Y Low tINGH G to Y High tINGL G to Y Low Input Module Predicted Routing Delays Min. `-1' Speed Max. Min. Max. Min. 1 tIRD1 FO=1 Routing Delay 4.1 4.6 5.4 ns tIRD2 FO=2 Routing Delay 4.6 5.2 6.1 ns tIRD3 FO=3 Routing Delay 5.3 6.0 7.1 ns tIRD4 FO=4 Routing Delay 5.7 6.4 7.6 ns tIRD8 FO=8 Routing Delay 7.4 8.3 9.8 ns Global Clock Network tCKH Input Low to High FO = 32 FO = 256 10.2 11.8 11.0 13.0 12.8 15.7 ns tCKL Input High to Low FO = 32 FO = 256 10.2 12.0 11.0 13.2 12.8 15.9 ns tPWH Minimum Pulse Width High FO = 32 FO = 256 3.4 3.8 4.1 4.5 4.5 5.0 ns tPWL Minimum Pulse Width Low FO = 32 FO = 256 3.4 3.8 4.1 4.5 4.5 5.0 ns tCKSW Maximum Skew FO = 32 FO = 256 tSUEXT Input Latch External Setup FO = 32 FO = 256 0.0 0.0 0.0 0.0 0.0 0.0 ns tHEXT Input Latch External Hold FO = 32 FO = 256 7.0 11.2 7.0 11.2 7.0 11.2 ns tP Minimum Period FO = 32 FO = 256 7.7 8.1 8.3 8.8 9.1 10.0 ns fMAX Maximum Frequency FO = 32 FO = 256 0.7 3.5 130.0 125.0 0.7 3.5 120.0 115.0 0.7 3.5 110.0 100.0 ns MHz Note: 1. These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to 4 ns. Routing delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. v4.0 13 A C T TM 2 F a m il y F P GA s A 12 25 A Ti m i ng Ch a r ac t e r i s t i cs (continued) ( W or st -C as e C om m er cia l Cond it ion s) Output Module Timing Parameter `-2' Speed Description Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. Units TTL Output Module Timing1 tDLH Data to Pad High 8.0 9.0 10.6 ns tDHL Data to Pad Low 10.1 11.4 13.4 ns tENZH Enable Pad Z to High 8.9 10.0 11.8 ns tENZL Enable Pad Z to Low 11.6 13.2 15.5 ns tENHZ Enable Pad High to Z 7.1 8.0 9.4 ns tENLZ Enable Pad Low to Z 8.3 9.5 11.1 ns tGLH G to Pad High 8.9 10.2 11.9 ns tGHL G to Pad Low 11.2 12.7 14.9 ns dTLH Delta Low to High 0.07 0.08 0.09 ns/pF dTHL Delta High to Low 0.12 0.13 0.16 ns/pF CMOS Output Module Timing 1 tDLH Data to Pad High 10.1 11.5 13.5 ns tDHL Data to Pad Low 8.4 9.6 11.2 ns tENZH Enable Pad Z to High 8.9 10.0 11.8 ns tENZL Enable Pad Z to Low 11.6 13.2 15.5 ns tENHZ Enable Pad High to Z 7.1 8.0 9.4 ns tENLZ Enable Pad Low to Z 8.3 9.5 11.1 ns tGLH G to Pad High 8.9 10.2 11.9 ns tGHL G to Pad Low 11.2 12.7 14.9 ns dTLH Delta Low to High 0.12 0.13 0.16 ns/pF dTHL Delta High to Low 0.09 0.10 0.12 ns/pF Note: 1. Delays based on 50 pF loading. 2. SSO information can be found at http://www.actel.com/support/appnotes/appnotes_design.html#board. 14 v4.0 A C T TM 2 F a m il y F PG A s A 12 40 A Ti m i ng Ch a r ac t e r i s t i cs (Worst-Case Commercial Conditions, V CC = 4.75 V, T J = 70C) Logic Module Propagation Delays1 `-2' Speed Parameter Description Max. tPD1 Single Module 3.8 tCO Sequential Clk to Q tGO tRS Min. Max. `Std' Speed Max. Units 4.3 5.0 ns 3.8 4.3 5.0 ns Latch G to Q 3.8 4.3 5.0 ns Flip-Flop (Latch) Reset to Q 3.8 4.3 5.0 ns Predicted Routing Delays Min. `-1' Speed Min. 2 tRD1 FO=1 Routing Delay 1.4 1.5 1.8 ns tRD2 FO=2 Routing Delay 1.7 2.0 2.3 ns tRD3 FO=3 Routing Delay 2.3 2.6 3.0 ns tRD4 FO=4 Routing Delay 3.1 3.5 4.1 ns tRD8 FO=8 Routing Delay 4.7 5.4 6.3 ns Sequential Timing Characteristics 3, 4 tSUD Flip-Flop (Latch) Data Input Setup 0.4 0.4 0.5 ns tHD Flip-Flop (Latch) Data Input Hold 0.0 0.0 0.0 ns tSUENA Flip-Flop (Latch) Enable Setup 0.8 0.9 1.0 ns tHENA Flip-Flop (Latch) Enable Hold 0.0 0.0 0.0 ns tWCLKA Flip-Flop (Latch) Clock Active Pulse Width 4.5 6.0 6.5 ns tWASYN Flip-Flop (Latch) Asynchronous Pulse Width 4.5 6.0 6.5 ns tA Flip-Flop Clock Input Period 9.8 12.0 15.0 ns tINH Input Buffer Latch Hold 0.0 0.0 0.0 ns tINSU Input Buffer Latch Setup 0.4 0.4 0.5 ns tOUTH Output Buffer Latch Hold 0.0 0.0 0.0 ns tOUTSU Output Buffer Latch Setup 0.4 0.4 0.5 ns fMAX Flip-Flop (Latch) Clock Frequency 100.0 80.0 66.0 MHz Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the DirectTime Analyzer utility. 4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. v4.0 15 A C T TM 2 F a m il y F P GA s A 12 40 A Ti m i ng Ch a r ac t e r i s t i cs (continued) ( W or st -C as e C om m er cia l Cond it ion s) Input Module Propagation Delays `-2' Speed Parameter Description tINYH Pad to Y High 2.9 tINYL Pad to Y Low tINGH G to Y High tINGL G to Y Low Input Module Predicted Routing Delays Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. Units 3.3 3.8 ns 2.6 3.0 3.5 ns 5.0 5.7 6.6 ns 4.7 5.4 6.3 ns 1 tIRD1 FO=1 Routing Delay 4.2 4.8 5.6 ns tIRD2 FO=2 Routing Delay 4.8 5.4 6.4 ns tIRD3 FO=3 Routing Delay 5.4 6.1 7.2 ns tIRD4 FO=4 Routing Delay 5.9 6.7 7.9 ns tIRD8 FO=8 Routing Delay 7.9 8.9 10.5 ns Global Clock Network tCKH Input Low to High FO = 32 FO = 256 10.2 11.8 11.0 13.0 12.8 15.7 ns tCKL Input High to Low FO = 32 FO = 256 10.2 12.0 11.0 13.2 12.8 15.9 ns tPWH Minimum Pulse Width High FO = 32 FO = 256 3.8 4.1 4.5 5.0 5.5 5.8 ns tPWL Minimum Pulse Width Low FO = 32 FO = 256 3.8 4.1 4.5 5.0 5.5 5.8 ns tCKSW Maximum Skew FO = 32 FO = 256 tSUEXT Input Latch External Setup FO = 32 FO = 256 0.0 0.0 0.0 0.0 0.0 0.0 ns tHEXT Input Latch External Hold FO = 32 FO = 256 7.0 11.2 7.0 11.2 7.0 11.2 ns tP Minimum Period FO = 32 FO = 256 8.1 8.8 9.1 10.0 11.1 11.7 ns fMAX Maximum Frequency FO = 32 FO = 256 0.5 2.5 125.0 115.0 0.5 2.5 110.0 100.0 0.5 2.5 90.0 85.0 ns MHz Note: These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to 4 ns. Routing delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 16 v4.0 A C T TM 2 F a m il y F PG A s A 12 4 0A T i m i ng C ha r a ct er i s t i c s (continued) ( W or st -C as e C om m er cia l Cond it ion s) Output Module Timing Parameter `-2' Speed Description Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. Units TTL Output Module Timing1 tDLH Data to Pad High 8.0 9.0 10.6 ns tDHL Data to Pad Low 10.1 11.4 13.4 ns tENZH Enable Pad Z to High 8.9 10.0 11.8 ns tENZL Enable Pad Z to Low 11.7 13.2 15.5 ns tENHZ Enable Pad High to Z 7.1 8.0 9.4 ns tENLZ Enable Pad Low to Z 8.4 9.5 11.1 ns tGLH G to Pad High 9.0 10.2 11.9 ns tGHL G to Pad Low 11.2 12.7 14.9 ns dTLH Delta Low to High 0.07 0.08 0.09 ns/pF dTHL Delta High to Low 0.12 0.13 0.16 ns/pF CMOS Output Module Timing 1 tDLH Data to Pad High 10.2 11.5 13.5 ns tDHL Data to Pad Low 8.4 9.6 11.2 ns tENZH Enable Pad Z to High 8.9 10.0 11.8 ns tENZL Enable Pad Z to Low 11.7 13.2 15.5 ns tENHZ Enable Pad High to Z 7.1 8.0 9.4 ns tENLZ Enable Pad Low to Z 8.4 9.5 11.1 ns tGLH G to Pad High 9.0 10.2 11.9 ns tGHL G to Pad Low 11.2 12.7 14.9 ns dTLH Delta Low to High 0.12 0.13 0.16 ns/pF dTHL Delta High to Low 0.09 0.10 0.12 ns/pF Note: 1. Delays based on 50 pF loading. 2. SSO information can be found at http://www.actel.com/support/appnotes/appnotes_design.html#board. v4.0 17 A C T TM 2 F a m il y F P GA s A 12 80 A Ti m i ng Ch a r ac t e r i s t i cs (Worst-Case Commercial Conditions, V CC = 4.75 V, T J = 70C) Logic Module Propagation Delays1 `-2' Speed Parameter Description Max. tPD1 Single Module 3.8 tCO Sequential Clk to Q tGO tRS Min. Max. `Std' Speed Max. Units 4.3 5.0 ns 3.8 4.3 5.0 ns Latch G to Q 3.8 4.3 5.0 ns Flip-Flop (Latch) Reset to Q 3.8 4.3 5.0 ns Predicted Routing Delays Min. `-1' Speed Min. 2 tRD1 FO=1 Routing Delay 1.7 2.0 2.3 ns tRD2 FO=2 Routing Delay 2.5 2.8 3.3 ns tRD3 FO=3 Routing Delay 3.0 3.4 4.0 ns tRD4 FO=4 Routing Delay 3.7 4.2 4.9 ns tRD8 FO=8 Routing Delay 6.7 7.5 8.8 ns Sequential Timing Characteristics 3,4 tSUD Flip-Flop (Latch) Data Input Setup 0.4 0.4 0.5 ns tHD Flip-Flop (Latch) Data Input Hold 0.0 0.0 0.0 ns tSUENA Flip-Flop (Latch) Enable Setup 0.8 0.9 1.0 ns tHENA Flip-Flop (Latch) Enable Hold 0.0 0.0 0.0 ns tWCLKA Flip-Flop (Latch) Clock Active Pulse Width 5.5 6.0 7.0 ns tWASYN Flip-Flop (Latch) Asynchronous Pulse Width 5.5 6.0 7.0 ns tA Flip-Flop Clock Input Period 11.7 13.3 18.0 ns tINH Input Buffer Latch Hold 0.0 0.0 0.0 ns tINSU Input Buffer Latch Setup 0.4 0.4 0.5 ns tOUTH Output Buffer Latch Hold 0.0 0.0 0.0 ns tOUTSU Output Buffer Latch Setup 0.4 0.4 0.5 ns fMAX Flip-Flop (Latch) Clock Frequency 85.0 75.0 50.0 MHz Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the DirectTime Analyzer utility. 4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 18 v4.0 A C T TM 2 F a m il y F PG A s A 12 8 0A T i m i ng C ha r a ct er i s t i c s (continued) ( W or st -C as e C om m er cia l Cond it ion s) Input Module Propagation Delays `-2' Speed Parameter Description tINYH Pad to Y High 2.9 tINYL Pad to Y Low tINGH G to Y High tINGL G to Y Low Input Module Predicted Routing Delays Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. Units 3.3 3.8 ns 2.7 3.0 3.5 ns 5.0 5.7 6.6 ns 4.8 5.4 6.3 ns 1 tIRD1 FO=1 Routing Delay 4.6 5.1 6.0 ns tIRD2 FO=2 Routing Delay 5.2 5.9 6.9 ns tIRD3 FO=3 Routing Delay 5.6 6.3 7.4 ns tIRD4 FO=4 Routing Delay 6.5 7.3 8.6 ns tIRD8 FO=8 Routing Delay 9.4 10.5 12.4 ns Global Clock Network tCKH Input Low to High FO = 32 FO = 384 10.2 13.1 11.0 14.6 12.8 17.2 ns tCKL Input High to Low FO = 32 FO = 384 10.2 13.3 11.0 14.9 12.8 17.5 ns tPWH Minimum Pulse Width High FO = 32 FO = 384 5.0 5.8 5.5 6.4 6.6 7.6 ns tPWL Minimum Pulse Width Low FO = 32 FO = 384 5.0 5.8 5.5 6.4 6.6 7.6 ns tCKSW Maximum Skew FO = 32 FO = 384 tSUEXT Input Latch External Setup FO = 32 FO = 384 0.0 0.0 0.0 0.0 0.0 0.0 ns tHEXT Input Latch External Hold FO = 32 FO = 384 7.0 11.2 7.0 11.2 7.0 11.2 ns tP Minimum Period FO = 32 FO = 384 9.6 10.6 11.2 12.6 13.3 15.3 ns fMAX Maximum Frequency FO = 32 FO = 384 0.5 2.5 105.0 95.0 0.5 2.5 90.0 80.0 0.5 2.5 75.0 65.0 ns MHz Note: These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to 4 ns. Routing delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. v4.0 19 A C T TM 2 F a m il y F P GA s A 12 80 A Ti m i ng Ch a r ac t e r i s t i cs (continued) ( W or st -C as e C om m er cia l Cond it ion s) Output Module Timing `-2' Speed `-1' Speed `Std' Speed Parameter Min. Min. Min. Description Max. Max. Max. Units TTL Output Module Timing1 tDLH Data to Pad High 8.1 9.0 10.6 ns tDHL Data to Pad Low 10.2 11.4 13.4 ns tENZH Enable Pad Z to High 9.0 10.0 11.8 ns tENZL Enable Pad Z to Low 11.8 13.2 15.5 ns tENHZ Enable Pad High to Z 7.1 8.0 9.4 ns tENLZ Enable Pad Low to Z 8.4 9.5 11.1 ns tGLH G to Pad High 9.0 10.2 11.9 ns tGHL G to Pad Low 11.3 12.7 14.9 ns dTLH Delta Low to High 0.07 0.08 0.09 ns/pF dTHL Delta High to Low 0.12 0.13 0.16 ns/pF CMOS Output Module Timing 1 tDLH Data to Pad High 10.3 11.5 13.5 ns tDHL Data to Pad Low 8.5 9.6 11.2 ns tENZH Enable Pad Z to High 9.0 10.0 11.8 ns tENZL Enable Pad Z to Low 11.8 13.2 15.5 ns tENHZ Enable Pad High to Z 7.1 8.0 9.4 ns tENLZ Enable Pad Low to Z 8.4 9.5 11.1 ns tGLH G to Pad High 9.0 10.2 11.9 ns tGHL G to Pad Low 11.3 12.7 14.9 ns dTLH Delta Low to High 0.12 0.13 0.16 ns/pF dTHL Delta High to Low 0.09 0.10 0.12 ns/pF Note: 1. Delays based on 50 pF loading. 2. SSO information can be found at http://www.actel.com/support/appnotes/appnotes_design.html#board. 20 v4.0 A C T TM 2 F a m il y F PG A s Pi n D es c r i pt i on CLKA Clock A (Input) TTL Clock input for clock distribution networks. The Clock input is buffered prior to clocking the logic modules. This pin can also be used as an I/O. CLKB Clock B (Input) TTL Clock input for clock distribution networks. The Clock input is buffered prior to clocking the logic modules. This pin can also be used as an I/O. DCLK Diagnostic Clock (Input) TTL Clock input for diagnostic probe and device programming. DCLK is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. GND Ground LOW supply voltage. I/O Input/Output (Input, Output) The I/O pin functions as an input, output, three-state, or bidirectional buffer. Input and output levels are compatible with standard TTL and CMOS specifications. Unused I/O pins are automatically driven LOW by the ALS software. MODE Mode (Input) The MODE pin controls the use of multifunction pins (DCLK, PRA, PRB, SDI). When the MODE pin is HIGH, the special functions are active. When the MODE pin is LOW, the pins function as I/Os. To provide Actionprobe capability, the MODE pin should be terminated to GND through a 10K resistor so that the MODE pin can be pulled high when required. NC PRA Probe A (Output) The Probe A pin is used to output data from any user-defined design node within the device. This independent diagnostic pin is used in conjunction with the Probe B pin to allow real-time diagnostic output of any signal path within the device. The Probe A pin can be used as a user-defined I/O when debugging has been completed. The pin's probe capabilities can be permanently disabled to protect programmed design confidentiality. PRA is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. PRB Probe B (Output) The Probe B pin is used to output data from any user-defined design node within the device. This independent diagnostic pin is used in conjunction with the Probe A pin to allow real-time diagnostic output of any signal path within the device. The Probe B pin can be used as a user-defined I/O when debugging has been completed. The pin's probe capabilities can be permanently disabled to protect programmed design confidentiality. PRB is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. SDI Serial Data Input (Input) Serial data input for diagnostic probe and device programming. SDI is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. V CC 5.0V Supply Voltage HIGH supply voltage. No Connection This pin is not connected to circuitry within the device. v4.0 21 A C T TM 2 F a m il y F P GA s Pa c ka ge P i n A s si g nm e n t s 84- Pi n PL CC 1 84 84-Pin PLCC Signal A1225A Function A1240A Function A1280A Function 2 CLKB, I/O CLKB, I/O CLKB, I/O 4 PRB, I/O PRB, I/O PRB, I/O 6 GND GND GND 10 DCLK, I/O DCLK, I/O DCLK, I/O 12 MODE MODE MODE 22 VCC VCC VCC 23 VCC VCC VCC 28 GND GND GND Notes: 1. All unlisted pin numbers are user I/Os. 2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND. 22 v4.0 A C T TM 2 F a m il y F PG A s Pa c ka ge P i n A s si g nm e n t s 84- Pi n PL CC 1 84 84-Pin PLCC Signal A1225A Function A1240A Function A1280A Function 43 VCC VCC VCC 49 GND GND GND 63 GND GND GND 64 VCC VCC VCC 65 VCC VCC VCC 70 GND GND GND 76 SDI, I/O SDI, I/O SDI, I/O 81 PRA, I/O PRA, I/O PRA, I/O 83 CLKA, I/O CLKA, I/O CLKA, I/O 84 VCC VCC VCC Notes: 1. All unlisted pin numbers are user I/Os. 2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND. v4.0 23 A C T TM 2 F a m il y F P GA s Pa c ka ge P i n A s si g nm e n t s (cont i nued) 100- P in P Q FP 100-Pin PQFP 100 1 Pin Number A1225A Function Pin Number A1225A Function 2 DCLK, I/O 66 VCC 4 MODE 67 VCC 9 GND 72 GND 16 VCC 79 SDI, I/O 17 VCC 84 GND 22 GND 87 PRA, I/O 34 GND 89 CLKA, I/O 40 VCC 90 VCC 46 GND 92 CLKB, I/O 57 GND 94 PRB, I/O 64 GND 96 GND 65 VCC Notes: 1. All unlisted pin numbers are user I/Os. 2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND. 24 v4.0 A C T TM 2 F a m il y F PG A s Pa c ka ge P i n A s si g nm e n t s (cont i nued) 144- P in P Q FP 1 144 144-Pin PQFP v4.0 25 A C T TM 2 F a m il y F P GA s 144- P in P Q FP Pin Number A1240A Function Pin Number A1240A Function 2 MODE 89 VCC 9 GND 90 VCC 10 GND 91 VCC 11 GND 92 VCC 18 VCC 93 VCC 19 VCC 100 GND 20 VCC 101 GND 21 VCC 102 GND 28 GND 110 SDI, I/O 29 GND 116 GND 30 GND 117 GND 44 GND 118 GND 45 GND 123 PRA, I/O 46 GND 125 CLKA, I/O 54 VCC 126 VCC 55 VCC 127 VCC 56 VCC 128 VCC 64 GND 130 CLKB, I/O 65 GND 132 PRB, I/O 79 GND 136 GND 80 GND 137 GND 81 GND 138 GND 88 GND 144 DCLK, I/O Notes: 1. All unlisted pin numbers are user I/Os. 2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND. 26 v4.0 A C T TM 2 F a m il y F PG A s Pa c ka ge P i n A s si g nm e n t s (cont i nued) 160- P in P Q FP 160 1 160-Pin PQFP v4.0 27 A C T TM 2 F a m il y F P GA s 160- P in P Q FP Pin Number A1280A Function Pin Number A1280A Function 2 DCLK, I/O 69 GND 6 VCC 80 GND 11 GND 86 VCC 16 PRB, I/O 89 GND 18 CLKB, I/O 98 VCC 20 VCC 99 GND 21 CLKA, I/O 109 GND 23 PRA, I/O 114 VCC 30 GND 120 GND 35 VCC 125 GND 38 SDI, I/O 130 GND 40 GND 135 VCC 44 GND 138 VCC 49 GND 139 VCC 54 VCC 140 GND 57 VCC 145 GND 58 VCC 150 VCC 59 GND 155 GND 60 VCC 159 MODE 61 GND 160 GND 64 GND Notes: 1. All unlisted pin numbers are user I/Os. 2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND. 28 v4.0 A C T TM 2 F a m il y F PG A s Pa c ka ge P i n A s si g nm e n t s (cont i nued) 100- P in VQF P 100 1 100-Pin VQFP 100- P in VQF P Pin Number A1225A Function Pin Number A1225A Function 2 MODE 65 VCC 7 GND 70 GND 14 VCC 77 SDI, I/O 15 VCC 82 GND 20 GND 85 PRA, I/O 32 GND 87 CLKA, I/O 38 VCC 88 VCC 44 GND 90 CLKB, I/O 55 GND 92 PRB, I/O 62 GND 94 GND 63 VCC 100 DCLK, I/O 64 VCC Notes: 1. All unlisted pin numbers are user I/Os. 2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND. v4.0 29 A C T TM 2 F a m il y F P GA s Pa c ka ge P i n A s si g nm e n t s (cont i nued) 176- P in T Q FP 176 1 176-Pin TQFP 30 v4.0 A C T TM 2 F a m il y F PG A s 176- P in T Q FP Pin Number A1240A Function A1280A Function 1 GND GND 2 MODE MODE 8 NC 10 NC Pin Number A1240A Function A1280A Function 101 NC NC 103 NC I/O NC 106 GND GND I/O 107 NC I/O 11 NC I/O 108 NC I/O 13 NC VCC 109 GND GND 18 GND GND 110 VCC VCC 19 NC I/O 111 GND GND 20 NC I/O 112 VCC VCC 22 NC I/O 113 VCC VCC 23 GND GND 114 NC I/O 24 NC VCC 115 NC I/O 25 VCC VCC 116 NC VCC 26 NC I/O 121 NC NC 27 NC I/O 124 NC I/O 28 VCC VCC 125 NC I/O 29 NC I/O 126 NC NC 33 NC NC 133 GND GND 37 NC I/O 135 SDI, I/O SDI, I/O 38 NC NC 136 NC I/O 45 GND GND 140 NC VCC 52 NC VCC 143 NC I/O 54 NC I/O 144 NC I/O 55 NC I/O 145 NC NC 57 NC NC 147 NC I/O 61 NC I/O 151 NC I/O 64 NC I/O 152 PRA, I/O PRA, I/O 66 NC I/O 154 CLKA, I/O CLKA, I/O 67 GND GND 155 VCC VCC 68 VCC VCC 156 GND GND 74 NC I/O 158 CLKB, I/O CLKB, I/O 77 NC NC 160 PRB, I/O PRB, I/O 78 NC I/O 161 NC I/O 80 NC I/O 165 NC NC 82 NC VCC 166 NC I/O 86 NC I/O 168 NC I/O 89 GND GND 170 NC VCC 96 NC I/O 173 NC I/O 97 NC I/O 175 DCLK, I/O DCLK, I/O Notes: 1. NC: Denotes No Connection 2. All unlisted pin numbers are user I/Os. 3. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND. v4.0 31 A C T TM 2 F a m il y F P GA s Pa c ka ge P i n A s si g nm e n t s (cont i nued) 172- P in CQF P 172 Pin #1 Index 1 172-Pin CQFP 172-Pin CQFP Pin Number 1 7 12 17 22 23 24 27 32 37 50 55 65 66 75 80 98 103 106 A1280A Function Pin Number MODE GND VCC GND GND VCC VCC VCC GND GND VCC GND GND VCC GND VCC GND GND GND 107 108 109 110 113 118 123 131 136 141 148 150 151 152 154 156 161 166 171 A1280A Function VCC GND VCC VCC VCC GND GND SDI, I/O VCC GND PRA, I/O CLKA, I/O VCC GND CLKB, I/O PRB, I/O GND VCC DCLK, I/O Notes: 1. All unlisted pin numbers are user I/Os. 2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND. 32 v4.0 A C T TM 2 F a m il y F PG A s Pa c ka ge P i n A s si g nm e n t s (cont i nued) 100- P in CP GA 1 2 3 4 5 6 7 8 9 10 11 A A B B C C D D E E 100-Pin CPGA F F G G H H J J K K L L 1 2 3 4 5 6 7 8 9 10 11 Orientation Pin Pin Number A1225A Function Pin Number A1225A Function A4 PRB, I/O E11 VCC A7 PRA, I/O F3 VCC B6 VCC F9 VCC C2 MODE F10 VCC C3 DCLK, I/O F11 GND C5 GND G1 VCC C6 CLKA, I/O G3 GND C7 GND G9 GND C8 SDI, I/O J5 GND D6 CLKB, I/O J7 GND D10 GND K6 VCC E3 GND Note: 1. All unlisted pin numbers are user I/Os. 2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND. v4.0 33 A C T TM 2 F a m il y F P GA s Pa c ka ge P i n A s si g nm e n t s (cont i nued) 132- P in CP GA 1 2 3 4 5 6 7 8 9 10 11 12 13 A A B B C C D D E E F F 132-Pin CPGA G G H H J J K K L L M M N N 1 2 3 4 5 6 7 8 9 10 11 12 13 Orientation Pin Pin Number A1240A Function Pin Number A1240A Function A1 MODE G2 VCC B5 GND G3 VCC B6 CLKB, I/O G4 VCC B7 CLKA, I/O G10 VCC B8 PRA, I/O G11 VCC B9 GND G12 VCC B12 SDI, I/O G13 VCC C3 DCLK, I/O H13 GND C5 GND J2 GND C6 PRB, I/O J3 GND C7 VCC J11 GND C9 GND K7 VCC D7 VCC K12 GND E3 GND L5 GND E11 GND L7 VCC E12 GND L9 GND F4 GND M9 GND Notes: 1. All unlisted pin numbers are user I/Os. 2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND. 34 v4.0 A C T TM 2 F a m il y F PG A s Pa c ka ge P i n A s si g nm e n t s (cont i nued ) 176- P in CP GA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A A B B C C D D E E F F G G 176-Pin CPGA H H J J K K L L M M N N P P R R 1 Pin Number A9 B3 B8 B14 C3 C8 C9 D4 D5 D6 D7 D8 D10 D11 D12 E4 E12 F4 F12 G4 G12 2 3 4 5 6 7 8 A1280A Function 9 10 11 12 13 14 15 Pin Number CLKA, I/O DCLK, I/O CLKB, I/O SDI, I/O MODE GND PRA, I/O GND VCC GND PRB, I/O VCC GND VCC GND GND GND VCC GND GND VCC H2 H3 H4 H12 H13 H14 J4 J12 J13 J14 K4 K12 L4 M4 M5 M6 M8 M10 M11 M12 N8 A1280A Function VCC VCC GND GND VCC VCC VCC GND GND VCC GND GND GND GND VCC GND GND GND VCC GND VCC Notes: 1. All unlisted pin numbers are user I/Os. 2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND. v4.0 35 A C T TM 2 F a m il y F P GA s Li s t o f C ha ng e s The following table lists critical changes that were made in the current version of the document. Previous version unspecified Changes in current version (production (unmarked) v4.0.1-web-only) Page In the 176-Pin CPGA package, pin A3 was incorrectly assigned as CLKA, I/O. A3 is a 35 user I/O. Pin A9 is CLKA, I/O D at a S he et Ca t e g o r i e s In order to provide the latest information to designers, some data sheets are published before data has been fully characterized. These data sheets are marked as "Advanced" or Preliminary" data sheets. The definition of these categories are as follows: Adv anc ed The data sheet contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. P rel im i nar y The data sheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. Unm ar ked (pr odu ct ion) The data sheet contains information that is considered to be final. 36 v4.0 A C T TM 2 F a m il y F PG A s v4.0 37 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. http://www.actel.com Actel Europe Ltd. Daneshill House, Lutyens Close Basingstoke, Hampshire RG24 8AG United Kingdom Tel: +44 (0)1256 305600 Fax: +44 (0)1256 355420 Actel Corporation 955 East Arques Avenue Sunnyvale, California 94086 USA Tel: (408) 739-1010 Fax: (408) 739-1540 Actel Asia-Pacific EXOS Ebisu Bldg. 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Tel: +81 03-3445-7671 Fax: +81 03-3445-7668 5172104-6/12.00