M48T251V-85PM1TR - STMicroelectronics

1/23May 2002

M48T251Y

M48T251V

5.0 or 3.3V, 4096K TIMEKEEPER®SRAM with PHANTOM

FEATURES SUMMARY

■5.0V OR 3.3V OPERATING VOLTAGE

■REAL TIME CLOCK KEEPS TRACK OF

TENTHS/HUNDREDTHS OF SECONDS,

SECONDS, MINUTES, HOURS, DAYS, DATE

OF THE MONTH, MONTHS, and YEARS

■AUTOMATIC LEAP YEAR CORRECTION

VALID UP TO THE YEAR 2100

■AUTOMATIC SWITCH-OVER and DESELECT

CIRCUITRY

■CHOICE OF POWER-FAIL DESELECT

VOLTAGES:

(VPFD = Power-fail Deselect Voltage):

– M48T251Y: 4.25V ≤VPFD ≤4.50V

– M48T251V: 2.80V ≤VPFD ≤2.97V

■FULL 10% VCC OPERATING RANGE

■OVER 10 YEARS’ DATA RETENTION IN THE

ABSENCE OF POWER

■WATCH FUNCTION IS TRANSPARENT TO

RAM OPERATION

■512K x 8 NV SRAM DIRECTLY REPLACES

VOLATILE STATIC RAM OR EEPROM

Figure 1. 32-pin, DIP Package

PMDIP32 (PM)

M48T251Y, M48T251V

2/23

TABLE OF CONTENTS

SUMMARYDESCRIPTION...........................................................3

LogicDiagram(Figure2.).........................................................3

SignalNames(Table1.)..........................................................3

DIP Connections (Figure 3.) .......................................................3

BlockDiagram(Figure4.).........................................................4

MAXIMUMRATING.................................................................5

AbsoluteMaximumRatings(Table2.) ...............................................5

DC AND AC PARAMETERS. . ........................................................6

DC and AC Measurement Conditions (Table 3.). . . .....................................6

AC Testing Load Circuit (Figure 5.)..................................................6

Capacitance (Table 4.) . . . ........................................................6

DCCharacteristics(Table5.) ......................................................7

OPERATIONMODES...............................................................8

Operating Modes (Table 6.)........................................................8

READ.........................................................................8

WRITE........................................................................8

MemoryREADCycle(Figure6.)....................................................8

MemoryWRITECycle1(Figure7.) .................................................9

MemoryWRITECycle2(Figure8.) ................................................10

Memory AC Characteristics, M48T251Y (Table 7.). ....................................11

Memory AC Characteristics, M48T251V (Table 8.). ....................................12

DataRetentionMode............................................................13

PowerDown/UpModeACWaveforms(Figure9.).....................................13

PowerDown/UpTripPointsDCCharacteristics(Table9.)...............................13

PHANTOMCLOCKOPERATION.....................................................14

ComparisonRegisterDefinition(Figure10.)..........................................15

ClockRegisterInformation .......................................................16

ClockAccuracy................................................................16

AM-PM/12/24Mode.............................................................16

Oscillator and Reset Bits. . .......................................................16

ZeroBits.....................................................................16

PhantomClockRegisterMap(Table10.)............................................16

PhantomClockREADCycle(Figure11.)............................................17

PhantomClockWRITECycle(Figure12.)...........................................17

PhantomClockReset(Figure13.) .................................................17

PhantomClockACCharacteristics(M48T251Y)(Table11.).............................18

PhantomClockACCharacteristics(M48T251V)(Table12.).............................19

PARTNUMBERING...............................................................20

PACKAGE MECHANICAL INFORMATION . . . ..........................................21

REVISIONHISTORY...............................................................22

3/23

M48T251Y, M48T251V

SUMMARY DESCRIPTION

The M48T251Y/V TIMEKEEPER®RAM is a

512Kbit x 8 non-volatile static RAM and real time

clock organized as 524,288 words by 8 bits. The

special DIP package provides a fully integrated

battery back-up memory and real time clock solu-

tion. In the event of power instability or absence, a

self-contained battery maintains the timekeeping

operation and provides power for a CMOS static

RAM. Control circuitry monitors VCC and invokes

writeprotectiontopreventdatacorruptioninthe

memory and RTC.

The clock keeps track of tenths/hundredths of sec-

onds, seconds, minutes, hours, day, date, month,

and year information. The last day of the month is

automatically adjusted for months with less than

31 days, including leap year correction.

The clock operates in one of two formats:

– a 12-hour mode with an AM/PM indicator; or

– a 24-hour mode

The M48T251Y/V is a 32-pin (PM) DIP module

that integrates the RTC, the battery, and SRAM in

one package.

The modules are shipped in plastic, anti-static

tubes (see Table 13, page 20).

Figure 2. Logic Diagram Table 1. Signal Names

Figure 3. DIP Connections

A0-A18

VSS

DQ0-D7

M48T251Y

M48T251V

VCC

RST

AI04237

A0–A18 Address Input

RST Reset Input

CE Chip Enable

OE Output Enable Input

WE WRITE Enable Input

DQ0–DQ7 Data Inputs/Outputs

VCC Supply Voltage Input

VSS Ground

VCC

M48T251Y

M48T251V

DQ3

DQ4

DQ5

DQ6

DQ7

A3 OE

A16 A17

16 17

DQ1

DQ2

VSS

DQ0

A10

A11

A13

A15

A14

A12

A18/RST

AI04239

M48T251Y, M48T251V

4/23

Figure 4. Block Diagram

UPDATE

DQ0

VCC

VBAT

DATA

INTERNAL VCC

READ

WRITE

32.768 Hz

CRYSTAL XI

POWER

FAIL

A0–A16

DQ0–DQ7

CLOCK/CALENDAR

LOGIC

TIMEKEEPER

SRAM

CONTROL

LOGIC

ACCESS

ENABLE

SEQUENCE

DETECTOR

COMPARISON

I/O

BUFFERS

POWER-FAIL

DETECT

LOGIC

RST

AI04238

5/23

M48T251Y, M48T251V

MAXIMUM RATING

Stressingthedeviceabovetheratinglistedinthe

“Absolute Maximum Ratings” table may cause

permanent damage to the device. These are

stress ratings only and operation of the device at

these or any other conditions above those indicat-

ed in the Operating sections of this specification is

not implied. Exposure to Absolute Maximum Rat-

ing conditions for extended periods may affect de-

vice reliability. Refer also to the

STMicroelectronics SURE Program and other rel-

evant quality documents.

Table 2. Absolute Maximum Ratings

Note: 1. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).

CAUTION! Negative undershoots below -0.3V are not allowed on any pin while in the Battery Back-up Mode.

Symbol Parameter Value Unit

TAOperating Temperature 0 to 70 °C

TSTG Storage Temperature (VCC, Oscillator Off) –40 to 85 °C

TSLD(1) Lead Solder Temperature for 10 seconds 260 °C

VCC Supply Voltage (on any

pin relative to Ground) M48T251Y –0.3 to +7.0 V

M48T251V –0.3 to +4.6 V

VIO Input or Output Voltages –0.3 to VCC + 0.3 V

IOOutput Current 20 mA

PDPower Dissipation 1 W

M48T251Y, M48T251V

6/23

DC AND AC PARAMETERS

This section summarizes the operating and mea-

surement conditions, as well as the DC and AC

characteristics of the device. The parameters in

the following DC and AC Characteristic tables are

derived from tests performed under the Measure-

ment Conditions listed in the relevant tables. De-

signers should check that the operating conditions

in their projects match the measurement condi-

tions when using the quoted parameters.

Table 3. DC and AC Measurement Conditions

Note: Output High Z is defined as the point where data is no longer driven (see Table 3, page 6).

Figure 5. AC Testing Load Circuit

Note: 50pF for M48T251V.

Table 4. Capacitance

Note: 1. Effective capacitance measured with power supply at 5V. Sampled only; not 100% tested.

2. At 25°C, f = 1MHz.

3. Outputs were deselected.

Parameter M48T251Y M48T251V

VCC Supply Voltage 4.5 to 5.5V 3.0 to 3.6V

Ambient Operating Temperature 0 to 70°C 0 to 70°C

Load Capacitance (CL)100pF 50pF

Input Rise and Fall Times ≤5ns ≤5ns

Input Pulse Voltages 0 to 3V 0 to 3V

Input and Output Timing Ref. Voltages 1.5V 1.5V

CL = 50 pF

DEVICE

UNDER

TEST

680 Ω

1.1 KΩ

VCCI

AI04240

Symbol Parameter(1,2) Min Max Unit

CIN Input Capacitance 10 pF

CIO(3) Input / Output Capacitance 10 pF

7/23

M48T251Y, M48T251V

Table 5. DC Characteristics

Note: 1. Valid for Ambient Operating Temperature: TA=0to70°C;V

CC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).

2. RST (Pin 1) has an internal pull-up resistor.

3. All voltages are referenced to Ground.

Sym Parameter(1) Test Condition

M48T251Y M48T251V

Unit–70 –85

Min Typ Max Min Typ Max

ILI(2) Input Leakage Current 0V ≤VIN ≤VCC ±1 ±1 µA

ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 ±1 µA

ICC1 Supply Current 85 50 mA

ICC2 Supply Current (TTL

Standby) CE =V

IH 510 5 7mA

CC3 VCC Power Supply

Current CE =V

CCI – 0.2 35 23mA

IL(3) Input Low Voltage –0.3 0.8 –0.3 0.6 V

VIH(3) Input High Voltage 2.2 VCC + 0.3 2.2 VCC +0.3 V

OL Output Low Voltage IOL =2.0mA 0.4 0.4 V

VOH Output High Voltage IOH = –1.0 mA 2.4 2.4 V

VPFD(3) Power Fail Deselect 4.25 4.37 4.50 2.80 2.97 V

VSO(3) Battery Back-up

Switchover VBAT 2.5 V

M48T251Y, M48T251V

8/23

OPERATION MODES

Table 6. Operating Modes

Note: X = VIH or VIL;V

SO = Battery Back-up Switchover Voltage

1. See Table 9, page 13 for details.

READ

A READ cycle executes whenever WRITE Enable

(WE) is high and Chip Enable (CE) is low (seeFig-

ure 6). The distinct address defined by the 19 ad-

dress inputs (A0-A18) specifies which of the 512K

bytes of data is to be accessed. Valid data will be

accessed by the eight data output drivers within

the specified Access Time (tACC) after the last ad-

dress input signal is stable, the CE and OE access

times, and their respective parameters are satis-

fied. When CE tACC and OE tACC are not satisfied,

then data access times must be measured from

the more recent CE and OE signals, with the limit-

ing parameter being tCO (for CE)ort

OE (for OE)in-

stead of address access.

WRITE

WRITEMode(seeFigure7,page9andFigure8,

page 10) occurs whenever CE and WE signals are

low (after address inputs are stable). The most re-

cent falling edge of CE and WE will determine

when the WRITE cycle begins (the earlier, rising

edge of CE or WE determines cycle termination).

All address inputs must be kept stable throughout

the WRITE cycle. WE must be high (inactive) for a

minimum recovery time (tWR) before a subsequent

cycle is initiated. The OE control signal should be

kept high (inactive) during the WRITE cycles to

avoid bus contention. If CE and OE are low (ac-

tive), WE will disable the outputs for Output Data

WRITE Time (tODW) from its falling edge.

Figure 6. Memory READ Cycle

Note: WE is high for a READ cycle.

Mode VCC CE OE WE DQ7-DQ0 Power

Deselect

4.5V to 5.5V

3.0V to 3.6V

VIH X X High-Z Standby

WRITE VIL XVIL DIN Active

READ VIL VIL VIH DOUT Active

READ VIL VIH VIH High-Z Active

Deselect VSO to VPFD (min)(1) X X X High-Z CMOS Standby

Deselect ≤VSO(1) X X X High-Z Battery Back-Up

DQ0 - DQ7

ADDRESSES

DATA OUTPUT

VALID

tOD

tODO

tOE

tRC

tCO

tACC

tCOE

tOH

AI04230

9/23

M48T251Y, M48T251V

Figure 7. Memory WRITE Cycle 1

Note: 1. OE =V

IH or VIL.IfOE=V

IH during a WRITE cycle, the output buffers remain in a high impedance state.

2. If the CE low transition occurs simultaneously with or later than the WE low transition in WRITE Cycle 1, the output buffers remain

in a high impedance state during this period.

3. If the CE high transition occurs simultaneously with the WE high transition, the output buffers remain in a high impedance state

during this period.

AI04231

DQ0–DQ7

ADDRESSES

DATA IN

STABLE

tWR

tOEW

tDH

tDS

tWC

tODW

tWP

tAW

HIGH IMPEDANCE

M48T251Y, M48T251V

10/23

Figure 8. Memory WRITE Cycle 2

Note: 1. OE =V

IH or VIL.IfOE=V

IH during a WRITE cycle, the output buffers remain in a high impedance state.

2. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high

impedance state during this period.

AI04232

DQ0–DQ7

ADDRESSES

WE = VIH

DATA IN

STABLE

tWR

tOEW

tWC

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIL VIL

VIH

tDS tDH

tODW

tCOE

tWP

tAW

11/23

M48T251Y, M48T251V

Table 7. Memory AC Characteristics, M48T251Y

Note: 1. Valid for Ambient Operating Temperature: TA=0to70°C;V

CC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).

2. These parameters are sampled with a 5 pF load are not 100% tested.

3. tWP is specified as the logical AND of CE and WE.t

WP is measured from the latter of CE or WE going low to the earlier of CE or

WE going high.

4. tDH and tDS are measured from the earlier of CE or WE going high.

Symbol Parameter(1) M48T251Y–70 Unit

Min Max

tAVAV tRC READ Cycle Time 70 ns

tAVQV tACC Access Time 70 ns

tELQV tCO Chip Enable Low to Output Valid 70 ns

tGLQV tOE Output Enable Low to Output Valid 35 ns

tELQX

tGLQX tCOE Chip Enable or Output Enable Low to Output Transition 5 ns

tAXQX tOH Output Hold from Address Change 5 ns

tEHQZ

tGHQZ tOD(2) Chip Enable or Output Enable High to Output Hi-Z 25 ns

tWLQZ tODW(2) Output Hi-Z from WE 25 ns

tAVAV tWC WRITE Cycle Time 70 ns

tWLWH

tELEH tWP(3) WE,CEPulse Width 50 ns

tAVEL

tAVWL tAW Address Setup Time 0 ns

tEHAX tWR1 WRITE Recovery Time 15 ns

tWHAX tWR2 Address Hold Time from WE 0ns

WHQX tOEW Output Active from WE 5ns

DVEH

tDVWH tDS(4) Data Setup Time 30 ns

tWHDX tDH1(4) Data Hold Time from WE 0ns

EHDX tDH2(4) Data Hold Time from CE 10 ns

M48T251Y, M48T251V

12/23

Table 8. Memory AC Characteristics, M48T251V

Note: 1. Valid for Ambient Operating Temperature: TA=0to70°C;V

CC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).

2. These parameters are sampled with a 5 pF load are not 100% tested.

3. tWP is specified as the logical AND of CE and WE.t

WP is measured from the latter of CE or WE going low to the earlier of CE or

WE going high.

4. tWR is a function of the latter occurring edge of WE or CE.

5. tDH and tDS are measured from the earlier of CE or WE going high.

Symbol Parameter(1) M48T251V–85 Unit

Min Max

tAVAV tRC READ Cycle Time 85 ns

tAVQV tACC Access Time 85 ns

tELQV tCO Chip Enable Low to Output Valid 85 ns

tGLQV tOE Output Enable Low to Output Valid 45 ns

tELQX

tGLQX tCOE Chip Enable or Output Enable Low to Output Transition 5 ns

tAXQX tOH Output Hold from Address Change 5 ns

tEHQZ

tGHQZ tOD(2) Chip Enable or Output Enable High to Output Hi-Z 35 ns

tWLQZ tODW(2) Output Hi-Z from WE 30 ns

tAVAV tWC WRITE Cycle Time 85 ns

tWLWH tWP1(3) WRITE Enable Pulse Width 65 ns

tELEH tWP2 Chip Enable Pulse Width 75 ns

tAVEL

tAVWL tAW Address Setup Time 0 ns

tEHAX tWR1(4) WRITE Recovery Time 15 ns

tWHAX tWR2 Address Hold Time from WE 5ns

WHQX tOEW Output Active from WE 5ns

DVEH

tDVWH tDS(5) Data Setup Time 35 ns

tWHDX tDH1(5) Data Hold Time from WE 0ns

EHDX tDH2 Data Hold Time from CE 15 ns

13/23

M48T251Y, M48T251V

Data Retention Mode

Data can be read or written only when VCC is

greater than VPFD. When VCC is below VPFD (the

point at which write protection occurs), the clock

registers and the SRAM are blocked from any ac-

cess. When VCC falls below the Battery Switch

Over threshold (VSO), the device is switched from

VCC to battery backup (VBAT). RTC operation and

SRAM data are maintained via battery backup un-

til power is stable. All control, data, and address

signals must be powered down when VCC is pow-

ered down.

The lithium power source is designed to provide

power for RTC activity as well as RTC and RAM

data retention when VCC is absent or unstable.

The capability of this source is sufficient to power

the device continuously for the life of the equip-

ment into which it has been installed. For specifi-

cation purposes, life expectancy is ten (10) years

at 25°C with the internal oscillator running without

VCC. Each unit is shipped with its energy source

disconnected, guaranteeing full energy capacity.

When VCC is first applied at a level greater than

VPFD, the energy source is enabled for battery

backup operation. The actual life expectancy will

be much longer if no battery energy is used (e.g.,

when VCC is present).

Figure 9. Power Down/Up Mode AC Waveforms

Table 9. Power Down/Up Trip Points DC Characteristics

Note: 1. Valid for Ambient Operating Temperature: TA=0to70°C;V

CC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).

2. At 25°C, the expected tDR is defined as cumulative time in the absence of VCC with the clock oscillator running.

Symbol Parameter(1) Min Max Unit

tREC VPFD (max) to CE low 1.5 2.5 ms

tFVPFD (max) to VPFD (min) VCC Fall Time 300 µs

tFB VPFD (min) to VSO VCC Fall Time 10 µs

tRVPFD (min) to VPFD (max) VCC Rise Time 0µs

tPD CE High to Power-Fail 0 µs

tDR(2) Expected Data Retention Time 10 Years

tDR

tREC

tPD

tFB

VSO

VCC

VPFD (max)

VPFD (min)

AI04236

M48T251Y, M48T251V

14/23

PHANTOM CLOCK OPERATION

Communication with the Phantom Clock is estab-

lished by pattern recognition of a serial bit-stream

of 64 bits which must be matched by executing 64

consecutive WRITE cycles containing the proper

data on DQ0.

All accesses which occur prior to recognition of the

64-bit pattern are directed to memory.

After recognition is established, the next 64 READ

or WRITE cycles either extract or update data in

the clock while disabling the memory.

Data transfer to and from the timekeeping function

is accomplished with a serial bit-stream under con-

trol of Chip Enable (CE), Output Enable (OE), and

WRITE Enable (WE). Initially, a READ cycle using

the CE and OE control of the clock starts the pat-

tern recognition sequence by moving the pointerto

the first bit of the 64-bit comparison register (see

Figure 10, page 15).

Next, 64 consecutive WRITE cycles are executed

using the CE and WE control of the device. These

64 WRITE cycles are used only to gain access to

the clock. Therefore, any address to the memory

is acceptable. However, the WRITE cycles gener-

ated to gain access to the Phantom Clock are also

writing data to a location in the mated RAM. The

preferred way to manage this requirement is to set

aside just one address location in RAM as a Phan-

tom Clock scratch pad.

When the first WRITE cycle is executed, it is com-

pared to Bit 1 of the 64-bit comparison register. If

a match is found, the pointer increments to the

next location of the comparison register and

awaits the next WRITE cycle.

If a match is not found, the pointer does not ad-

vance and all subsequent WRITE cycles are ig-

nored. If a READ cycle occurs at any time during

pattern recognition, the present sequence is abort-

ed and the comparison register pointer is reset.

Pattern recognition continues for a total of 64

WRITE cycles as described above until all of the

bits in the comparison register have been

matched. With a correct match for 64-bits, the

Phantom Clock is enabled and data transfer to or

from the timekeeping registers can proceed. The

next 64 cycles will cause the Phantom Clock to ei-

ther receive or transmit data on DQ0, depending

on the level of the OE pin orthe WE pin. Cycles to

other locations outside the memory block can be

interleaved with CE cycles without interrupting the

pattern recognition sequence or data transfer se-

quence to the Phantom Clock.

15/23

M48T251Y, M48T251V

Figure 10. Comparison Register Definition

Note: The odds of this pattern being accidentally duplicated and sending aberrant entries to the RTC is less than 1 in 1019. This pattern is

senttotheclockLSBtoMSB.

765 43210

BYTE 0

BYTE 1

BYTE 2

BYTE 3

BYTE 4

BYTE 5

BYTE 6

BYTE 7

Hex

Value

010 00

101 11

110 01

001 10

010 00

101 11

110 01

001 10

AI04262

M48T251Y, M48T251V

16/23

Clock Register Information

Clock information is contained in eight registers of

8 bits, each of which is sequentially accessed one

(1) bit at a time after the 64-bit pattern recognition

sequence has been completed. When updating

the clock registers, each must be handled in

groups of 8 bits. Writing andreading individualbits

within a register could produce erroneous results.

These READ/WRITE registers are defined in the

clock register map (see Table 10).

Data contained in the clock registers is in Binary

Coded Decimal format(BCD). Reading and writing

the registers is always accomplished by stepping

through all eight registers, starting with Bit 0 of

Clock Accuracy

The RTC is guaranteed to keep time accuracy to

with ±1 minute per month at 25°C. The clock is fac-

tory-tuned with special calibration elements, and

does not require additional calibration. Moderate

temperature deviation will have a negligible effect

in most applications.

AM-PM/12/24 Mode

Bit 7 of the hours register is defined as the 12-hour

or 24-hour mode select bit. When it is high, the 12-

hour mode is selected. In the 12-hour mode, Bit 5

is the AM/PM bit with the logic high being “PM.” In

the 24-hour mode, Bit 5 is the second 10-hour bit

(20-23 hours).

Oscillator and Reset Bits

Bits 4 and 5 of the day register are used to control

the reset and oscillator functions. Bit4 controls the

reset pin input. When the reset bit is set to logic '1,'

the Reset Input pin is ignored. When the reset bit

logic is set to '0,' a low input on the reset pin will

cause the device to abort data transfer without

changing data in the timekeeping registers. Reset

operates independently of all other inputs. Bit 5

controls the oscillator. When set to logic '0,' the os-

cillator turns on and the RTC/calendar begins to

increment.

Zero Bits

Registers 1, 2, 3, 4, 5, and 6 contain one (1) or

more bits that will always read logic '0.' When writ-

ing to these locations, either a logic '1' or '0' is ac-

ceptable.

Table 10. Phantom Clock Register Map

Keys: A/P = AM/PM Bit

12/24 = 12 or 24-hour mode Bit

OSC = Oscillator Bit

RST = Reset Bit

0=Mustbesetto'0'

Function/Range

BCD Format

0 0.1 Seconds 0.01 Seconds Seconds 00-99

1 0 10 Seconds Seconds Seconds 00-59

2 0 10 Minutes Minutes Minutes 00-59

3 12/24 0 10 /

A/P Hrs Hours (24 Hour Format) Hours 01-12/

00-23

400OSC

RST 0 Day of the Week Day 01-7

5 0 0 10 date Date: Day of the Month Date 01-31

6 0 0 0 10M Month Month 01-12

7 10 Years Year Year 00-99

17/23

M48T251Y, M48T251V

Figure 11. Phantom Clock READ Cycle

Figure 12. Phantom Clock WRITE Cycle

Figure 13. Phantom Clock Reset

DATA OUTPUT VALID

tCW

tCO

tRC

tOW

tCOE

tODO

tRR

tOD

tOE

tOEE

AI04259

DATA INPUT STABLE

tWP

tWC

tCW

tDH

tWR

tDH

tDS

AI04261

tRST

RST

AI04235

M48T251Y, M48T251V

18/23

Table 11. Phantom Clock AC Characteristics (M48T251Y)

Note: 1. Valid for Ambient Operating Temperature: TA=0to70°C;V

CC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).

2. These parameters are sampled with a 5 pF load and are not 100% tested.

3. tWP is specified as the logical AND of CE and WE.t

WP is measured from the latter of CE or WE going low to the earlier of CE or

WE going high.

4. tWR is a function of the latter occurring edge of WE or CE.

5. tDH and tDS are measured from the earlier of CE or WE going high.

Symbol Parameter(1) Min Typ Max Unit

tAVAV tRC READ Cycle Time 65 ns

tELQV tCO CE Access Time 55 ns

tGLQV tOE OE Access Time 55 ns

tELQX tCOE CE to Output Low Z 5 ns

tGLQX tOEE OE to Output Low Z 5 ns

tEHQZ tOD(2) CE to Output High Z 25 ns

tGHQZ tODO(2) OE to Output High Z 25 ns

tRR READ Recovery 10 ns

tAVAV tWC WRITE Cycle Time 65 ns

tWLWH tWP(3) WRITE Pulse Width 55 ns

tEHAX tWR(4) WRITE Recovery 10 ns

tDVEH tDS(5) Data Setup Time 30 ns

tWHDX tDH1(5) Data Hold Time from WE 0ns

EHDX tDH2(5) Data Hold Time from CE 0ns

ELEH tCW CE Pulse Width 55 ns

tRST RST Pulse Width 65 ns

19/23

M48T251Y, M48T251V

Table 12. Phantom Clock AC Characteristics (M48T251V)

Note: 1. Valid for Ambient Operating Temperature: TA=0to70°C;V

CC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).

2. These parameters are sampled with a 5 pF load and are not 100% tested.

3. tWP is specified as the logical AND of CE and WE.t

WP is measured from the latter of CE or WE going low to the earlier of CE or

WE going high.

4. tWR is a function of the latter occurring edge of WE or CE.

5. tDH and tDS are measured from the earlier of CE or WE going high.

Symbol Parameter(1) Min Typ Max Unit

tAVAV tRC READ Cycle Time 85 ns

tELQV tCO CE Access Time 85 ns

tGLQV tOE OE Access Time 85 ns

tELQX tCOE CE to Output Low Z 5 ns

tGLQX tOEE OE to Output Low Z 5 ns

tEHQZ tOD(2) CE to Output High Z 30 ns

tGHQZ tODO(2) OE to Output High Z 30 ns

tRR READ Recovery 20 ns

tAVAV tWC WRITE Cycle Time 85 ns

tWLWH tWP(3) WRITE Pulse Width 60 ns

tEHAX tWR(4) WRITE Recovery 20 ns

tDVEH tDS(5) Data Setup Time 35 ns

tWHDX tDH1(5) Data Hold Time from WE 0ns

EHDX tDH2(5) Data Hold Time from CE 0ns

ELEH tCW CE Pulse Width 65 ns

tRST RST Pulse Width 85 ns

M48T251Y, M48T251V

20/23

PART NUMBERING

Table 13. Ordering Information Example

For a list of available options (e.g.,Speed, Package) or for further information on any aspect of this device,

please contact the ST Sales Office nearest to you.

Example: M48T 251Y –70 PM 1 TR

Device Type

M48T

Supply Voltage and Write Protect Voltage

251Y = VCC = 4.5 to 5.5V; VPFD = 4.25 to 4.50V

251V = VCC = 3.0 to 3.6V; VPFD = 2.80 to 2.97V

Speed

–70 = 70ns (M48T251Y)

–85 = 85ns (M48T251V)

Package

PM = PMDIP32

Temperature Range

1 = 0 to 70°C

Shipping Method for SOIC

blank = Tubes

TR = Tape & Reel

21/23

M48T251Y, M48T251V

PACKAGE MECHANICAL INFORMATION

Figure 14. PMDIP32 – 32-pin Plastic Module DIP, Package Outline

Note: Drawing is not to scale.

Table 14. PMDIP32 – 32-pin Plastic Module DIP, Package Mechanical Data

Symb mm inches

Typ Min Max Typ Min Max

A 9.27 9.52 0.365 0.375

A1 0.38 – 0.015 –

B 0.43 0.59 0.017 0.023

C 0.20 0.33 0.008 0.013

D 42.42 43.18 1.670 1.700

E 18.03 18.80 0.710 0.740

e1 2.29 2.79 0.090 0.110

e3 34.29 41.91 1.350 1.650

eA 14.99 16.00 0.590 0.630

L 3.05 3.81 0.120 0.150

S 1.91 2.79 0.075 0.110

N3232

PMDIP

Be1

M48T251Y, M48T251V

22/23

REVISION HISTORY

Table 15. Document Revision History

Date Revision Details

June 2001 First Issue

05/20/02 Add countries to disclaimer

23/23

M48T251Y, M48T251V

M48T251, M48T251Y, M48T251V, 48T251, 48T251Y, 48T251V, T251, T251Y, T251V, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER,

TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEP-

ER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIME-

KEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM,

NVRAM, NVRAM,NVRAM, NVRAM,NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM,NVRAM, NVRAM,NVRAM, NVRAM,

NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, SRAM, SRAM,

SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM,

SRAM,SRAM,SRAM,SRAM,SRAM,SRAM,SRAM,RTC,RTC,RTC,RTC,RTC,RTC,RTC,RTC,RTC,RTC,RTC,RTC,RTC,RTC,

RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC,

RTC, RTC, RTC, Transparent, Transparent, Transparent, Transparent, Transparent, Transparent, Transparent, Transparent, Transparent,

Transparent, Transparent, Transparent, Transparent, Transparent, Transparent, Transparent, Transparent, Transparent, Transparent,

Transparent, Transparent, Transparent, Transparent, Transparent, Transparent, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock,

Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock,

Clock, Clock, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Comparator,

Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Com-

parator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator,

Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Com-

parator, Comparator, Comparator, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crys-

tal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal,

Crystal, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery,Bat-

tery,Battery,Battery,Battery,Battery,Battery,Battery,Battery,Battery,Battery,Battery,Battery,Battery,Battery,Battery,Battery,Battery,

Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery,Bat-

tery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Switchover, Switchover, Switchover,

Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Backup, Backup, Backup, Backup, Backup, Backup,

Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, 5V, 5V, 5V, 5V,

5V,5V,5V,5V,5V,5V,5V,5V,5V,5V,5V,5V,5V,5V,5V,5V,5V,5V,5V,5V,5V,5V,5V,5V,5V,5V,5V,5V,5V,5V,5V,5V,5V,5V,5V,

5V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights ofthird parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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All other names are the property of their respective owners.

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