Dual Bootstrapped 12 V MOSFET Driver with Output Disable ADP3418 FEATURES APPLICATIONS All-in-one synchronous buck driver Bootstrapped high-side drive 1 PWM signal generates both drives Anticross-conduction protection circuitry Output disable control turns off both MOSFETs to float output per Intel(R) VRM 10 specification Multiphase desktop CPU supplies Single-supply synchronous buck converters FUNCTIONAL BLOCK DIAGRAM VCC 4 The ADP3418 is a dual, high voltage MOSFET driver optimized for driving two N-channel MOSFETs, the two switches in a nonisolated, synchronous, buck power converter. Each of the drivers is capable of driving a 3000 pF load with a 20 ns propagation delay and a 30 ns transition time. One of the drivers can be bootstrapped, and is designed to handle the high voltage slew rate associated with floating high-side gate drivers. The ADP3418 includes overlapping drive protection to prevent shoot-through current in the external MOSFETs. The OD pin shuts off both the high-side and the low-side MOSFETs to prevent rapid, output capacitor discharge during system shutdowns. BST 1 IN 2 OVERLAP PROTECTION CIRCUIT OD 3 ADP3418 6 PGND The ADP3418 is specified over the commercial temperature range of 0C to 85C, and is available in an 8-lead SOIC package. 8 DRVH 7 SW 5 DRVL 03229-0-001 GENERAL DESCRIPTION Figure 1. Functional Block Diagram 12V VCC CVCC D1 4 ADP3418 BST 1 CBST IN DRVH 8 Q1 SW 7 TO INDUCTOR DELAY 1V DRVL 5 Q2 PGND 6 OD 3 03229-0-002 1V Figure 2. General Application Circuit Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved. ADP3418 TABLE OF CONTENTS Specifications..................................................................................... 3 High-Side Driver ...........................................................................9 Absolute Maximum Ratings............................................................ 4 Overlap Protection Circuit...........................................................9 ESD Caution.................................................................................. 4 Application Information................................................................ 10 Pin Configuration and Function Descriptions............................. 5 Supply Capacitor Selection ....................................................... 10 Timing Characteristics..................................................................... 6 Bootstrap Circuit ........................................................................ 10 Typical Performance Characteristics ............................................. 7 PC Board Layout Considerations............................................. 10 Theory of Operation ........................................................................ 9 Outline Dimensions ....................................................................... 12 Low-Side Driver............................................................................ 9 Ordering Guide .......................................................................... 12 REVISION HISTORY Revision A 4/04--Data Sheet Changed from Rev. 0 to Rev. A Updated format....................................................................... Universal Change to General Description ...........................................................1 Change to Figure 14 ..............................................................................8 Change to Ordering Guide.................................................................12 3/03--Revision 0: Initial Version Rev. A | Page 2 of 12 ADP3418 SPECIFICATIONS All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC). VCC = 12 V, BST = 4 V to 26 V, TA = 0C to 85C, unless otherwise noted. Table 1. Parameter SUPPLY Supply Voltage Range Supply Current OD INPUT Input Voltage High Input Voltage Low Input Current Propagation Delay Time1 PWM INPUT Input Voltage High Input Voltage Low Input Current HIGH-SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Transition Times 1 Symbol Conditions VCC ISYS BST = 12 V, IN = 0 V 1 LOW-SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Transition Times 1 Propagation Delay , 1 1 2 2 Typ Max Unit 3 13.2 6 V mA V V A ns 4.15 2.8 tpdhOD See Figure 4 20 0.8 +1 40 tpdlOD See Figure 4 15 40 ns 0.8 +1 V V A 1.8 1.0 35 3.0 2.5 45 ns -1 3.5 -1 trDRVH tfDRVH Propagation Delay , 2 Min tpdhDRVH tpdlDRVH trDRVL tfDRVL tpdhDRVL tpdlDRVL VBST - VSW = 12 V VBST - VSW = 12 V See Figure 5, VBST - VSW = 12 V, CLOAD = 3 nF See Figure 5, VBST - VSW = 12 V, CLOAD = 3 nF See Figure 5, VBST - VSW = 12 V VBST - VSW = 12 V 20 30 ns 40 20 65 35 ns ns See Figure 5, CLOAD = 3 nF See Figure 5, CLOAD = 3 nF See Figure 5 See Figure 5 1.8 1.0 25 21 30 10 3.0 2.5 35 30 60 20 ns ns ns ns AC specifications are guaranteed by characterization, but not production tested. For propagation delays, tpdh refers to the specified signal going high, and tpdl refers to it going low. Rev. A | Page 3 of 12 ADP3418 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VCC BST BST to SW SW DC <200 ns DRVH DRVL (<200 ns) All Other Inputs and Outputs Operating Ambient Temperature Range Operating Junction Temperature Range Storage Temperature Range Junction-to-Air Thermal Resistance (JA) 2-Layer Board 4-Layer Board Lead Temperature (Soldering, 10 sec) Vapor Phase (60 sec) Infrared (15 sec) Rating -0.3 V to +15 V -0.3 V to VCC + 15 V -0.3 V to +15 V -5 V to +15 V -10 V to +15 V SW - 0.3 V to BST + 0.3 V -2 V to VCC + 0.3 V -0.3 V to VCC + 0.3 V 0C to 85C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all voltages are referenced to PGND. 0C to 150C -65C to +150C 123C/W 90C/W 300C 215C 220C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 4 of 12 ADP3418 BST 1 IN 2 OD 3 VCC 4 ADP3418 TOP VIEW (Not to Scale) 8 DRVH 7 SW 6 PGND 5 DRVL 03229-0-003 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 Mnemonic BST 2 3 4 5 6 7 IN OD VCC DRVL PGND SW 8 DRVH Description Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this bootstrapped voltage for the high-side MOSFET as it is switched. The capacitor should be between 100 nF and 1 F. Logic Level Input. This pin has primary control of the drive outputs. Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low. Input Supply. This pin should be bypassed to PGND with ~1 F ceramic capacitor. Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET. Power Ground. Should be closely connected to the source of the lower MOSFET. This pin is connected to the buck switching node, close to the upper MOSFET's source. It is the floating return for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent turn on of the lower MOSFET until the voltage is below ~1 V. Thus, according to operating conditions, the high-low transition delay is determined at this pin. Buck Drive. Output drive for the upper (buck) MOSFET. Rev. A | Page 5 of 12 ADP3418 TIMING CHARACTERISTICS OD tpdlOD DRVH OR DRVL tpdhOD 03229-0-004 90% 10% Figure 4. Output Disable Timing Diagram IN tpdlDRVL tfDRVL tpdlDRVH trDRVL DRVL tfDRVH tpdhDRVH trDRVH VTH VTH tpdhDRVL 1V SW 03229-0-005 DRVH-SW Figure 5. Nonoverlap Timing Diagram. Timing Is Referenced to the 90% and 10% Points, Unless Otherwise Noted. Rev. A | Page 6 of 12 ADP3418 TYPICAL PERFORMANCE CHARACTERISTICS 26 VCC = 12V CLOAD = 3nF IN 1 24 FALL TIME (ns) DRVL DRVH 2 22 DRVH 20 DRVL 18 16 0 25 50 75 100 JUNCTION TEMPERATURE (C) 125 03229-0-009 03229-0-006 3 Figure 9. DRVH and DRVL Fall Times vs. Temperature Figure 6. DRVH Rise and DRVL Fall Times 60 TA = 25C VCC = 12V IN DRVH 50 1 RISE TIME - ns DRVH 2 40 DRVL 30 20 DRVL 10 1 Figure 7. DRVH Fall and DRVL Rise Times 35 4 5 TA = 25C VCC = 12V DRVH 30 35 FALL TIME (ns) DRVL 30 DRVL 25 DRVH 20 25 20 0 25 50 75 100 JUNCTION TEMPERATURE (C) 125 10 1 2 3 LOAD CAPACITANCE (nF) 4 5 Figure 11. DRVH and DRVL Fall Times vs. Load Capacitance Figure 8. DRVH and DRVL Rise Times vs. Temperature Rev. A | Page 7 of 12 03229-0-011 15 03229-0-008 RISE TIME (ns) 3 LOAD CAPACITANCE - nF Figure 10. DRVH and DRVL Rise Times vs. Load Capacitance 40 VCC = 12V CLOAD = 3nF 2 03229-0-010 03229-0-007 3 ADP3418 60 5 TA = 25C CLOAD = 3nF DRVL OUTPUT VOLTAGE (V) SUPPLY CURRENT (mA) TA = 25C VCC = 12V CLOAD = 3nF 40 20 4 3 2 0 200 400 600 800 IN FREQUENCY (kHz) 1000 1200 0 0 16 VCC = 12V CLOAD = 3nF fIN = 250kHz 14 13 12 50 75 100 JUNCTION TEMPERATURE (C) 125 03229-0-013 SUPPLY CURENT (mA) 15 25 2 3 VCC VOLTAGE (V) 4 Figure 14. DRVL Output Voltage vs. Supply Voltage Figure 12. Supply Current vs. Frequency 0 1 Figure 13. Supply Current vs. Temperature Rev. A | Page 8 of 12 5 03229-0-014 0 03229-0-012 1 ADP3418 THEORY OF OPERATION The ADP3418 is a dual MOSFET driver optimized for driving two N-channel MOSFETs in a synchronous buck converter topology. A single PWM input signal is all that is required to properly drive the high-side and the low-side MOSFETs. Each driver is capable of driving a 3 nF load at speeds up to 500 kHz. A more detailed description of the ADP3418 and its features follows. Refer to the Functional Block Diagram. LOW-SIDE DRIVER The low-side driver is designed to drive a ground-referenced low RDS(ON) N-channel MOSFET. The bias to the low-side driver is internally connected to the VCC supply and PGND. When the driver is enabled, the driver's output is 180 degrees out of phase with the PWM input. When the ADP3418 is disabled, the low-side gate is held low. HIGH-SIDE DRIVER The high-side driver is designed to drive a floating, low RDS(ON) N-channel MOSFET. The bias voltage for the high-side driver is developed by an external bootstrap supply circuit, which is connected between the BST and SW pins. The bootstrap circuit comprises a diode, D1, and bootstrap capacitor, CBST. When the ADP3418 is starting up, the SW pin is at ground, so the bootstrap capacitor will charge up to VCC through D1. When the PWM input goes high, the high-side driver will begin to turn on the high-side MOSFET, Q1, by pulling charge out of CBST. As Q1 turns on, the SW pin will rise up to VIN, forcing the BST pin to VIN + VC(BST), which is enough gate-to-source voltage to hold Q1 on. To complete the cycle, Q1 is switched off by pulling the gate down to the voltage at the SW pin. When the low-side MOSFET, Q2, turns on, the SW pin is pulled to ground. This allows the bootstrap capacitor to charge up to VCC again. OVERLAP PROTECTION CIRCUIT The overlap protection circuit prevents both of the main power switches, Q1 and Q2, from being on at the same time. This is done to prevent shoot-through currents from flowing through both power switches and the associated losses that can occur during their on-off transitions. The overlap protection circuit accomplishes this by adaptively controlling the delay from Q1's turn-off to Q2's turn-on, and by internally setting the delay from Q2's turn-off to Q1's turn-on. To prevent the overlap of the gate drives during Q1's turn-off and Q2's turn-on, the overlap circuit monitors the voltage at the SW pin. When the PWM input signal goes low, Q1 will begin to turn-off (after a propagation delay), but before Q2 can turn on, the overlap protection circuit waits for the voltage at the SW pin to fall from VIN to 1 V. Once the voltage on the SW pin has fallen to 1 V, Q2 will begin turn-on. By waiting for the voltage on the SW pin to reach 1 V, the overlap protection circuit ensures that Q1 is off before Q2 turns on, regardless of variations in temperature, supply voltage, gate charge, and drive current. To prevent the overlap of the gate drives during Q2's turn-off and Q1's turn-on, the overlap circuit provides an internal delay that is set to 50 ns. When the PWM input signal goes high, Q2 will begin to turn off (after a propagation delay), but before Q1 can turn on, the overlap protection circuit waits for the voltage at DRVL to drop to around 10% of VCC. Once the voltage at DRVL has reached the 10% point, the overlap protection circuit will wait for a 20 ns typical propagation delay. Once the delay period has expired, Q1 will begin turn-on. The high-side driver's output is in phase with the PWM input. When the driver is disabled, the high-side gate is held low. Rev. A | Page 9 of 12 ADP3418 APPLICATION INFORMATION SUPPLY CAPACITOR SELECTION PC BOARD LAYOUT CONSIDERATIONS For the supply input (VCC) of the ADP3418, a local bypass capacitor is recommended to reduce the noise and to supply some of the peak currents drawn. Use a 4.7 F, low ESR capacitor. Multilayer ceramic chip (MLCC) capacitors provide the best combination of low ESR and small size. Keep the ceramic capacitor as close as possible to the ADP3418. Use the following general guidelines when designing printed circuit boards. BOOTSTRAP CIRCUIT 3. The bootstrap circuit uses a charge storage capacitor (CBST) and a diode, as shown in Figure 2. These components can be selected after the high-side MOSFET has been chosen. The bootstrap capacitor must have a voltage rating that is able to handle twice the maximum supply voltage. A minimum 50 V rating is recommended. The capacitance is determined using the following equation: QGATE (1) CBST = VBST where QGATE is the total gate charge of the high-side MOSFET, and VBST is the voltage droop allowed on the high-side MOSFET drive. For example, an IPD30N06 has a total gate charge of about 20 nC. For an allowed droop of 200 mV, the required bootstrap capacitance is 100 nF. A good quality ceramic capacitor should be used. 1. 2. 4. Trace out the high current paths and use short, wide (>20 mil) traces to make these connections. Connect the PGND pin of the ADP3418 as close as possible to the source of the lower MOSFET. The VCC bypass capacitor should be located as close as possible to the VCC and PGND pins. Use vias to other layers when possible to maximize thermal conduction away from the IC. The circuit in Figure 16 shows how three drivers can be combined with the ADP3168 to form a total power conversion solution for generating VCC(CORE) for an Intel CPU that is VRD 10 compliant. Figure 15 shows an example of the typical land patterns based on the guidelines given previously. For more detailed layout guidelines for a complete CPU voltage regulator subsystem, refer to the ADP3168 data sheet. CBST D1 A small-signal diode can be used for the bootstrap diode due to the ample gate drive voltage supplied by VCC. The bootstrap diode must have a minimum 15 V rating to withstand the maximum supply voltage. The average forward current can be estimated by I F ( AVG) = QGATE x f MAX (2) CVCC 03229-0-016 where fMAX is the maximum switching frequency of the controller. The peak surge current rating should be checked incircuit, since this is dependent on the source impedance of the 12 V supply and the ESR of CBST. Figure 15. External Component Placement Example for the ADP3418 Driver Rev. A | Page 10 of 12 ADP3418 VIN 12V L1 1.6 H 470 F/16V x 6 NICHICON PW SERIES + + C1 C9 4.7 F D2 1N4148WS VIN RTN C6 U2 C8 ADP3418 100nF D1 1N4148WS Q1 IPD12N03L DRVH 8 1 BST 2 IN 3 OD PGND 6 4 VCC DRVL 5 820 F/2.5V x 8 L2 FUJITSU RE SERIES 600nH/1.6m 14m ESR (EACH) SW 7 C10 4.7nF C7 4.7 F D3 1N4148WS IN 3 OD PGND 6 4 DRVL 5 VCC R2 2.2 Q5 IPD06N03L D4 1N4148WS U4 C17 4.7 F C16 DRVH 8 SW 7 OD PGND 6 VCC DRVL 5 BST 2 IN 3 4 Q7 IPD12N03L RTH 100k, 5% R3 2.2 Q8 IPD06N03L Q9 IPD06N03L + C20 C19 1 F FROM CPU 33 F CB 1.5nF CFB 33pF CA RA 390pF 16.9k RR 412k U1 ADP3168 1 VID4 VCC 28 2 VID3 PWM1 27 3 VID2 PWM2 26 4 VID1 PWM3 25 5 VID0 PWM4 24 6 VID5 SW1 23 7 FBRTN SW2 22 8 FB SW3 21 RT 249k RSW1 RSW2 RSW3 9 COMP 10 PWRGD 11 EN ENABLE SW4 20 GND 19 CSCOMP 18 12 DELAY CSSUM 17 13 RT CSREF 16 14 RAMPADJ CCS2 RCS1 1.5nF 35.7k RPH1 124k RPH3 124k R CS2 73.2k RPH2 124k CCS1 2.2nF ILIMIT 15 RLIM 200k 03229-0-015 RDLY 390k L4 600nH/1.6m C18 4.7nF C15 4.7 F CDLY 39nF Q6 IPD06N03L ADP3418 100nF 1 RB 1.33k C28 C14 4.7nF C11 4.7 F POWER GOOD 0.8375V - 1.6V 65A AVG, 74A PK L3 600nH/1.6m 7 SW VCC(CORE) 10F x 20 MLCC IN SOCKET Q4 IPD12N03L DRVH 8 BST 2 C21 C13 4.7 F C12 U3 ADP3418 100nF 1 + VCC(CORE) RTN R1 2.2 Q3 IPD06N03L Q2 IPD06N03L R4 10 + Figure 16. VRD 10 Compliant Intel CPU Supply Circuit Rev. A | Page 11 of 12 ADP3418 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 8 5 4.00 (0.1574) 3.80 (0.1497) 1 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) 6.20 (0.2440) 5.80 (0.2284) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) COPLANARITY SEATING 0.31 (0.0122) 0.10 PLANE 0.50 (0.0196) x 45 0.25 (0.0099) 8 0.25 (0.0098) 0 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 17. 8-Lead Standard Small Outline Package [SOIC] (RN-8) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model ADP3418JR ADP3418JR-REEL ADP3418JRZ* ADP3418JRZ-REEL* Temperature Range 0C to 85C 0C to 85C 0C to 85C 0C to 85C Package Description 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC *Z = Pb-free part. (c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03229-0-4/04(A) Rev. A | Page 12 of 12 Package Option RN-8 RN-8 RN-8 RN-8 Quantity Per Reel N/A 2500 N/A 2500