K6T0808C1D-RB70 - Samsung Electronics

K6T0808C1D Family CMOS SRAM

Revision 1.0

November 1997

Document Title

32Kx8 bit Low Power CMOS Static RAM

Revision History

Revision No

0.0

0.1

1.0

Remark

Design target

Preliminily

Final

History

Initial draft

First revision

- KM62256DL/DLI ISB1 = 100 → 50µA

KM62256DL-L ISB1 = 20 → 10µA

KM62256DLI-L ISB1 = 50 → 15µA

- CIN = 6 → 8pF, CIO = 8 → 10pF

- KM62256D-4/5/7 Family

tOH = 5 → 10ns

- KM62256DL/DLI IDR = 50→30µA

KM62256DL-L/DLI-L IDR = 30 → 15µA

Finalize

- Remove ICC write value

- Improved operating current

ICC2 = 70 → 60mA

- Improved standby current

KM62256DL/DLI ISB1 = 50 → 30µA

KM62256DL-L ISB1 = 10 → 5µA

KM62256DLI-L ISB1 = 15 → 5µA

- Improved data retention current

KM62256DL/DLI IDR = 30 → 5µA

KM62256DL-L/DLI-L IDR = 15 → 3µA

- Remove 45ns part from commercial product and 100ns part

from industrial product.

Replace test load 100pF to 50pF for 55ns part

Draft Data

May 18, 1997

April 1, 1997

November 11, 1997

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and

products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.

K6T0808C1D Family CMOS SRAM

Revision 1.0

November 1997

32Kx8 bit Low Power CMOS Static RAM

GENERAL DESCRIPTION

The K6T0808C1D families are fabricated by SAMSUNG′s

advanced CMOS process technology. The families support

various operating temperature ranges and have various

package types for user flexibility of system design. The fami-

lies also support low data retention voltage for battery back-

up operation with low data retention current.

FEATURES

• Process Technology : TFT

• Organization : 32Kx8

• Power Supply Voltage : 4.5~5.5V

• Low Data Retention Voltage : 2V(Min)

• Three state output and TTL Compatible

• Package Type : 28-DIP-600B, 28-SOP-450

28-TSOP1-0813.4 F/R

PIN DESCRIPTION

Pin Name Function Pin Name Function

CS Chip Select Input I/O1~I/O8Data Inputs/Outputs

OE Output Enable Input Vcc Power

WE Write Enable Input Vss Ground

A0~A14 Address Inputs NC No connect

PRODUCT FAMILY

1. The parameter is tested with 50pF test load.

Product Family Operating Temperature VCC Range Speed Power Dissipation PKG Type

Standby

(ISB1, Max) Operating

(Icc2, Max)

K6T0808C1D-L Commercial (0~70°C)

4.5 to 5.5V

551)/70ns 30µA

60mA

28-DIP,28-SOP

28-TSOP1-F/R

K6T0808C1D-B 5µA

K6T0808C1D-P Industrial (-40~85°C) 70ns 30µA28-SOP

28-TSOP1-F/R

K6T0808C1D-F 5µA

FUNCTIONAL BLOCK DIAGRAM

A14

A12

I/O1

I/O2

I/O3

VSS

VCC

A13

A11

A10

I/O8

I/O7

I/O6

I/O5

I/O4

28-DIP

28-SOP

A11

A13

VCC

A14

A12

A10

I/O8

I/O7

I/O6

I/O5

I/O4

VSS

I/O3

I/O2

I/O1

28-TSOP

Type1 - Forward

28-TSOP

A11

A13

VCC

A14

A12

A10

I/O8

I/O7

I/O6

I/O5

I/O4

VSS

I/O3

I/O2

I/O1

Type1 - Reverse

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

Precharge circuit.

Memory array

256 rows

128×8 columns

I/O Circuit

Column select

Clk gen.

Row

select

A10 A3 A0 A1 A2 A11A9

A13

A12

A14

I/O1Data

cont

Data

cont

I/O8

Control

Logic

K6T0808C1D Family CMOS SRAM

Revision 1.0

November 1997

PRODUCT LIST

Commercial Temperature Products(0~70°C) Industrial Temperature Products(-40~85°C)

Part Name Function Part Name Function

K6T0808C1D-DL55

K6T0808C1D-DB55

K6T0808C1D-DL70

K6T0808C1D-DB70

K6T0808C1D-GL55

K6T0808C1D-GB55

K6T0808C1D-GL70

K6T0808C1D-GB70

K6T0808C1D-TL55

K6T0808C1D-TB55

K6T0808C1D-TL70

K6T0808C1D-TB70

K6T0808C1D-RL55

K6T0808C1D-RB55

K6T0808C1D-RL70

K6T0808C1D-RB70

28-DIP, 55ns, L-pwr

28-DIP, 55ns, LL-pwr

28-DIP, 70ns, L-pwr

28-DIP, 70ns, LL-pwr

28-SOP, 55ns, L-pwr

28-SOP, 55ns, LL-pwr

28-SOP, 70ns, L-pwr

28-SOP, 70ns, LL-pwr

28-TSOP1 F, 55ns, L-pwr

28-TSOP1 F, 55ns, LL-pwr

28-TSOP1 F, 70ns, L-pwr

28-TSOP1 F, 70ns, LL-pwr

28-TSOP1 R, 55ns, L-pwr

28-TSOP1 R, 55ns, LL-pwr

28-TSOP1 R, 70ns, L-pwr

28-TSOP1 R, 70ns, LL-pwr

K6T0808C1D-GP70

K6T0808C1D-GF70

K6T0808C1D-TP70

K6T0808C1D-TF70

K6T0808C1D-RP70

K6T0808C1D-RF70

28-SOP, 70ns, L-pwr

28-SOP, 70ns, LL-pwr

28-TSOP1 F, 70ns, L-pwr

28-TSOP1 F, 70ns, LL-pwr

28-TSOP1 R, 70ns, L-pwr

28-TSOP1 R, 70ns, LL-pwr

FUNCTIONAL DESCRIPTION

1. X means don′t care (Must be in high or low states)

CS OE WE I/O Mode Power

HX1) X1) High-Z Deselected Standby

LH H High-Z Output Disabled Active

L L HDout Read Active

LX1) LDin Write Active

ABSOLUTE MAXIMUM RATINGS1)

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be

restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Item Symbol Ratings Unit Remark

Voltage on any pin relative to Vss VIN,VOUT -0.5 to 7.0 V-

Voltage on Vcc supply relative to Vss VCC -0.5 to 7.0 V-

Power Dissipation PD1.0 W-

Storage temperature TSTG -65 to 150 °C-

Operating Temperature TA0 to 70 °C K6T0808C1D-L

-40 to 85 °C K6T0808C1D-P

Soldering temperature and time TSOLDER 260°C, 10sec (Lead Only) - -

K6T0808C1D Family CMOS SRAM

Revision 1.0

November 1997

RECOMMENDED DC OPERATING CONDITIONS1)

Note:

1. Commercial Product : TA=0 to 70°C, otherwise specified

Industrial Product : TA=-40 to 85°C, otherwise specified

2. Overshoot : VCC+3.0V in case of pulse width≤30ns

3. Undershoot : -3.0V in case of pulse width≤30ns

4. Overshoot and undershoot are sampled, not 100% tested

Item Symbol Min Typ Max Unit

Supply voltage Vcc 4.5 5.0 5.5 V

Ground Vss 000V

Input high voltage VIH 2.2 -Vcc+0.5V2) V

Input low voltage VIL -0.53) -0.8 V

CAPACITANCE1) (f=1MHz, TA=25°C)

1. Capacitance is sampled not, 100% tested

Item Symbol Test Condition Min Max Unit

Input capacitance CIN VIN=0V -8pF

Input/Output capacitance CIO VIO=0V -10 pF

DC AND OPERATING CHARACTERISTICS

Item Symbol Test Conditions Min Typ Max Unit

Input leakage current ILI VIN=Vss to Vcc -1 -1µA

Output leakage current ILO CS=VIH or OE=VIH or WE=VIL, VIO=VSS to Vcc -1 -1µA

Operating power supply current ICC IIO=0mA, CS=VIL, VIN=VIH or VIL, Read -510 mA

Average operating current ICC1 Cycle time=1µs, 100% duty, IIO=0mA

CS≤0.2V, VIN≤0.2V, VIN≥Vcc -0.2V Read -2 5 mA

Write -20

ICC2 Cycle time=Min,100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL -45 60 mA

Output low voltage VOL IOL=2.1mA - - 0.4 V

Output high voltage VOH IOH=-1.0mA 2.4 - - V

Standby Current(TTL) ISB CS=VIH, Other inputs=VIH or VIL - - 1mA

Standby Current (CMOS) ISB1 CS≥Vcc-0.2V, Other inputs=0~Vcc Low Power -130 µA

Low Low Power -0.2 5µA

K6T0808C1D Family CMOS SRAM

Revision 1.0

November 1997

CL1)

1. Including scope and jig capacitance

AC OPERATING CONDITIONS

TEST CONDITIONS (Test Load and Test Input/Output Reference)

Input pulse level : 0.8 to 2.4V

Input rising and falling time : 5ns

Input and output reference voltage : 1.5V

Output load (See right) :CL=100pF+1TTL

CL=50pF+1TTL

AC CHARACTERISTICS (Vcc=4.5~5.5V, K6T0808C1D-L Family:TA=0 to 70°C, K6T0808C1D-P Family:TA=-40 to 85°C)

1. The parameter is tested with 50pF test load.

Parameter List Symbol Speed Bins Units

551)ns 70ns

Min Max Min Max

Read

Read cycle time tRC 55 -70 -ns

Address access time tAA -55 -70 ns

Chip select to output tCO -55 -70 ns

Output enable to valid output tOE -25 -35 ns

Chip select to low-Z output tLZ 10 -10 -ns

Output enable to low-Z output tOLZ 5-5-ns

Chip disable to high-Z output tHZ 020 030 ns

Output disable to high-Z output tOHZ 020 030 ns

Output hold from address change tOH 10 -10 -ns

Write

Write cycle time tWC 55 -70 -ns

Chip select to end of write tCW 45 -60 -ns

Address set-up time tAS 0-0-ns

Address valid to end of write tAW 45 -60 -ns

Write pulse width tWP 40 -50 -ns

Write recovery time tWR 0-0-ns

Write to output high-Z tWHZ 020 025 ns

Data to write time overlap tDW 25 -30 -ns

Data hold from write time tDH 0-0-ns

End write to output low-Z tOW 5-5-ns

DATA RETENTION CHARACTERISTICS

Item Symbol Test Condition Min Typ Max Unit

Vcc for data retention VDR CS≥Vcc-0.2V 2.0 -5.5 V

Data retention current IDR Vcc=3.0V, CS≥Vcc-0.2V L-Ver -115 µA

LL-Ver -0.2 3

Data retention set-up time tSDR See data retention waveform 0- - ms

Recovery time tRDR 5- -

K6T0808C1D Family CMOS SRAM

Revision 1.0

November 1997

Address

Data Out Previous Data Valid Data Valid

TIMMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)

tAA

tRC

tOH

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

Data Valid

High-Z

Address

Data out

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

tOH

tAA

tOLZ

tLZ tOHZ

tHZ

tRC

tOE

tCO

K6T0808C1D Family CMOS SRAM

Revision 1.0

November 1997

TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)

Address

tWC

tWR(4)

tAS(3)

tDW tDH

Data Valid

Data in

Data out High-Z High-Z

tCW(2)

tWP(1)

tAW

NOTES (WRITE CYCLE)

1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE

going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write

to the end of write.

2. tCW is measured from the CS going low to end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.

DATA RETENTION WAVE FORM

CS controlled

VCC

4.5V

2.2V

VDR

GND

Data Retention Mode

CS≥VCC - 0.2V

tSDR tRDR

TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)

Address

tCW(2) tWR(4)

tWP(1)

tDW tDH

tOW

tWHZ

Data Undefined

Data Valid

Data in

Data out

tWC

tAW

tAS(3)

K6T0808C1D Family CMOS SRAM

Revision 1.0

November 1997

PACKAGE DIMENSIONS Units: millimeter(inch)

1.65

28 PIN DUAL INLINE PACKAGE(600mil)

#28

13.60± 0.20

0.535± 0.008

36.32± 0.20

1.430± 0.008

( )

0.065 1.52± 0.10

0.060± 0.004

0.46± 0.10

0.018± 0.004

15.24

0.600

+0.10

MAX

36.72

1.446

0.25 -0.05

+0.004

0.010

-0.002

#14

#15

2.54

0.100

MAX

3.81± 0.20

0.150± 0.008

5.08

0.200

MIN

0.015

0.38 0.130± 0.012

3.30± 0.30

0~15°

28 PIN PLASTIC SMALL OUTLINE PACKAGE(450mil)

0~8°

#28

11.81± 0.30

0.465± 0.012

18.29± 0.20

0.720± 0.008

MAX

18.69

0.736

MAX

2.59± 0.20

0.102± 0.008

3.00

0.118

MIN

0.002

0.05

0.004 MAX

0.10 MAX

#15

0.41± 0.10

0.016± 0.004

#1 #14

0.89

( )

0.035

11.43

0.450

8.38± 0.20

0.330± 0.008

1.02± 0.20

0.040± 0.008

+0.10

0.15 -0.05

+0.004

0.006

-0.002

1.27

0.050

K6T0808C1D Family CMOS SRAM

Revision 1.0

November 1997

PACKAGE DIMENSIONS

28 PIN THIN SMALL OUTLINE PACKAGE TYPE1 (0813.4F)

#28

1.00± 0.10

0.039± 0.004

MAX

8.40

0.331

0.004 MAX

0.10 MAX

13.40± 0.20

0.528± 0.008

#15#14

+0.10

0.20 -0.05

+0.004

0.008

-0.002

0.55

0.0217

0.425

( )

0.017

MIN

0.05

0.002

MAX

1.20

0.047

8.00

0.315

#28

1.00± 0.10

0.039± 0.004

MAX

8.40

0.331

0.004 MAX

0.10 MAX

0.50

( )

0.020

11.80± 0.10

0.465± 0.004

0.45 ~0.75

0.018 ~0.030

13.40± 0.20

0.528± 0.008

#15#14

+0.10

0.15 -0.05

+0.004

0.006

-0.002

0~8°

0.425

( )

0.017

MIN

0.05

0.002

MAX

1.20

0.047

8.00

0.315

TYP

0.25

0.010

0.55

0.0217

+0.10

0.20 -0.05

+0.004

0.008

-0.002

28 PIN THIN SMALL OUTLINE PACKAGE TYPE1 (0813.4R)

0.50

( )

0.020

11.80± 0.10

0.465± 0.004

0.45 ~0.75

0.018 ~0.030

+0.10

0.15 -0.05

+0.004

0.006

-0.002

0~8°

TYP

0.25

0.010

Units: millimeter(inch)