LP3875EMP5.0NOPB - NATIONAL SEMICONDUCTOR

LP38691,LP38693

LP38691 LP38693 500mA Low Dropout CMOS Linear Regulators Stable with

Ceramic Output Capacitors

Literature Number: SNVS321I

LP38691

LP38693

June 27, 2011

500mA Low Dropout CMOS Linear Regulators

Stable with Ceramic Output Capacitors

General Description

The LP38691/3 low dropout CMOS linear regulators provide

tight output tolerance (2.0% typical), extremely low dropout

voltage (250 mV @ 500mA load current, VOUT = 5V), and ex-

cellent AC performance utilizing ultra low ESR ceramic output

capacitors.

The low thermal resistance of the LLP, SOT-223 and TO-252

packages allow the full operating current to be used even in

high ambient temperature environments.

The use of a PMOS power transistor means that no DC base

drive current is required to bias it allowing ground pin current

to remain below 100 µA regardless of load current, input volt-

age, or operating temperature.

Dropout Voltage: 250 mV (typ) @ 500mA (typ. 5V out).

Ground Pin Current: 55 µA (typ) at full load.

Precision Output Voltage: 2.0% (25°C) accuracy.

Features

■All LLP options are available as AEC-Q100 Grade 1

■2.0% output accuracy (25°C)

■Low dropout voltage: 250 mV @ 500mA (typ, 5V out)

■Wide input voltage range (2.7V to 10V)

■Precision (trimmed) bandgap reference

■Guaranteed specs for -40°C to +125°C

■1µA off-state quiescent current

■Thermal overload protection

■Foldback current limiting

■T0-252, SOT-223 and 6-Lead LLP packages

■Enable pin (LP38693)

Applications

■Hard Disk Drives

■Notebook Computers

■Battery Powered Devices

■Portable Instrumentation

Typical Application Circuits

20126501

20126502

Note: * Minimum value required for stability.

**LLP package devices only.

LP38691/LP38693 500mA Low Dropout CMOS Linear Regulators

Stable with Ceramic Output Capacitors

Connection Diagrams

20126503

TO-252, Top View

LP38691DT-X.X

20126504

SOT-223, Top View

LP38693MP-X.X

20126505

6-Lead LLP, Top View

LP38691SD-X.X

20126506

6-Lead LLP, Top View

LP38693SD-X.X

Pin Descriptions

Pin Description

VIN

This is the input supply voltage to the regulator. For LLP devices, both VIN pins must be tied together

for full current operation (250mA maximum per pin).

GND Circuit ground for the regulator. For the TO-252 and SOT-223 packages this is thermally connected

to the die and functions as a heat sink when the soldered down to a large copper plane.

SNS

Output sense pin allows remote sensing at the load which will eliminate the error in output voltage

due to voltage drops caused by the resistance in the traces between the regulator and the load. This

pin must be tied to VOUT.

VEN The enable pin allows the part to be turned ON and OFF by pulling this pin high or low.

VOUT Regulated output voltage

DAP LLP Only - The DAP (Exposed Pad) functions as a thermal connection when soldered to a copper

plane. See LLP MOUNTING section in Application Hints for more information.

www.national.com 2

LP38691/LP38693

Ordering Information

Output

Voltage

Order

Number Grade Package

Marking

Package

Type

Package

Drawing

Supplied

1.8V

LP38691SD-1.8 Standard L118B 6-Lead LLP SDE06A Reel of 1000 Units

LP38691SDX-1.8 Reel of 4500 Units

LP38691QSD-1.8 Automotive L256B 6-Lead LLP SDE06A Reel of 1000 Units

LP38691QSDX-1.8 Reel of 4500 Units

LP38691DT-1.8 Standard LP38691DT-1.8 TO-252 TD03B Rail of 75 Units

LP38691DTX-1.8 Reel of 2500 Units

LP38693SD-1.8 Standard L128B 6-Lead LLP SDE06A Reel of 1000 Units

LP38693SDX-1.8 Reel of 4500 Units

LP38693QSD-1.8 Automotive L260B 6-Lead LLP SDE06A Reel of 1000 Units

LP38693QSDX-1.8 Reel of 4500 Units

LP38693MP-1.8 Standard LJVB SOT-223 MP05A Reel of 1000 Units

LP38693MPX-1.8 Reel of 2000 Units

2.5V

LP38691SD-2.5 Standard L119B 6-Lead LLP SDE06A Reel of 1000 Units

LP38691SDX-2.5 Reel of 4500 Units

LP38691QSD-2.5 Automotive L257B 6-Lead LLP SDE06A Reel of 1000 Units

LP38691QSDX-2.5 Reel of 4500 Units

LP38691DT-2.5 Standard LP38691DT-2.5 TO-252 TD03B Rail of 75 Units

LP38691DTX-2.5 Reel of 2500 Units

LP38693SD-2.5 Standard L129B 6-Lead LLP SDE06A Reel of 1000 Units

LP38693SDX-2.5 Reel of 4500 Units

LP38693QSD-2.5 Automotive L261B 6-Lead LLP SDE06A Reel of 1000 Units

LP38693QSDX-2.5 Reel of 4500 Units

LP38693MP-2.5 Standard LJXB SOT-223 MP05A Reel of 1000 Units

LP38693MPX-2.5 Reel of 2000 Units

3.3V

LP38691SD-3.3 Standard L120B 6-Lead LLP SDE06A Reel of 1000 Units

LP38691SDX-3.3 Reel of 4500 Units

LP38691QSD-3.3 Automotive L258B 6-Lead LLP SDE06A Reel of 1000 Units

LP38691QSDX-3.3 Reel of 4500 Units

LP38691DT-3.3 Standard LP38691DT-3.3 TO-252 TD03B Rail of 75 Units

LP38691DTX-3.3 Reel of 2500 Units

LP38693SD-3.3 Standard L130B 6-Lead LLP SDE06A Reel of 1000 Units

LP38693SDX-3.3 Reel of 4500 Units

LP38693QSD-3.3 Automotive L262B 6-Lead LLP SDE06A Reel of 1000 Units

LP38693QSDX-3.3 Reel of 4500 Units

LP38693MP-3.3 Standard LJYB SOT-223 MP05A Reel of 1000 Units

LP38693MPX-3.3 Reel of 2000 Units

3 www.national.com

LP38691/LP38693

Output

Voltage

Order

Number Grade Package

Marking

Package

Type

Package

Drawing

Supplied

5.0V

LP38691SD-5.0 Standard L121B 6-Lead LLP SDE06A Reel of 1000 Units

LP38691SDX-5.0 Reel of 4500 Units

LP38691QSD-5.0 Automotive L259B 6-Lead LLP SDE06A Reel of 1000 Units

LP38691QSDX-5.0 Reel of 4500 Units

LP38691DT-5.0 Standard LP38691DT-5.0 TO-252 TD03B Rail of 75 Units

LP38691DTX-5.0 Reel of 2500 Units

LP38693SD-5.0 Standard L131B 6-Lead LLP SDE06A Reel of 1000 Units

LP38693SDX-5.0 Reel of 4500 Units

LP38693QSD-5.0 Automotive L263B 6-Lead LLP SDE06A Reel of 1000 Units

LP38693QSDX-5.0 Reel of 4500 Units

LP38693MP-5.0 Standard LJZB SOT-223 MP05A Reel of 1000 Units

LP38693MPX-5.0 Reel of 2000 Units

Automotive Grade (Q) product incorporates enhanced manufacturing and support processes for the automotive market, including defect detection methodologies.

Reliability qualification is compliant with the requirements and temperature grades defined in the AEC Q100 standard. Automotive Grade products are identified

with the letter Q. For more information go to: http://www.national.com/automotive

For LP38691 Ordering and Availability Information see: http://www.national.com/pf/LP/LP38691.html#Order

For LP38693 Ordering and Availability Information see: http://www.national.com/pf/LP/LP38693.html#Order

www.national.com 4

LP38691/LP38693

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Storage Temperature Range −65°C to +150°C

Lead Temp. (Soldering, 5 seconds) 260°C

ESD Rating (Note 3) 2 kV

Power Dissipation (Note 2) Internally Limited

V(max) All pins (with respect to GND) -0.3V to 12V

IOUT Internally Limited

Junction Temperature −40°C to +150°C

Operating Ratings

VIN Supply Voltage 2.7V to 10V

Operating Junction

Temperature Range

−40°C to +125°C

Electrical Characteristics Limits in standard typeface are for TJ = 25°C, and limits in boldface type apply over

the full operating temperature range. Unless otherwise specified: VIN = VOUT + 1V, CIN = COUT = 10 µF, ILOAD = 10mA. Min/Max

limits are guaranteed through testing, statistical correlation, or design.

Symbol Parameter Conditions Min Typ

(Note 4)Max Units

VOOutput Voltage Tolerance

-2.0 2.0

%VOUT

100 µA < IL < 0.5A

VO + 1V ≤ VIN ≤ 10V -4.0 4.0

ΔVO/ΔVIN Output Voltage Line Regulation

(Note 6)

VO + 0.5V ≤ VIN ≤ 10V

IL = 25mA 0.03 0.1 %/V

ΔVO/ΔILOutput Voltage Load Regulation

(Note 7)

1 mA < IL < 0.5A

VIN = VO + 1V 1.8 5%/A

VIN - VOUT Dropout Voltage (Note 8)

(VO = 2.5V)

IL = 0.1A

IL = 0.5A

430

145

725

(VO = 3.3V)

IL = 0.1A

IL = 0.5A

330

110

550

(VO = 5V)

IL = 0.1A

IL = 0.5A

250

100

450

IQQuiescent Current VIN ≤ 10V, IL =100 µA - 0.5A 55 100

µA

VEN ≤ 0.4V, (LP38693 Only) 0.001 1

IL(MIN) Minimum Load Current VIN - VO ≤ 4V 100

IFB Foldback Current Limit VIN - VO > 5V 350 mA

VIN - VO < 4V 850

PSRR Ripple Rejection VIN = VO + 2V(DC), with 1V(p-p) /

120Hz Ripple 55 dB

TSD Thermal Shutdown Activation

(Junction Temp)

160

°C

TSD (HYST) Thermal Shutdown Hysteresis

(Junction Temp)

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LP38691/LP38693

Symbol Parameter Conditions Min Typ

(Note 4)Max Units

enOutput Noise BW = 10Hz to 10kHz

VO = 3.3V 0.7 µV/

VO (LEAK) Output Leakage Current VO = VO(NOM) + 1V @ 10VIN 0.5 12 µA

VEN Enable Voltage (LP38693 Only) Output = OFF 0.4

Output = ON, VIN = 4V 1.8

Output = ON, VIN = 6V 3.0

Output = ON, VIN = 10V 4.0

IEN Enable Pin Leakage (LP38693

Only)

VEN = 0V or 10V, VIN = 10V -1 0.001 1 µA

Note 1: Absolute maximum ratings indicate limits beyond which damage to the component may occur. Operating ratings indicate conditions for which the device

is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications, see Electrical Characteristics. Specifications do not

apply when operating the device outside of its rated operating conditions.

Note 2: At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heatsink values (if a heatsink is used).

The junction-to-ambient thermal resistance ( θJ-A) for the TO-252 is approximately 90°C/W for a PC board mounting with the device soldered down to minimum

copper area (less than 0.1 square inch). If one square inch of copper is used as a heat dissipator for the TO-252, the θJ-A drops to approximately 50°C/W. The

SOT-223 package has a θJ-A of approximately 125°C/W when soldered down to a minimum sized pattern (less than 0.1 square inch) and approximately 70°C/W

when soldered to a copper area of one square inch. The θJ-A values for the LLP package are also dependent on trace area, copper thickness, and the number

of thermal vias used (refer to application note AN-1187 and the LLP MOUNTING section in this datasheet). If power dissipation causes the junction temperature

to exceed specified limits, the device will go into thermal shutdown.

Note 3: ESD is tested using the human body model which is a 100pF capacitor discharged through a 1.5k resistor into each pin.

Note 4: Typical numbers represent the most likely parametric norm for 25°C operation.

Note 5: If used in a dual-supply system where the regulator load is returned to a negative supply, the output pin must be diode clamped to ground.

Note 6: Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage.

Note 7: Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from 1mA to full load.

Note 8: Dropout voltage is defined as the minimum input to output differential required to maintain the output within 100mV of nominal value.

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LP38691/LP38693

Block Diagrams

20126507

FIGURE 1. LP38691 Functional Diagram (LLP)

20126508

FIGURE 2. LP38691 Functional Diagram (TO-252)

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LP38691/LP38693

20126509

FIGURE 3. LP38693 Functional Diagram (LLP)

20126510

FIGURE 4. LP38693 Functional Diagram (SOT-223)

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LP38691/LP38693

Typical Performance Characteristics Unless otherwise specified: TJ = 25°C, CIN = COUT = 10 µF, Enable

pin is tied to VIN (LP38693 only), VOUT = 1.8V, VIN = VOUT +1V, IL = 10mA.

Noise vs Frequency

20126535

Noise vs Frequency

20126536

Noise vs Frequency

20126537

Ripple Rejection

20126518

Ripple Rejection

20126520

Ripple Rejection

20126522

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LP38691/LP38693

Line Transient Response

20126524

Line Transient Response

20126526

Line Transient Response

20126528

Load Transient Response

20126542

Load Transient Response

20126544

VOUT vs Temperature (5.0V)

20126530

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LP38691/LP38693

VOUT vs Temperature (3.3V)

20126531

VOUT vs Temperature (2.5V)

20126532

VOUT vs Temperature (1.8V)

20126533

VOUT vs VIN (1.8V)

20126559

VOUT vs VIN, Power-Up

20126560

VOUT vs VEN, ON (LP38693 Only)

20126561

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LP38691/LP38693

VOUT vs VEN, OFF (LP38693 Only)

20126562

Enable Voltage vs Temperature

20126552

Load Regulation vs Temperature

20126553

Line Regulation vs Temperature

20126554

MIN VIN vs IOUT

20126557

Dropout Voltage vs IOUT

20126556

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LP38691/LP38693

Application Hints

EXTERNAL CAPACITORS

Like any low-dropout regulator, external capacitors are re-

quired to assure stability. These capacitors must be correctly

selected for proper performance.

INPUT CAPACITOR: An input capacitor of at least 1µF is re-

quired (ceramic recommended). The capacitor must be lo-

cated not more than one centimeter from the input pin and

returned to a clean analog ground.

OUTPUT CAPACITOR: An output capacitor is required for

loop stability. It must be located less than 1 centimeter from

the device and connected directly to the output and ground

pins using traces which have no other currents flowing

through them.

The minimum amount of output capacitance that can be used

for stable operation is 1µF. Ceramic capacitors are recom-

mended (the LP38691/3 was designed for use with ultra low

ESR capacitors). The LP38691/3 is stable with any output

capacitor ESR between zero and 100 Ohms.

ENABLE PIN (LP38693 only): The LP38693 has an Enable

pin (EN) which allows an external control signal to turn the

regulator output On and Off. The Enable On/Off threshold has

no hysteresis. The voltage signal must rise and fall cleanly,

and promptly, through the ON and OFF voltage thresholds.

The Enable pin has no internal pull-up or pull-down to estab-

lish a default condition and, as a result, this pin must be

terminated either actively or passively. If the Enable pin is

driven from a source that actively pulls high and low, the drive

voltage should not be allowed to go below ground potential or

higher than VIN. If the application does not require the Enable

function, the pin should be connected directly to the VIN pin.

Foldback Current Limiting: Foldback current limiting is built

into the LP38691/3 which reduces the amount of output cur-

rent the part can deliver as the output voltage is reduced. The

amount of load current is dependent on the differential voltage

between VIN and VOUT. Typically, when this differential volt-

age exceeds 5V, the load current will limit at about 350 mA.

When the VIN - VOUT differential is reduced below 4V, load

current is limited to about 850 mA.

SELECTING A CAPACITOR

It is important to note that capacitance tolerance and variation

with temperature must be taken into consideration when se-

lecting a capacitor so that the minimum required amount of

capacitance is provided over the full operating temperature

range.

Capacitor Characteristics

CERAMIC

For values of capacitance in the 10 to 100 µF range, ceramics

are usually larger and more costly than tantalums but give

superior AC performance for bypassing high frequency noise

because of very low ESR (typically less than 10 mΩ). How-

ever, some dielectric types do not have good capacitance

characteristics as a function of voltage and temperature.

Z5U and Y5V dielectric ceramics have capacitance that drops

severely with applied voltage. A typical Z5U or Y5V capacitor

can lose 60% of its rated capacitance with half of the rated

voltage applied to it. The Z5U and Y5V also exhibit a severe

temperature effect, losing more than 50% of nominal capac-

itance at high and low limits of the temperature range.

X7R and X5R dielectric ceramic capacitors are strongly rec-

ommended if ceramics are used, as they typically maintain a

capacitance range within ±20% of nominal over full operating

ratings of temperature and voltage. Of course, they are typi-

cally larger and more costly than Z5U/Y5U types for a given

voltage and capacitance.

TANTALUM

Solid Tantalum capacitors have good temperature stability: a

high quality Tantalum will typically show a capacitance value

that varies less than 10-15% across the full temperature

range of -40°C to +125°C. ESR will vary only about 2X going

from the high to low temperature limits.

REVERSE VOLTAGE

A reverse voltage condition will exist when the voltage at the

output pin is higher than the voltage at the input pin. Typically

this will happen when VIN is abruptly taken low and COUT con-

tinues to hold a sufficient charge such that the input to output

voltage becomes reversed. A less common condition is when

an alternate voltage source is connected to the output.

There are two possible paths for current to flow from the out-

put pin back to the input during a reverse voltage condition.

1) While VIN is high enough to keep the control circuity alive,

and the Enable pin (LP38693 only) is above the VEN(ON)

threshold, the control circuitry will attempt to regulate the out-

put voltage. If the input voltage is less than the programmed

output voltage, the control circuit will drive the gate of the pass

element to the full ON condition. In this condition, reverse

current will flow from the output pin to the input pin, limited

only by the RDS(ON) of the pass element and the output to input

voltage differential. Discharging an output capacitor up to

1000 μF in this manner will not damage the device as the

current will rapidly decay. However, continuous reverse cur-

rent should be avoided. When the Enable pin is low this

condition will be prevented.

2) The internal PFET pass element has an inherent parasitic

diode. During normal operation, the input voltage is higher

than the output voltage and the parasitic diode is reverse bi-

ased. However, when VIN is below the value where the control

circuity is alive, or the Enable pin is low (LP38693 only), and

the output voltage is more than 500 mV (typical) above the

input voltage the parasitic diode becomes forward biased and

current flows from the output pin to the input pin through the

diode. The current in the parasitic diode should be limited to

less than 1A continuous and 5A peak.

If used in a dual-supply system where the regulator output

load is returned to a negative supply, the output pin must be

diode clamped to ground to limit the negative voltage transi-

tion. A Schottky diode is recommended for this protective

clamp.

PCB LAYOUT

Good PC layout practices must be used or instability can be

induced because of ground loops and voltage drops. The in-

put and output capacitors must be directly connected to the

input, output, and ground pins of the regulator using traces

which do not have other currents flowing in them (Kelvin con-

nect).

The best way to do this is to lay out CIN and COUT near the

device with short traces to the VIN, VOUT, and ground pins. The

regulator ground pin should be connected to the external cir-

cuit ground so that the regulator and its capacitors have a

"single point ground".

It should be noted that stability problems have been seen in

applications where "vias" to an internal ground plane were

used at the ground points of the IC and the input and output

capacitors. This was caused by varying ground potentials at

these nodes resulting from current flowing through the ground

13 www.national.com

LP38691/LP38693

plane. Using a single point ground technique for the regulator

and it’s capacitors fixed the problem. Since high current flows

through the traces going into VIN and coming from VOUT,

Kelvin connect the capacitor leads to these pins so there is

no voltage drop in series with the input and output capacitors.

LLP MOUNTING

The SDE06A (No Pullback) 6-Lead LLP package requires

specific mounting techniques which are detailed in National

Semiconductor Application Note # 1187. Referring to the sec-

tion PCB Design Recommendations in AN-1187 (Page 5), it

should be noted that the pad style which should be used with

the LLP package is the NSMD (non-solder mask defined)

type. Additionally, it is recommended the PCB terminal pads

to be 0.2 mm longer than the package pads to create a solder

fillet to improve reliability and inspection.

The input current is split between two VIN pins, 1 and 6. The

two VIN pins must be connected together to ensure that the

device can meet all specifications at the rated current.

The thermal dissipation of the LLP package is directly related

to the printed circuit board construction and the amount of

additional copper area connected to the DAP.

The DAP (exposed pad) on the bottom of the LLP package is

connected to the die substrate with a conductive die attach

adhesive. The DAP has no direct electrical (wire) connection

to any of the pins. There is a parasitic PN junction between

the die substrate and the device ground. As such, it is strongly

recommend that the DAP be connected directly to the ground

at device lead 2 (i.e. GND). Alternately, but not recommend-

ed, the DAP may be left floating (i.e. no electrical connection).

The DAP must not be connected to any potential other than

ground.

For the LP38691SD and LP38693SD in the SDE06A 6-Lead

LLP package, the junction-to-case thermal rating, θJC, is

10.4°C/W, where the case is the bottom of the package at the

center of the DAP. The junction-to-ambient thermal perfor-

mance for the LP38691SD and LP38693SD in the SDE06A

6-Lead LLP package, using the JEDEC JESD51 standards is

summarized in the following table:

Board

Type

Thermal

Vias θJC θJA

JEDEC

2-Layer

JESD 51-3

None 10.4°C/W 237° C/W

JEDEC

4-Layer

JESD 51-7

1 10.4°C/W 74° C/W

2 10.4°C/W 60° C/W

4 10.4°C/W 49° C/W

6 10.4°C/W 45° C/W

RFI/EMI SUSCEPTIBILITY

RFI (radio frequency interference) and EMI (electromagnetic

interference) can degrade any integrated circuit’s perfor-

mance because of the small dimensions of the geometries

inside the device. In applications where circuit sources are

present which generate signals with significant high frequen-

cy energy content (> 1 MHz), care must be taken to ensure

that this does not affect the IC regulator.

If RFI/EMI noise is present on the input side of the regulator

(such as applications where the input source comes from the

output of a switching regulator), good ceramic bypass capac-

itors must be used at the input pin of the IC.

If a load is connected to the IC output which switches at high

speed (such as a clock), the high-frequency current pulses

required by the load must be supplied by the capacitors on

the IC output. Since the bandwidth of the regulator loop is less

than 100 kHz, the control circuitry cannot respond to load

changes above that frequency. This means the effective out-

put impedance of the IC at frequencies above 100 kHz is

determined only by the output capacitor(s).

In applications where the load is switching at high speed, the

output of the IC may need RF isolation from the load. It is

recommended that some inductance be placed between the

output capacitor and the load, and good RF bypass capacitors

be placed directly across the load.

PCB layout is also critical in high noise environments, since

RFI/EMI is easily radiated directly into PC traces. Noisy cir-

cuitry should be isolated from "clean" circuits where possible,

and grounded through a separate path. At MHz frequencies,

ground planes begin to look inductive and RFI/ EMI can cause

ground bounce across the ground plane. In multi-layer PCB

applications, care should be taken in layout so that noisy

power and ground planes do not radiate directly into adjacent

layers which carry analog power and ground.

OUTPUT NOISE

Noise is specified in two ways: Spot Noise or Output Noise

Density is the RMS sum of all noise sources, measured at

the regulator output, at a specific frequency (measured with

a 1Hz bandwidth). This type of noise is usually plotted on a

curve as a function of frequency. Total Output Noise or

Broad-Band Noise is the RMS sum of spot noise over a

specified bandwidth, usually several decades of frequencies.

Attention should be paid to the units of measurement. Spot

noise is measured in units µV/root-Hz or nV/root-Hz and total

output noise is measured in µV(rms)

The primary source of noise in low-dropout regulators is the

internal reference. Noise can be reduced in two ways: by in-

creasing the transistor area or by increasing the current drawn

by the internal reference. Increasing the area will decrease

the chance of fitting the die into a smaller package. Increasing

the current drawn by the internal reference increases the total

supply current (ground pin current).

www.national.com 14

LP38691/LP38693

Physical Dimensions inches (millimeters) unless otherwise noted

6-lead, LLP Package

NS Package Number SDE06A

TO-252 Package

NS Package Number TD03B

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LP38691/LP38693

SOT-223 Package

NS Package Number MP05A

www.national.com 16

LP38691/LP38693

Notes

17 www.national.com

LP38691/LP38693

Notes

LP38691/LP38693 500mA Low Dropout CMOS Linear Regulators

Stable with Ceramic Output Capacitors

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