1 of 51 June 1, 2012
2012 I ntegrated Devi ce Technology, Inc. DSC 6930
®
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
Device Overview
The 89HPES24T3G2 is a member of IDT’ s PRE CISE™ family of PCI
Express® switching solutions. The PES24T3G2 is a 24-lane, 3-port
Gen2 peripheral chip that performs PCI Express base switching with a
feature set optimized for high performance applications such as servers,
storage, and communications systems. It provides connectivity and
switching functions between a PCI Express upstream port and two
downstream ports and supports switching between downstream ports.
Features
◆High Performance PCI Express Switch
– Twenty-four 5 Gbps Gen2 PCI Ex press lanes supporting
5 Gbps and 2.5 Gbps operation
– Up to three switch ports
– Support for Max Payload Size up to 2048 bytes
– Supports one virtual channel and eight traffic classes
– Fully compliant with PCI Express bas e specification Revision
2.0
◆Flexible Architecture with Numerous Configuration Options
– Automatic per port link width negotiation to x8, x4, x2, or x1
– Automatic lane reversal on all ports
– Automatic polarity inversion
– Supports in-band hot-plug presence detect capability
– Supports external signal for hot plug event notification allowing
SCI/SMI generation for legacy operating systems
– Dynamic link width reconfiguration for power/performance
optimization
– Configurable downstream port PCI-to-PCI bridge device
numbering
– Crosslink support
– Supports ARI forwarding defined in the Alternative Routing-ID
Interpretation (ARI) ECN for virtualized and non-virtualized
environments
– Ability to load device configuration from serial EEPROM
◆Legacy Support
– PCI compatible INTx emulation
– Supports bus locked transactions, allowing use of PCI Express
with legacy software
◆Highly Integrated Solution
– Requires no external components
– Incorporates on-chip internal memory for packet buf fering and
queueing
– Integrates twenty-four 5 Gbps / 2.5 Gbps embedded SerDes,
8B/10B encoder/decoder (no separate transceivers needed)
◆Reliability, Availability, and Serviceability (RAS) Features
– Ability to disable peer-to-peer communications
– Supports ECRC and Advanced Error Reporting
– All internal data and control RAMs are SECDED ECC
protected
– Supports PCI Express hot-plug on all downstream ports
– Supports upstream port hot-plug
Block Diagram
Figure 1 Internal Block Diagram
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
...
Multiplexer / Demultiplexer
3-Port Sw itch C ore / 24 Gen2 PCI Express Lanes
Frame Buf fer Route Table Port
Arbitration Scheduler
Tran sa ction Layer
Data Link Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
...
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
...
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
89HPES24T3G2
Data Sheet
24-Lan e 3 - Port
Gen2 PCI Express® Switch
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IDT 89HPES24T3G2 Data Sheet
– Hot-swap capable I/O
– External Serial EEPROM contents are checksum protected
– Supports PCI Express Device Serial Number Capability
– Capability to monitor link reliability and autonomously change
link speed to prevent link instability
◆Power Management
– Utilizes advanced low-power design techniques to achieve low
typical power consumption
– Support PCI Power Management Interface specification (PCI-
PM 1.1)
• Supports device power management states: D0, D3hot and
D3cold
– Support for PCI Express Active State Power Management
(ASPM) link state
• Supports link power management states: L0, L0s, L1, L2/L3
Ready and L3
– Supports PCI Express Power Budgeting Capability
– Configurable SerDes power consumption
• Supports optional PCI-Express SerDes T ransmit Low-Swing
Voltage Mode
• Supports numerous SerDes Transmit Voltage Margin
settings
– Unused SerDes are disabled
◆Testability and Debug Features
– Per port link up and activity status outputs available on I/O
expander outputs
– Built in SerDes 8-bit and 10-bit pseudo-random bit stream
(PRBS) generators
– Numerous SerDes test modes, including a PRBS Master
Loopback mode for in-system link testing
– Ability to read and write any internal register via SMBus and
JTAG interfaces, including SerDes internal controls
– Per port statistics and performa nce counters, as well as propri-
etary link status registers
◆General Purpose Input/Output Pins
– Each pin may be individually configured as an input or output
– Each pin may be individually configured as an interrupt input
– Some pins have selectable alternate functions
◆Option A Package: 19mm x 19mm 324-ball Flip Chip BGA
with 1mm ball spacing
◆Option B Package: 27mm x 27mm 676-ball Flip Chip BGA
with 1mm ball spacing
Product Description
Utilizing standard PCI Express interconnect, the PES24T3G2
provides the most efficient I/O connectivity solution for applications
requiring high throughput, low latency, and simple board layout with a
minimum number of board layers. It provides connectivity for up to 3
ports across 24 integrated serial lanes. Each lane provides 5 Gbps of
bandwidth in both directions and is fully compliant with PCI Express
Base Specification, Revision 2.0, including operation in 5 Gbps, 2.5
Gbps, and mixed 5 Gbps / 2.5Gbps modes.
The PES24T3G2 is based on a flexible and efficient layered architec-
ture. The PCI Express layer consists of SerDes, Physical, Data Link and
Transaction layers in compliance with PCI Express Base specification
Revision 2.0. The PES24T3G2 can operate either as a store and
forward or cut-through switch and is designed to switch memory and I/O
transactions. It supports eight Traffic Classes (TCs) and one Virtual
Channel (VC) with sophisticated resource management to enable effi-
cient switching and I/O connectivity for servers, storage, and embedded
processors with limited connectivity.
Figure 2 I/O Expansion Application
SMBus Interface
The PES24T3G2 contains two SMBus interfaces. The slave inter-
face provides full access to the configuration registers in the
PES24T3G2, allowing every configuration register in the device to be
read or written by an external agent. The master interface allows the
default configuration register values of the PES24T3G2 to be over-
ridden following a reset with values programmed in an external serial
EEPROM. The master interface is also used by an external Hot-Plug I/O
expander.
Six pins make up each of the two SMBus interfaces. These pins
consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus
address pins. In the slave interface, these address pins allow the
SMBus address to which the device responds to be configured. In the
master interface, these address pins allow the SMBus address of the
serial configuration EEPROM from which data is loaded to be config-
ured. The SMBus address is set up on negation of PERSTN by
sampling the corresponding address pins. When the pins are sampled,
the resulting address is assigned as shown in Table 1.
Note: MSMBADDR and SSMBADDR address pins are not
available in the 19mm package. The MSMBADDR address is
hardwired to 0x50, and the SSMBADDR address is hardwired
to 0x77.
Memory
Memory
Memory
Processor
Memory
North
Bridge
PES24T3G2
I/O Dual
10GbE
I/O
SATA I/O
SATA
PCI Express
Slot
Processor
x8
x8 x8
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IDT 89HPES24T3G2 Data Sheet
As shown in Figure 3, the master and slave SMBuses may be us ed in a unified or split configuration. In the unified configuration, s hown in Figure
3(a), the master and slave SMBuses are ti ed together and the PES24T3G2 acts both as a SMBus master as well as a SMBus slave on this bus. This
requires that the SMBus master or processor that has access to PES24T3G2 registers supports SMBus arbitration. In some systems, this SMBus
master interface may be implemented using general purpose I/O pins on a processor or micro controller, and may not support SMBus arbitration. To
support these systems, the PES24T3G2 may be configured to operate in a split configuration as shown in Figure 3(b).
In the split configuration, the master and s lave SMBuses operate as two independent buses and thus multi-master arbitration is never required.
The PES24T3G2 supports reading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system programming of
the serial EEPROM.
Figure 3 SMBus Interface Configuration Examples
Hot-Plug Interface
The PES24T3G2 supports PCI Express Ho t-Plug on each downstream port. To reduce the number of pins required on the device, the PES24T3G2
utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configura-
tion, whenever the state of a Hot-Plug output needs to be modified, the PES24T3G2 generates an SMBus transaction to the I/O expander with the
new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXP INTN
input pin (alternate function of GPIO) of the PES24T3G2. In response to an I/O expander interrupt, the PES24T3G2 generates an SMBus transaction
to read the state of all of the Hot-Plug inputs from the I/O expander.
General Pur pose Input/Output
The PES24T3G2 provides General Purpose Input/Output (GPIO) pins (7 pins in the 19mm package and 11 pins in the 27mm package) that may be
used by the system designer as bit I/O ports. Each GPIO pin may be confi gured independently as an input or output through software control. Many
GPIO pins are shared with other on-chip functions. These alternate functions may be enabled via software, S MBus slave interface, or serial configura-
tion EEPROM.
Bit Slave
SMBus
Address
Master
SMBus
Address
1 SSMBADDR[1] MSMBADDR[1]
2 SSMBADDR[2] MSMBADDR[2]
3 SSMBADDR[3] MSMBADDR[3]
4 0 MSMBADDR[4]
5 SSMBADDR[5] 1
61 0
71 1
Table 1 Master and Slave SMBus Address Assignment for 27x27mm Package
Processor
PES24T3G2
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
SMBus
Master
Other
SMBus
Devices
Serial
EEPROM
Processor
PES24T3G2
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
SMBus
Master
Other
SMBus
Devices
Serial
EEPROM
... ...
(a) Unified Configuration and Ma nageme nt Bus (b) Split Configuration and Management Buses
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IDT 89HPES24T3G2 Data Sheet
Pin Description
The following tables list the functions of the pins provided on the PES24T3G2. Some of the functions listed may be multiplexed onto the same pin.
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Note: In the PES24T3G2, the two downstream ports are labeled port 2 and port 4.
Signal Type Name/Description
PE0RP[7:0]
PE0RN[7:0] IPCI Express Port 0 Serial Data Receive. Differential PCI Express receive
pairs for port 0. Port 0 is the upstream port.
PE0TP[7:0]
PE0TN[7:0] OPCI Express Port 0 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 0. Port 0 is the upstream port.
PE2RP[7:0]
PE2RN[7:0] IPCI Express Port 2 Serial Data Receive. Differential PCI Express receive
pairs for port 2.
PE2TP[7:0]
PE2TN[7:0] OPCI Express Port 2 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 2.
PE4RP[7:0]
PE4RN[7:0] IPCI Express Port 4 Serial Data Receive. Differential PCI Express receive
pairs for port 4.
PE4TP[7:0]
PE4TN[7:0] OPCI Express Port 4 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 4.
PEREFCLKP
PEREFCLKN IPCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is determined by the REFCLKM signal.
REFCLKM1
1. REFCLKM is not available in the 19mm package and frequency is set at 100MHz.
IPCI Express Reference Clock Mode Select. This signal selects the fre-
quency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
This pin should be static and not change following the negation of
PERSTN.
Table 2 PCI Express Interface Pins
Signal Type Name/Description
MSMBADDR[4:1]1IMaster SMBus Address. These pins determine the SMBus address of the
serial EEPROM from which configuration information is loaded.
MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize
transfers on the master SMBus.
MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the mas-
ter SMBus.
SSMBADDR[5,3:1]2ISlave SMBus Address. These pins determine the SMBus address to
which the slave SMBus interface responds.
SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize trans-
fers on the slave SMBus.
Table 3 SMBus Interface Pins (Part 1 of 2)
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IDT 89HPES24T3G2 Data Sheet
SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave
SMBus.
1. MSMBADDR pins are not available in the 19mm package. Address hardwired to 0x50.
2. SSMBADDR pins are not available in the 19mm package. Address hardwired to 0x77.
Signal Type Name/Description
GPIO[0] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P2RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 2
GPIO[1] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P4RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 4
GPIO[2] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN0
Alternate function pin type: Input
Alternate function: I/O Expander interrupt 0 input
GPIO[3]1
1. GPIO pins 3, 4, 5, 6 are not available in the 19mm package.
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN1
Alternate function pin type: Input
Alternate function: I/O Expander interrupt 1 input
GPIO[4]1I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN2
Alternate function pin type: Input
Alternate function: I/O Expander interrupt 2 input
GPIO[5]1I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[6]1I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[7] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: GPEN
Alternate function pin type: Output
Alternate function: General Purpose Event (GPE) output
GPIO[8] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[9] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[10] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Table 4 General Purpose I/O Pins
Signal Type Name/Description
Table 3 SMBus Interface Pins (Part 2 of 2)
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IDT 89HPES24T3G2 Data Sheet
Signal Type Name/Description
CCLKDS I Common Clock Downstream. The assertion of this pin indicates that all
downstream ports are using the same clock source as that provided to
downstream devices.This bit is used as the initial value of the Slot Clock
Configuration bit in all of the Link Status Registers for downstream ports.
The value may be overridden by modifying the SCLK bit in each down-
stream port’s PCIELSTS register.
CCLKUS I Common Clock Upstream. The assertion of this pin indicates that the
upstream port is using the same clock source as the upstream device. This
bit is used as the initial value of the Slot Clock Configuration bit in the Link
Status Register for the upstream port. The value may be overridden by
modifying the SCLK bit in the P0_PCIELSTS register.
MSMBSMODE1
1. MSMBSMODE is not available in the 19mm package, resulting in the master SMBus operating only at 400 KHz.
IMaster SMBus Slow Mode. The assertion of this pin indicates that the
master SMBus should operate at 100 KHz instead of 400 KHz. This value
may not be overridden.
PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside
PES24T3G2 and initiates a PCI Express fundamental reset.
RSTHALT2
2. RSTHALT is not available in the 19mm package.
IReset Halt. When this signal is asserted during a PCI Express fundamental
reset, PES24T3G2 executes the reset procedure and remains in a reset
state with the Master and Slave SMBuses active. This allows software to
read and write registers internal to the device before normal device opera-
tion begins. The device exits the reset state when the RSTHALT bit is
cleared in the SWCTL register by an SMBus master.
SWMODE[2:0] I Switch Mode. These configuration pins determine the PES24T3G2 switch
operating mode.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM initialization
0x2 - through 0x7 Reserved
These pins should be static and not change following the negation of
PERSTN.
Table 5 System Pins
Signal Type Name/Description
JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data
into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the system clock with a nominal 50% duty cycle.
JTAG_TDI I JTAG Data Input. This is the serial data input to the boundary scan logic or
JTAG Controller.
JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary
scan logic or JTAG Controller. When no data is being shifted out, this signal
is tri-stated.
JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the
boundary scan logic or JTAG Controller.
Table 6 Test Pins (Part 1 of 2)
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IDT 89HPES24T3G2 Data Sheet
JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary
scan logic and JTAG TAP Controller. An external pull-up on the board is
recommended to meet the JTAG specification in cases where the tester
can access this signal. However, for systems running in functional mode,
one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
Signal Type Name/Description
REFRES0,
REFRES1 I/O Port 0 External Reference Resistors. Provides a reference for the Port 0
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-
tor should be connected from these pins to ground.
REFRES2,
REFRES3 I/O Port 2 External Reference Resistors. Provides a reference for the Port 2
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-
tor should be connected from these pins to ground.
REFRES4,
REFRES5 I/O Port 4 External Reference Resistors. Provides a reference for the Port 4
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-
tor should be connected from these pins to ground.
VDDCORE I Core VDD. Power supply for core logic.
VDDI/O I I/O VDD. LVTTL I/O buffer power supply.
VDDPEA I PCI Express Analog Power. Serdes analog power supply (1.0V).
VDDPEHA I PCI Express Analog High Power. Serdes analog power supply (2.5V).
VDDPETA I PCI Express Transmitter Analog Voltage. Serdes transmitter analog
power supply (1.0V).
VSS IGround.
Table 7 Power, Ground, and SerDes Resistor Pins
Signal Type Name/Description
Table 6 Test Pins (Part 2 of 2)
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IDT 89HPES24T3G2 Data Sheet
Pin Characteristics
Note: Some input pads of the PES24T3G2 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate
levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left
floating can cause a slight increase in power consumption.
Function Pin Name Type Buffer I/O
Type Internal
Resistor1Notes
PCI Express Inter-
face PE0RN[7:0] I PCIe
differential2Serial Link
PE0RP[7:0] I
PE0TN[7:0] O
PE0TP[7:0] O
PE2RN[7:0] I
PE2RP[7:0] I
PE2TN[7:0] O
PE2TP[7:0] O
PE4RN[7:0] I
PE4RP[7:0] I
PE4TN[7:0] O
PE4TP[7:0] O
PEREFCLKN I HCSL Diff. Clock
Input Refer to Table 9
PEREFCLKP I
REFCLKM3I LVTTL Input pull-down
SMBus MSMBADDR[4:1]4I LVTTL Input pull-down
MSMBCLK I/O STI5pull-up on board
MSMBDAT I/O STI pull-up on board
SSMBADDR[5,3:1]4I Input pull-up
SSMBCLK I/O STI pull-up on board
SSMBDAT I/O STI pull-up on board
General Purpose I/O GPIO[10:0]6I/O LVTTL STI,
High Drive pull-up
System Pins CCLKDS I LVTTL Input pull-up
CCLKUS I Input pull-up
MSMBSMODE7I Input pull-down
PERSTN I STI
RSTHALT7I Input pull-down
SWMODE[2:0] I Input pull-down
EJTAG / JTAG JTAG_TCK I LVTTL STI pull-up
JTAG_TDI I STI pull-up
JTAG_TDO O
JTAG_TMS I STI pull-up
JTAG_TRST_N I STI pull-up
Table 8 Pin Characteristics (Part 1 of 2)
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IDT 89HPES24T3G2 Data Sheet
SerDes Reference
Resistors REFRES0 I/O Analog
REFRES1 I/O
REFRES2 I/O
REFRES3 I/O
REFRES4 I/O
REFRES5 I/O
1. Internal resistor values under typical operating conditions are 92K Ω for pull-up and 90K Ω for pull-down.
2. All receiver pins set the DC common mode voltage to ground. All transmitters must be AC coupled to the media.
3. REFCLKM pin is not available in the 19mm package.
4. SMBus address pins are not available in the 19mm package.
5. Schmitt Trigger Input (STI).
6. GPIO pins 3, 4, 5, 6 are not available in the 19mm package.
7. MSMBSMODE and RSTHALT are not available in the 19mm package.
Function Pin Name Type Buffer I/O
Type Internal
Resistor1Notes
Table 8 Pin Characteristics (Part 2 of 2)
10 of 51 June 1, 2012
IDT 89HPES24T3G2 Data Sheet
Logic Diagram — PES24T3G2
Figure 4 PES24T3G2 Logic Diagram
Note: The following pins are not available in the 19mm package: REFCLKM, MSMBADDR, SSMBADDR, MSMBSMODE, RSTHALT,
GPIO[6:3].
Reference
Clocks PEREFCLKP
PEREFCLKN
JTAG_TCK
GPIO[10:0]
11 General Purpose
I/O*
VDDCORE
VDDI/O
VDDPEA Power/Ground
MSMBADDR[4:1]
MSMBCLK
MSMBDAT
4
SSMBADDR[5,3:1]
SSMBCLK
SSMBDAT
4
Master
SMBus Interface
Slave
SMBus Interface
CCLKUS
RSTHALT
System
Pins
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
JTAG Pins
VSS
SWMODE[2:0] 3
CCLKDS
PERSTN
REFCLKM
MSMBSMODE
PE0RP[0]
PE0RN[0]
PE0RP[7]
PE0RN[7]
PCI Express
Switch
SerDes Input
PE0TP[0]
PE0TN[0]
PE0TP[7]
PE0TN[7]
PCI Expres s
Switch
SerDes Output
...
Port 0 Port 0
...
PE2RP[0]
PE2RN[0]
PE2RP[7]
PE2RN[7]
PCI Express
Switch
SerDes Input
PE2TP[0]
PE2TN[0]
PE2TP[7]
PE2TN[7]
PCI Expres s
Switch
SerDes Output
...
Port 2 Port 2
...
PE4RP[0]
PE4RN[0]
PE4RP[7]
PE4RN[7]
PCI Express
Switch
SerDes Input
PE4TP[0]
PE4TN[0]
PE4TP[7]
PE4TN[7]
PCI Expres s
Switch
SerDes Output
...
Port 4 Port 4
...
PES24T3G2
REFRES0
SerDes
Reference
Resistors
REFRES2
REFRES4
REFRES5
VDDPEHA
Reference Clock
Frequency Selection
REFRES1
REFRES3
VDDPETA
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IDT 89HPES24T3G2 Data Sheet
System Clock Pa rameters
Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 15.
AC Timing Characteristics
Parameter Description Condition Min Typical Max Unit
RefclkFREQ Input reference clock frequency range 100 1251
1. The input clock frequency will be either 100 or 125 MHz depending on signal REFCLKM. Frequency is set at 100 MHz in the 19mm package.
MHz
TC-RISE Rising edge rate Differential 0.6 4 V/ns
TC-FALL Falling edge rate Differential 0.6 4 V/ns
VIH Differential input high voltage Differential +150 mV
VIL Differential input low voltage Differential -150 mV
VCROSS Absolute single-ended crossing point
voltage Single-ended +250 +550 mV
VCROSS-DELTA Variation of VCROSS over all rising clock
edges Single-ended +140 mV
VRB Ring back voltage margin Differential -100 +100 mV
TSTABLE Time before VRB is allowed Differential 500 ps
TPERIOD-AVG Average clock period accuracy -300 2800 ppm
TPERIOD-ABS Absolute period, including spread-spec-
trum and jitter 9.847 10.203 ns
TCC-JITTER Cycle to cycle jitter 150 ps
VMAX Absolute maximum input voltage +1.15 V
VMIN Absolute minimum input voltage -0.3 V
Duty Cycle Duty cycle 40 60 %
Rise/Fall Matching Single ended rising Refclk edge rate ver-
sus falling Refclk edge rate 20 %
ZC-DC Clock source output DC impedance 40 60 Ω
Table 9 Input Clock Requirements
Parameter Description Gen 1 Gen 2 Units
Min1Typ1Max1Min1Typ1Max1
PCIe Transmit
UI Unit Interval 399.88 400 400.12 199.94 200 200.06 ps
TTX-EYE Minimum Tx Eye Width 0.75 0.75 UI
TTX-EYE-MEDIAN-to-
MAX-JITTER Maximum time between the jitter median and maximum
deviation from the median 0.125 UI
TTX-RISE, TTX-FALL TX Rise/Fall Time: 20% - 80% 0.125 0.15 UI
TTX- IDL E - MIN Minimum time in idle 20 20 UI
Table 10 PCIe AC Timing Characteristics (Part 1 of 2)
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IDT 89HPES24T3G2 Data Sheet
TTX-IDLE-SET-TO-IDLE Maximum time to transition to a valid Idle after sending
an Idle ordered set 88 ns
TTX-IDLE-TO-DIFF-
DATA Maximum time to transition from valid idle to diff data 8 8 ns
TTX-SKEW Transmitter data skew between any 2 lanes 1.3 1.3 ns
TMIN-PULSED Minimum Instantaneous Lone Pulse Width NA 0.9 UI
TTX-HF-DJ-DD Transmitter Deterministic Jitter > 1.5MHz Bandwidth NA 0.15 UI
TRF-MISMATCH Rise/Fall Time Differential Mismatch NA 0.1 UI
PCIe Receive
UI Unit Interval 399.88 400 400.12 199.94 200.06 ps
TRX-EYE (with jitter) Minimum Receiver Eye Width (jitter tolerance) 0.4 0.4 UI
TRX-EYE-MEDIUM TO
MAX JITTER Max time between jitter median & max deviation 0.3 UI
TRX-SKEW Lane to lane input skew 20 8 ns
TRX-HF-RMS 1.5 — 100 MHz RMS jitter (common clock) NA 3.4 ps
TRX-HF-DJ-DD Maximum tolerable DJ by the receiver (common clock) NA 88 ps
TRX-LF-RMS 10 KHz to 1.5 MHz RMS jitter (common clock) NA 4.2 ps
TRX-MIN-PULSE Minimum receiver instantaneous eye width NA 0.6 UI
1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 2.0
Signal Symbol Reference
Edge Min Max Unit Timing
Diagram
Reference
GPIO
GPIO[10:0]1
1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if
they are asynchronous. Note that GPIO{6:3} pins are not available in the 19mm package.
Tpw2
2. The values for this symbol were determined by calculation, not by testing.
None 50 — ns
Table 11 GPIO AC Timing Characteristics
Parameter Description Gen 1 Gen 2 Units
Min1Typ1Max1Min1Typ1Max1
Table 10 PCIe AC Timing Characteristics (Part 2 of 2)
13 of 51 June 1, 2012
IDT 89HPES24T3G2 Data Sheet
Figure 5 JTAG AC Timing Waveform
Signal Symbol Reference
Edge Min Max Unit Timing
Diagram
Reference
JTAG
JTAG_TCK T per_1 6a none 50.0 — ns See Figure 5.
Thigh_16a,
Tlow_16a 10.0 25.0 ns
JTAG_TMS1,
JTAG_TDI
1. The JT AG specific ation, IEEE 1149.1, re commend s that JTAG _TMS sho uld be held a t 1 while the signal app lied at JTAG _TRST_N
changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK
when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state.
Tsu_16b JTAG_TCK rising 2.4 — ns
Thld_16b 1.0 — ns
JTAG_TDO Tdo_16c JTAG_TCK falling — 20 ns
Tdz_16c2
2. The values for this symbol were determined by calculation, not by testing.
—20ns
JTAG_TRST_N Tpw_16d2none 25.0 — ns
Table 12 JTAG AC Timing Characteristics
Tpw_16d
Tdz_16cTdo_16c
Thld_16b
Tsu_16b
Thld_16b
Tsu_16b
Tlow_16aTlow_16a Tper_16a
Thigh_16a
JTAG_TCK
JTAG_TDI
JTAG_TMS
JTAG_TDO
JTAG_TRST_N
14 of 51 June 1, 2012
IDT 89HPES24T3G2 Data Sheet
Recommended Operating Supply Voltages
Absolute Maxim um Voltage Rati ng
Warning: For proper and reliable operation in adherence with this data sheet, the device should not exceed the recommended operating voltages
in Table 13. The absolute maximum operating voltages in Table 14 are offered to provide guidelines for voltage excursions outside the recommended
voltage ranges. Device functionality is not guarant eed at these c onditions and sustained operation at these values or any exposure to voltages outside
the maximum range may adversely affect device functionality and reliability.
Power-Up/Power-Down Sequence
During power supply ramp-up, V DDCORE must remain at least 1.0V below VDDI/O at all times. There are no other power-up sequence require-
ments for the various operating supply voltages.
The power-down sequence can occur in any order.
Recommended Operating Temperature
Symbol Parameter Minimum Typical Maximum Unit
VDDCORE Internal logic supply 0.9 1.0 1.1 V
VDDI/O I/O supply except for SerDes LVPECL/CML 3.135 3.3 3.465 V
VDDPEA1
1. VDDPEA and VDDPETA should have no more than 25mVpeak-peak AC power supply noise superimposed on the 1.0V nominal DC
value.
PCI Express Analog Power 0.95 1.0 1.1 V
VDDPEHA2
2. VDDPEHA should have no more than 50mVpeak-peak AC power supply noise superimposed on the 2.5V nominal DC value.
PCI Express Analog High Power 2.25 2.5 2.75 V
VDDPETA1PCI Express Transmitter Analog Voltage 0.95 1.0 1.1 V
VSS Common ground 0 0 0 V
Table 13 PES24T3G2 Operating Voltages
Core Supply PCIe Analog
Supply PCIe Analog
High Supp l y
PCIe
Transmitter
Supply I/O Sup pl y
1.5V 1.5V 4.6V 1.5V 4.6V
Table 14 PES24T3G2 Absolute Maximum Voltage Rating
Grade Temperature
Commercial 0°C to +70°C Ambient
Industrial -40°C to +85°C Ambient
Table 15 PES24T3G2 Operating Temperatures
15 of 51 June 1, 2012
IDT 89HPES24T3G2 Data Sheet
Po wer Consumption
Typical power is measured under the follow ing conditions: 25° C Am bient, 35% total link usage on all ports, ty pical voltages defined in Table 13
(and also listed below).
Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in
Table 13 (and also listed below).
Number of Active
Lanes per Port
Core Supply PCIe Analog
Supply PCIe Analog
High Supply PCIe Termin-
ation Sup pl y I/O Supply Total
Typ
1.0V Max
1.1V Typ
1.0V Max
1.1V Typ
2.5V Max
2.75V Typ
1.0V Max
1.15V Typ
3.3V Max
3.465V Typ
Power Max
Power
8/8/8
(Full Swing) mA 1010 1260 1384 1600 161 176 541 600 3 5
Watts 1.01 1.39 1.38 1.76 0.40 0.48 0.54 0.66 0.010 0.017 3.35 4.31
88/8
(Half Swing) mA 1010 1260 1190 1376 161 176 281 312 3 5
Watts 1.01 1.39 1.19 1.51 0.40 0.48 0.28 0.34 0.010 0.017 2.89 3.74
Table 16 PES24T3G2 Power Consumption
16 of 51 June 1, 2012
IDT 89HPES24T3G2 Data Sheet
Thermal Considerations — Option A Package
This section describes thermal considerations for the PES24T3G2 (19mm2 FCBGA324 package). The data in Table 17 below contains information
that is relevant to the thermal performance of the PES24T3G2 switch.
Thermal Considerations — Option B Package
This section describes thermal considerations for the PES24T3G2 (27mm2 FCBGA676 package). The data in Table 18 below contains information
that is relevant to the thermal performance of the PES24T3G2 switch.
Note: It is important for the reliability of this device in any user environment that the junction temperature not exceed the TJ(max) value
specified in Table 17. Consequently, the effective junction to ambient thermal resistance (θJA) for the worst case scenario must be
maintained below the value determined by the formula:
θ
JA = (TJ(max) - TA(max))/P
Given that the values of TJ(max), TA(max), and P are known, the value of desired θJA becomes a known entity to the system designer . How to
achieve the desired θJA is left up to the board or system designer, but in general, it can be achieved by adding the effects of θJC (value
provided in Table 17), thermal resistance of the chosen adhesive (θCS), that of the heat sink (θSA), amount of airflow, and properties of the
circuit board (number of layers and size of the boar d). As a general guideline, this device will not need a heat sink if the board has 8 or more
layers AND the board size is larger than 4"x12" AND airflow in excess of 0.5 m/s is available. It is strongly recommended th at users perfor m
their own thermal analysis for their own board and system design scenarios.
Symbol Parameter Value Units Conditions
TJ(max) Junction Temperature 125 oC Maximum
TA(max) Ambient Temperature 70 oC Maximum
θJA(effective) Effective Thermal Resistance, Junction-to-Ambient
16.8 oC/W Zero air flow
10.1 oC/W 1 m/ S air flow
9.2 oC/W 2 m/ S air flow
θJB Thermal Resistance, Junction-to-Board 4.1 oC/W
θJC Thermal Resistance, Jun ction- to-Cas e 0.3 oC/W
P Power Dissipation of the Device 4.31 Watts Maximum
Table 17 Thermal Specifications for PES24T3G2, 19x19 mm FCBGA324 Package
Symbol Parameter Value Units Conditions
TJ(max) Junction Temperature 125 oC Maximum
TA(max) Ambient Temperature 70 oC Maximum
θJA(effective) Effective Thermal Resistance, Junction-to-Ambient
14.6 oC/W Zero air flow
8.2 oC/W 1 m/ S air flow
7.2 oC/W 2 m/ S air flow
θJB Thermal Resistance, Junction-to-Board 3.1 oC/W
θJC Thermal Resistance, Jun ction- to-Cas e 0.3 oC/W
P Power Dissipation of the Device 4.31 Watts Maximum
Table 18 Thermal Specifications for PES24T3G2, 27x27 mm FCBGA676 Package
17 of 51 June 1, 2012
IDT 89HPES24T3G2 Data Sheet
DC Electrical Characteristics
Values based on systems running at recommended supply voltages, as shown in Table 13.
Note: See Table 8, Pin Characteristics, for a complete I/O listing.
I/O Type Parameter Description Gen1 Gen2 Unit Condi-
tions
Min1Typ1Max1Min1Typ1Max1
Serial Link PCIe Transmit
VTX-DIFFp-p Differential peak-to-peak output
voltage 800 1200 800 1200 mV
VTX-DIFFp-p-LOW Low-Drive Differential Peak to
Peak Output Voltage 400 1200 400 1200 mV
VTX-DE-RATIO-
3.5dB De-emphasized differential output
voltage -3 -4 -3.0 -3.5 -4.0 dB
VTX-DE-RATIO-
6.0dB De-emphasized differential output
voltage NA -5.5 -6.0 -6.5 dB
VTX-DC-CM DC Common mode voltage 0 3.6 0 3.6 V
VTX-CM-ACP RMS AC peak common mode
output voltage 20 mV
VTX-CM-DC-active-
idle-delta Abs delta of DC common mode
voltage between L0 and idle 100 100 mV
VTX-CM-DC-line-
delta Abs delta of DC common mode
voltage between D+ and D- 25 25 mV
VTX-Idle-DiffP Electrical idle diff peak output 20 20 mV
RLTX-DIFF Transmitter Differential Return
loss 10 10 dB 0.05 - 1.25GHz
8 dB 1.25 - 2.5GHz
RLTX-CM Transmitter Common Mode
Return loss 66dB
ZTX-DIFF-DC DC Differential TX impedance 80 100 120 120 Ω
VTX-CM-ACpp Peak-Peak AC Common NA 100 mV
VTX-DC-CM Transmit Driver DC Common
Mode Voltage 0 3.6 0 3.6 V
VTX-RCV-DETECT The amount of voltage change
allowed during Receiver Detec-
tion
600 600 mV
ITX-SHORT Transmitter Short Circuit Current
Limit 090 90mA
Table 19 DC Electrical Characteristics (Part 1 of 2)
18 of 51 June 1, 2012
IDT 89HPES24T3G2 Data Sheet
Serial Link
(cont.) PCIe Receive
VRX-DIFFp-p Differential input voltage (peak-to-
peak) 175 1200 120 1200 mV
RLRX-DIFF Receiver Differential Return Loss 10 10 dB 0.05 - 1.25GHz
8 1.25 - 2.5GHz
RLRX-CM Receiver Common Mode Return
Loss 66dB
ZRX-DIFF-DC Differential input impedance (DC) 80 100 120 Refer to return loss spec Ω
ZRX--DC DC common mode impedance 40 50 60 40 60 Ω
ZRX-COMM-DC Powered down input common
mode impedance (DC) 200k 350k 50k Ω
ZRX-HIGH-IMP-DC-
POS DC input CM input impedance for
V>0 during reset or power down 50k 50k Ω
ZRX-HIGH-IMP-DC-
NEG DC input CM input impedance for
V<0 during reset or power down 1.0k 1.0k Ω
VRX-IDLE-DET-
DIFFp-p Electrical idle detect threshold 65 175 65 175 mV
VRX-CM-ACp Receiver AC common-mode peak
voltage 150 150 mV VRX-CM-ACp
PCIe REFCLK
CIN Input Capacitance 1.5 — 1.5 — pF
Other I/Os
LOW Drive
Output IOL —2.5——2.5—mAV
OL = 0.4v
IOH —-5.5— —-5.5— mAV
OH = 1.5V
High Drive
Output IOL — 12.0 — — 12.0 — mA VOL = 0.4v
IOH — -20.0 — — -20.0 — mA VOH = 1.5V
Schmitt Trig-
ger Input
(STI)
VIL -0.3 — 0.8 -0.3 — 0.8 V —
VIH 2.0 — VDDI/O +
0.5 2.0 — VDDI/O +
0.5 V—
Input VIL -0.3 — 0.8 -0.3 — 0.8 V —
VIH 2.0 — VDDI/O +
0.5 2.0 — VDDI/O +
0.5 V—
Capacitance CIN — — 8.5 — — 8.5 pF —
Leakage Inputs — — + 10 — — + 10 μAV
DDI/O (max)
I/OLEAK W/O
Pull-ups/downs ——+
10 — — + 10 μAV
DDI/O (max)
I/OLEAK WITH
Pull-ups/downs ——+
80 — — + 80 μAV
DDI/O (max)
1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 2.0.
I/O Type Parameter Description Gen1 Gen2 Unit Condi-
tions
Min1Typ1Max1Min1Typ1Max1
Table 19 DC Electrical Characteristics (Part 2 of 2)
19 of 51 June 1, 2012
IDT 89HPES24T3G2 Data Sheet
Option A Pack age Pinout, 19x19mm 324-BGA Signal Pinout
The following table lists the pin numbers and signal names for the PES24T3G2 device.
Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt
A1 VSS B17 PE4TN00 D15 VDDCORE F13 VSS
A2 VDDI/O B18 PE4TP00 D16 VSS F14 PE4RN03
A3 VSS C1 PE2TP06 D17 VSS F15 PE4RP03
A4 VSS C2 PE2TN06 D18 VSS F16 VSS
A5 VSS C3 VSS E1 PE2TP05 F17 PE4TN03
A6 VDDI/O C4 PE2RP06 E2 PE2TN05 F18 PE4TP03
A7 VSS C5 PE2RN06 E3 VSS G1 VSS
A8 JTAG_TDI C6 VSS E4 PE2RP05 G2 VSS
A9 MSMBDAT C7 JTAG_TCK E5 PE2RN05 G3 VSS
A10 VDDI/O C8 JTAG_TRST_N E6 VDDCORE G4 VDDCORE
A11 VSS C9 SSMBDAT E7 VDDCORE G5 VDDCORE
A12 GPIO_00 1 C10 CCLKDS E8 VDDCORE G6 VDDPEA
A13 VDDI/O C11 SWMODE_2 E9 VSS G7 VDDPEA
A14 VDDI/O C12 GPIO_02 E10 VDDCORE G8 VDDCORE
A15 VSS C13 GPIO_09 E11 VDDCORE G9 VDDCORE
A16 VSS C14 PE4RN01 E12 VDDCORE G10 VDDCORE
A17 VDDI/O C15 PE4RP01 E13 VDDCORE G11 VSS
A18 VDDI/O C16 VSS E14 PE4RN02 G12 VDDPEA
B1 PE2TP07 C17 PE4TN01 E15 PE4RP02 G13 VDDPEA
B2 PE2TN07 C18 PE4TP01 E16 VSS G14 VDDCORE
B3 VSS D1 VSS E17 PE4TN02 G15 VDDCORE
B4 PE2RP07 D2 VSS E18 PE4TP02 G16 VSS
B5 PE2RN07 D3 VSS F1 PE2TP04 G17 VSS
B6 VDDI/O D4 VDDCORE F2 PE2TN04 G18 VSS
B7 VSS D5 VDDCORE F3 VSS H1 PE2TP03
B8 JTAG_TMS D6 VDDI/O F4 PE2RP04 H2 PE2TN03
B9 SSMBCLK D7 JTAG_TDO F5 PE2RN04 H3 VSS
B10 VDDI/O D8 MSMBCLK F6 VSS H4 PE2RP03
B11 SWMODE_1 D9 CCLKUS F7 VSS H5 PE2RN03
B12 GPIO_01 1 D10 SWMODE_0 F8 VDDCORE H6 VDDPEA
B13 GPIO_10 D11 PERSTN F9 VSS H7 VDDPEA
B14 PE4RN00 D12 GPIO_07 1 F10 VDDCORE H8 VDDCORE
B15 PE4RP00 D13 GPIO_08 F11 VSS H9 VDDCORE
B16 VSS D14 VDDCORE F12 VSS H10 VDDCORE
Table 20 PES24T3G2 (19x19mm 324-pin) Signal Pin-Out (Part 1 of 3)
20 of 51 June 1, 2012
IDT 89HPES24T3G2 Data Sheet
H11 VSS K13 VDDPETA M15 PE4RP07 P17 VDDCORE
H12 VDDPEA K14 VDDCORE M16 VSS P18 VSS
H13 VDDPEA K15 NC M17 PE4TN07 R1 VSS
H14 PE4RN04 K16 VSS M18 PE4TP07 R2 VDDCORE
H15 PE4RP04 K17 REFRES5 N1 VSS R3 VDDCORE
H16 VSS K18 REFRES4 N2 VSS R4 PE0RP07
H17 PE4TN04 L1 PE2TP01 N3 VSS R5 PE0RP06
H18 PE4TP04 L2 PE2TN01 N4 VDDCORE R6 NC
J1 PE2TP02 L3 VSS N5 VDDCORE R7 PE0RP05
J2 PE2TN02 L4 PE2RP01 N6 VSS R8 PE0RP04
J3 VSS L5 PE2RN01 N7 VSS R9 VDDCORE
J4 PE2RP02 L6 VDDPETA N8 VDDPEA R10 PE0RP03
J5 PE2RN02 L7 VDDPETA N9 VDDPEHA R11 PE0RP02
J6 VDDPEHA L8 VDDPEA N10 VDDPETA R12 VDDCORE
J7 VDDPEHA L9 VDDPEHA N11 VDDPEA R13 PE0RP01
J8 VDDCORE L10 VDDPETA N12 VDDPEHA R14 PE0RP00
J9 VSS L11 VDDPEA N13 VSS R15 VDDCORE
J10 VDDCORE L12 VDDPEHA N14 VSS R16 VDDCORE
J11 VSS L13 VDDPETA N15 VDDCORE R17 VDDCORE
J12 VDDPEHA L14 PE4RN06 N16 VSS R18 VSS
J13 VDDPEHA L15 PE4RP06 N17 VSS T1 VSS
J14 PE4RN05 L16 VSS N18 VSS T2 VSS
J15 PE4RP05 L17 PE4TN06 P1 VSS T3 VSS
J16 VSS L18 PE4TP06 P2 VDDCORE T4 VSS
J17 PE4TN05 M1 PE2TP00 P3 VDDCORE T5 VSS
J18 PE4TP05 M2 PE2TN00 P4 PE0RN07 T6 VSS
K1 REFRES2 M3 VSS P5 PE0RN06 T7 VSS
K2 REFRES3 M4 PE2RP00 P6 VDDCORE T8 VSS
K3 VSS M5 PE2RN00 P7 PE0RN05 T9 VSS
K4 VDDCORE M6 VDDPETA P8 PE0RN04 T10 VSS
K5 VDDCORE M7 VDDPETA P9 VDDCORE T11 VSS
K6 VDDPETA M8 VDDPEA P10 PE0RN03 T12 VSS
K7 VDDPETA M9 VDDPEHA P11 PE0RN02 T13 VSS
K8 VDDCORE M10 VDDPETA P12 VDDCORE T14 VSS
K9 VSS M11 VDDPEA P13 PE0RN01 T15 VSS
K10 VDDCORE M12 VDDPEHA P14 PE0RN00 T16 VSS
K11 VSS M13 VSS P15 VDDCORE T17 VSS
K12 VDDPETA M14 PE4RN07 P16 VDDCORE T18 VSS
Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt
Table 20 PES24T3G2 (19x19mm 324-pin) Signal Pin-Out (Part 2 of 3)
21 of 51 June 1, 2012
IDT 89HPES24T3G2 Data Sheet
Option A Package Power Pins (19x19mm 324-Pin)
U1 VSS U10 PE0TN03 V1 VSS V10 PE0TP03
U2 PEREFCLKN U11 PE0TN02 V2 PEREFCLKP V11 PE0TP02
U3 VSS U12 VSS V3 VSS V12 VSS
U4 PE0TN07 U13 PE0TN01 V4 PE0TP07 V13 PE0TP01
U5 PE0TN06 U14 PE0TN00 V5 PE0TP06 V14 PE0TP00
U6 REFRES1 U15 VSS V6 REFRES0 V15 VSS
U7 PE0TN05 U16 VSS V7 PE0TP05 V16 VSS
U8 PE0TN04 U17 VSS V8 PE0TP04 V17 VSS
U9 VSS U18 VSS V9 VSS V18 VSS
VDDCore VDDCore VDDCore VDDI/O VDDPEA VDDPEHA VDDPETA
D4 G9 N15 A2 G6 J6 K6
D5 G10 P2 A6 G7 J7 K7
D14 G14 P3 A10 G12 J12 K12
D15 G15 P6 A13 G13 J13 K13
E6 H8 P9 A14 H6 L9 L6
E7 H9 P12 A17 H7 L12 L7
E8 H10 P15 A18 H12 M9 L10
E10 J8 P16 B6 H13 M12 L13
E11 J10 P17 B10 L8 N9 M6
E12 K4 R2 D6 L11 N12 M7
E13 K5 R3 M8 M10
F8 K8 R9 M11 N10
F10 K10 R12 N8
G4 K14 R15 N11
G5 N4 R16
G8 N5 R17
Table 21 PES24T3G2 (19x19mm 324-Pin) Power Pins
Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt
Table 20 PES24T3G2 (19x19mm 324-pin) Signal Pin-Out (Part 3 of 3)
22 of 51 June 1, 2012
IDT 89HPES24T3G2 Data Sheet
Option A Package Ground Pins (19x19mm 324-Pin)
Option A Package Alternate Signal Functions (19x19mm 324-Pin)
VSS VSS VSS VSS VSS VSS
A1 D16 G11 M3 T1 T18
A3 D17 G16 M13 T2 U1
A4 D18 G17 M16 T3 U3
A5 E3 G18 N1 T4 U9
A7 E9 H3 N2 T5 U12
A11 E16 H11 N3 T6 U15
A15 F3 H16 N6 T7 U16
A16 F6 J3 N7 T8 U17
B3 F7 J9N13T9U18
B7 F9 J11 N14 T10 V1
B16 F11 J16 N16 T11 V3
C3 F12 K3 N17 T12 V9
C6 F13 K9 N18 T13 V12
C16 F16 K11 P1 T14 V15
D1 G1 K16 P18 T15 V16
D2 G2 L3 R1 T16 V17
D3 G3 L16 R18 T17 V18
Table 22 PES24T3G2 (19x19mm 324-Pin) Ground Pins
Pin GPIO Alternate
A12 GPIO_00 P2RSTN
B12 GPIO_01 P4RSTN
C12 GPIO_02 IOEXPINTN0
D12 GPIO_07 GPEN
Table 23 PES24T3G2 (19x19mm 324-Pin) Alternate Signal Functions
23 of 51 June 1, 2012
IDT 89HPES24T3G2 Data Sheet
Opti on A Package Si gn als List e d Alph abet i ca l ly (19x19 m m 32 4-Pi n )
Signal Name I/O Type Location Signal Category
CCLKDS I C10 System
CCLKUS I D9
GPIO_00 I/O A12 General Purpose Input/Output
GPIO_01 I/O B12
GPIO_02 I/O C12
GPIO_07 I/O D12
GPIO_08 I/O D13
GPIO_09 I/O C13
GPIO_10 I/O B13
JTAG_TCK I C7 JTAG
JTAG_TDI I A8
JTAG_TDO O D7
JTAG_TMS I B8
JTAG_TRST_N I C8
MSMBCLK I/O D8 SMBus
MSMBDAT I/O A9
NO CONNECT K15, R6
PE0RN00 I P14 PCI Express
PE0RN01 I P13
PE0RN02 I P11
PE0RN03 I P10
PE0RN04 I P8
PE0RN05 I P7
PE0RN06 I P5
PE0RN07 I P4
PE0RP00 I R14
PE0RP01 I R13
PE0RP02 I R11
PE0RP03 I R10
PE0RP04 I R8
PE0RP05 I R7
PE0RP06 I R5
PE0RP07 I R4
PE0TN00 O U14
Table 24 PES24T3G2 (19x19mm 324-Pin) Alphabetical Signal List (Part 1 of 4)
24 of 51 June 1, 2012
IDT 89HPES24T3G2 Data Sheet
PE0TN01 O U13 PCI Express (cont.)
PE0TN02 O U11
PE0TN03 O U10
PE0TN04 O U8
PE0TN05 O U7
PE0TN06 O U5
PE0TN07 O U4
PE0TP00 O V14
PE0TP01 O V13
PE0TP02 O V11
PE0TP03 O V10
PE0TP04 O V8
PE0TP05 O V7
PE0TP06 O V5
PE0TP07 O V4
PE2RN00 I M5
PE2RN01 I L5
PE2RN02 I J5
PE2RN03 I H5
PE2RN04 I F5
PE2RN05 I E5
PE2RN06 I C5
PE2RN07 I B5
PE2RP00 I M4
PE2RP01 I L4
PE2RP02 I J4
PE2RP03 I H4
PE2RP04 I F4
PE2RP05 I E4
PE2RP06 I C4
PE2RP07 I B4
PE2TN00 O M2
PE2TN01 O L2
PE2TN02 O J2
PE2TN03 O H2
PE2TN04 O F2
Signal Name I/O Type Location Signal Category
Table 24 PES24T3G2 (19x19mm 324-Pin) Alphabetical Signal List (Part 2 of 4)
25 of 51 June 1, 2012
IDT 89HPES24T3G2 Data Sheet
PE2TN05 O E2 PCI Express (cont.)
PE2TN06 O C2
PE2TN07 O B2
PE2TP00 O M1
PE2TP01 O L1
PE2TP02 O J1
PE2TP03 O H1
PE2TP04 O F1
PE2TP05 O E1
PE2TP06 O C1
PE2TP07 O B1
PE4RN00 I B14
PE4RN01 I C14
PE4RN02 I E14
PE4RN03 I F14
PE4RN04 I H14
PE4RN05 I J14
PE4RN06 I L14
PE4RN07 I M14
PE4RP00 I B15
PE4RP01 I C15
PE4RP02 I E15
PE4RP03 I F15
PE4RP04 I H15
PE4RP05 I J15
PE4RP06 I L15
PE4RP07 I M15
PE4TN00 O B17
PE4TN01 O C17
PE4TN02 O E17
PE4TN03 O F17
PE4TN04 O H17
PE4TN05 O J17
PE4TN06 O L17
PE4TN07 O M17
PE4TP00 O B18
Signal Name I/O Type Location Signal Category
Table 24 PES24T3G2 (19x19mm 324-Pin) Alphabetical Signal List (Part 3 of 4)
26 of 51 June 1, 2012
IDT 89HPES24T3G2 Data Sheet
PE4TP01 O C18 PCI Express (cont.)
PE4TP02 O E18
PE4TP03 O F18
PE4TP04 O H18
PE4TP05 O J18
PE4TP06 O L18
PE4TP07 O M18
PEREFCLKN I U2
PEREFCLKP I V2
PERSTN I D11 System
REFRES0 I/O V6 SerDes Reference Resistors
REFRES1 I/O U6
REFRES2 I/O K1
REFRES3 I/O K2
REFRES4 I/O K18
REFRES5 I/O K17
SSMBCLK I/O B9 SMBus
SSMBDAT I/O C9
SWMODE_0 I D10 System
SWMODE_1 I B11
SWMODE_2 I C11
VDDCORE, VDDI/O,
VDDPEA, VDDPEHA,
VDDPETA
See Table 21 for a listing of power pins.
VSS See Table 22 for a listing of ground pins.
Signal Name I/O Type Location Signal Category
Table 24 PES24T3G2 (19x19mm 324-Pin) Alphabetical Signal List (Part 4 of 4)
27 of 51 June 1, 2012
IDT 89HPES24T3G2 Data Sheet
Option A Pack age — Package Trace Length
Signal Name Conductor Length
(microns)
PE0RN00 6476.76
PE0RP00 6852.44
PE0RN01 5193.18
PE0RP01 5556.44
PE0RN02 4122.07
PE0RP02 4488.70
PE0RN03 4026.18
PE0RP03 4426.98
PE0TN00 9779.14
PE0TP00 9830.77
PE0TN01 8725.88
PE0TP01 8836.41
PE0TN02 7608.89
PE0TP02 7657.42
PE0TN03 7295.70
PE0TP03 7361.98
PE1RN00 3844.19
PE1RP00 4219.88
PE1RN01 4261.05
PE1RP01 4636.74
PE1RN02 5263.73
PE1RP02 5639.42
PE1RN03 6331.07
PE1RP03 6726.84
PE1TN00 7518.88
PE1TP00 7605.87
PE1TN01 7393.75
PE1TP01 7528.38
PE1TN02 8469.86
PE1TP02 8583.77
PE1TN03 8516.01
PE1TP03 8650.63
PE2RN00 2227.99
PE2RP00 2600.58
PE2RN01 1881.27
Table 25 Signal Trace Length (Part 1 of 3)
28 of 51 June 1, 2012
IDT 89HPES24T3G2 Data Sheet
PE2RP01 2256.96
PE2RN02 2105.60
PE2RP02 2470.94
PE2RN03 2835.27
PE2RP03 3207.86
PE2TN00 5462.64
PE2TP00 5576.55
PE2TN01 5163.54
PE2TP01 5273.30
PE2TN02 5389.58
PE2TP02 5512.25
PE2TN03 5310.88
PE2TP03 5451.71
PE3RN00 9181.06
PE3RP00 9541.52
PE3RN01 8602.32
PE3RP01 8994.21
PE3RN02 8220.08
PE3RP02 8604.05
PE3RN03 8906.71
PE3RP03 9193.82
PE3TN00 10606.88
PE3TP00 10747.72
PE3TN01 10972.20
PE3TP01 11117.18
PE3TN02 11862.08
PE3TP02 11978.06
PE3TN03 11822.86
PE3TP03 11870.23
PE4RN00 9450.47
PE4RP00 9700.88
PE4RN01 8438.57
PE4RP01 8818.65
PE4RN02 8521.33
PE4RP02 8890.07
PE4RN03 9130.21
PE4RP03 9403.58
Signal Name Conductor Length
(microns)
Table 25 Signal Trace Length (Part 2 of 3)
29 of 51 June 1, 2012
IDT 89HPES24T3G2 Data Sheet
PE4TN00 12116.40
PE4TP00 12168.24
PE4TN01 12011.65
PE4TP01 12035.01
PE4TN02 12731.79
PE4TP02 12864.34
PE4TN03 11571.96
PE4TP03 11712.79
PE5RN00 3155.78
PE5RP00 3508.24
PE5RN01 2200.39
PE5RP01 2545.56
PE5RN02 1838.19
PE5RP02 2171.00
PE5RN03 2126.08
PE5RP03 2467.21
PE5TN00 7480.71
PE5TP00 7630.60
PE5TN01 5329.03
PE5TP01 5422.12
PE5TN02 5244.03
PE5TP02 5302.02
PE5TN03 4991.19
PE5TP03 5127.88
PE0REFCLKN 12558.62
PE0REFCLKP 12641.05
Signal Name Conductor Length
(microns)
Table 25 Signal Trace Length (Part 3 of 3)
30 of 51 June 1, 2012
IDT 89HPES24T3G2 Data Sheet
Option A Pack age Pinout — Top View
1 2 3 4 5 6 7 8 9 101112131415 16
Vss (Ground)
VDDCore (Power)
A
B
VDDI/O (Power)
17 18
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
VDDPETA (Power)
VDDPEA (Power)
VDDPEHA (Power)
Signals
1 2 3 4 5 6 7 8 9 101112131415 1617 18
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
xNo Connect
X
X
XX XX
X
XX
X
X
X
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IDT 89HPES24T3G2 Data Sheet
19x19mm Package Drawing — 324-Pin AL324/AR324
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IDT 89HPES24T3G2 Data Sheet
19x19mm Package Dr awing — Page Two
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IDT 89HPES24T3G2 Data Sheet
Option B Pack age Pinout, 27x27mm 676-BGA Signal Pinout
The following table lists the pin numbers and signal names for the PES24T3G2 device.
Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt
A1 VSS B9 MSMBDAT C17 VDDI/O D25 VSS
A2 VSS B10 SSMBADDR_2 C18 VSS D26 NC
A3 VSS B11 SSMBADDR_5 C19 VDDI/O E1 VSS
A4 JTAG_TDI B12 SSMBDAT C20 VSS E2 VSS
A5 JTAG_TMS B13 VSS C21 VDDI/O E3 VSS
A6 MSMBADDR_1 B14 SWMODE_0 C22 GPIO_10 E4 VSS
A7 MSMBADDR_3 B15 SWMODE_2 C23 VDDI/O E5 VSS
A8 MSMBCLK B16 VSS C24 VSS E6 VDDCORE
A9 SSMBADDR_1 B17 VDDI/O C25 VSS E7 VDDCORE
A10 SSMBADDR_3 B18 GPIO_00 1 C26 NC E8 VSS
A11 SSMBCLK B19 GPIO_02 1 D1 PEREFCLKP E9 VDDCORE
A12 CCLKUS B20 GPIO_04 1 D2 VSS E10 VSS
A13 CCLKDS B21 GPIO_06 D3 VSS E11 VDDCORE
A14 VSS B22 MSMBSMODE D4 VSS E12 VSS
A15 SWMODE_1 B23 REFCLKM D5 VDDCORE E13 VDDCORE
A16 NC B24 VDDI/O D6 VDDCORE E14 VSS
A17 PERSTN B25 VSS D7 VSS E15 VDDCORE
A18 RSTHALT B26 VSS D8 VDDCORE E16 VSS
A19 GPIO_01 1 C1 PEREFCLKN D9 VSS E17 VDDCORE
A20 GPIO_03 1 C2 VSS D10 VDDCORE E18 VSS
A21 GPIO_05 C3 VSS D11 VSS E19 VDDCORE
A22 GPIO_07 1 C4 VDDCORE D12 VDDCORE E20 VDDCORE
A23 VSS C5 VDDI/O D13 VDDCORE E21 VDDCORE
A24 GPIO_09 C6 VSS D14 VSS E22 VSS
A25 VSS C7 VDDI/O D15 VDDCORE E23 VSS
A26 VSS C8 VSS D16 VSS E24 VSS
B1 VSS C9 VDDI/O D17 VDDCORE E25 VSS
B2 VSS C10 VSS D18 VDDCORE E26 VSS
B3 VDDI/O C11 VDDI/O D19 VDDCORE F1 VDDCORE
B4 JTAG_TCK C12 VSS D20 VSS F2 VDDCORE
B5 JTAG-TDO C13 VDDI/O D21 VDDCORE F3 VDDPEA
B6 JTAG-TRST_N C14 VDDCORE D22 VDDCORE F4 VSS
B7 MSMBADDR_2 C15 VDDI/O D23 GPIO_08 F5 VSS
B8 MSMBADDR_4 C16 VDDCORE D24 VSS F6 VDDI/O
Table 26 PES24T3G2 (27x27mm 676-Pin) Signal Pin-Out (Part 1 of 5)
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IDT 89HPES24T3G2 Data Sheet
F7 VSS G18 VSS J3 VDDPETA K14 VSS
F8 VSS G19 VSS J4 PE2RN06 K15 VDDCORE
F9 VSS G20 VSS J5 PE2RP06 K16 VDDCORE
F10 VSS G21 VSS J6 VSS K17 VSS
F11 VSS G22 PE4RP00 J7 VDDCORE K18 VSS
F12 NC G23 PE4RN00 J8 VDDCORE K19 VDDCORE
F13 VSS G24 VDDPETA J9 VSS K20 VDDCORE
F14 VSS G25 PE4TP00 J10 VSS K21 VSS
F15 VSS G26 PE4TN00 J11 VDDCORE K22 VDDPEA
F16 NC H1 VSS J12 VDDCORE K23 VDDPEA
F17 VSS H2 VSS J13 VSS K24 VDDPEA
F18 VSS H3 VDDPEHA J14 VSS K25 VSS
F19 VSS H4 VDDPEHA J15 VDDCORE K26 REFRES4
F20 VSS H5 VSS J16 VDDCORE L1 PE2TN05
F21 VSS H6 VSS J17 VSS L2 PE2TP05
F22 VSS H7 VDDCORE J18 VSS L3 VDDPETA
F23 VSS H8 VDDCORE J19 VDDCORE L4 PE2RN05
F24 VDDPEA H9 VSS J20 VDDCORE L5 PE2RP05
F25 VDDCORE H10 VSS J21 VSS L6 VSS
F26 VDDCORE H11 VDDCORE J22 PE4RP01 L7 VDDCORE
G1 PE2TN07 H12 VDDCORE J23 PE4RN01 L8 VDDCORE
G2 PE2TP07 H13 VSS J24 VDDPETA L9 VSS
G3 VDDPETA H14 VSS J25 PE4TP01 L10 VSS
G4 PE2RN07 H15 VDDCORE J26 PE4TN01 L11 VDDCORE
G5 PE2RP07 H16 VDDCORE K1 REFRES3 L12 VDDCORE
G6 VSS H17 VSS K2 VSS L13 VSS
G7 VSS H18 VSS K3 VDDPEA L14 VSS
G8 VSS H19 VDDCORE K4 VDDPEA L15 VDDCORE
G9 VSS H20 VDDCORE K5 VDDPEA L16 VDDCORE
G10 VSS H21 VSS K6 VSS L17 VSS
G11 VSS H22 VSS K7 VDDCORE L18 VSS
G12 VSS H23 VDDPEHA K8 VDDCORE L19 VDDCORE
G13 VSS H24 VDDPEHA K9 VSS L20 VDDCORE
G14 VSS H25 VSS K10 VSS L21 VSS
G15 VSS H26 VSS K11 VDDCORE L22 PE4RP02
G16 VSS J1 PE2TN06 K12 VDDCORE L23 PE4RN02
G17 VSS J2 PE2TP06 K13 VSS L24 VDDPETA
Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt
Table 26 PES24T3G2 (27x27mm 676-Pin) Signal Pin-Out (Part 2 of 5)
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IDT 89HPES24T3G2 Data Sheet
L25 PE4TP02 N10 VSS P21 VSS T6 NC
L26 PE4TN02 N11 VDDCORE P22 VSS T7 VDDCORE
M1 VDDCORE N12 VDDCORE P23 VDDPEHA T8 VDDCORE
M2 VSS N13 VSS P24 VDDPEHA T9 VSS
M3 VDDPEHA N14 VSS P25 VSS T10 VSS
M4 VDDPEHA N15 VDDCORE P26 VDDCORE T11 VDDCORE
M5 VSS N16 VDDCORE R1 PE2TN03 T12 VDDCORE
M6 NC N17 VSS R2 PE2TP03 T13 VSS
M7 VDDCORE N18 VSS R3 VDDPETA T14 VSS
M8 VDDCORE N19 VDDCORE R4 PE2RN03 T15 VDDCORE
M9 VSS N20 VDDCORE R5 PE2RP03 T16 VDDCORE
M10 VSS N21 VSS R6 VSS T17 VSS
M11 VDDCORE N22 PE4RP03 R7 VDDCORE T18 VSS
M12 VDDCORE N23 PE4RN03 R8 VDDCORE T19 VDDCORE
M13 VSS N24 VDDPETA R9 VSS T20 VDDCORE
M14 VSS N25 PE4TP03 R10 VSS T21 NC
M15 VDDCORE N26 PE4TN03 R11 VDDCORE T22 VSS
M16 VDDCORE P1 VDDCORE R12 VDDCORE T23 VDDPEA
M17 VSS P2 VSS R13 VSS T24 VDDPEA
M18 VSS P3 VDDPEHA R14 VSS T25 VSS
M19 VDDCORE P4 VDDPEHA R15 VDDCORE T26 VDDCORE
M20 VDDCORE P5 VSS R16 VDDCORE U1 PE2TN02
M21 NC P6 VSS R17 VSS U2 PE2TP02
M22 VSS P7 VDDCORE R18 VSS U3 VDDPETA
M23 VDDPEHA P8 VDDCORE R19 VDDCORE U4 PE2RN02
M24 VDDPEHA P9 VSS R20 VDDCORE U5 PE2RP02
M25 VSS P10 VSS R21 VSS U6 VSS
M26 VDDCORE P11 VDDCORE R22 PE4RP04 U7 VDDCORE
N1 PE2TN04 P12 VDDCORE R23 PE4RN04 U8 VDDCORE
N2 PE2TP04 P13 VSS R24 VDDPETA U9 VSS
N3 VDDPETA P14 VSS R25 PE4TP04 U10 VSS
N4 PE2RN04 P15 VDDCORE R26 PE4TN04 U11 VDDCORE
N5 PE2RP04 P16 VDDCORE T1 VDDCORE U12 VDDCORE
N6 VSS P17 VSS T2 VSS U13 VSS
N7 VDDCORE P18 VSS T3 VDDPEA U14 VSS
N8 VDDCORE P19 VDDCORE T4 VDDPEA U15 VDDCORE
N9 VSS P20 VDDCORE T5 VSS U16 VDDCORE
Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt
Table 26 PES24T3G2 (27x27mm 676-Pin) Signal Pin-Out (Part 3 of 5)
36 of 51 June 1, 2012
IDT 89HPES24T3G2 Data Sheet
U17 VSS W2 PE2TP01 Y13 VSS AA24 VDDPETA
U18 VSS W3 VDDPETA Y14 VSS AA25 PE4TP07
U19 VDDCORE W4 PE2RN01 Y15 VDDCORE AA26 PE4TN07
U20 VDDCORE W5 PE2RP01 Y16 VDDCORE AB1 VSS
U21 VSS W6 VSS Y17 VSS AB2 VSS
U22 PE4RP05 W7 VDDCORE Y18 VSS AB3 VDDCORE
U23 PE4RN05 W8 VDDCORE Y19 VDDCORE AB4 VDDCORE
U24 VDDPETA W9 VSS Y20 VDDCORE AB5 VDDCORE
U25 PE4TP05 W10 VSS Y21 VSS AB6 VSS
U26 PE4TN05 W11 VDDCORE Y22 VSS AB7 PE0RP07
V1 VDDCORE W12 VDDCORE Y23 VDDPEHA AB8 VSS
V2 VSS W13 VSS Y24 VDDPEHA AB9 PE0RP06
V3 VDDPEA W14 VSS Y25 VSS AB10 VDDPEA
V4 VDDPEA W15 VDDCORE Y26 REFRES5 AB11 PE0RP05
V5 VDDPEA W16 VDDCORE AA1 PE2TN00 AB12 VSS
V6 VSS W17 VSS AA2 PE2TP00 AB13 PE0RP04
V7 VDDCORE W18 VSS AA3 VDDPETA AB14 VDDPEA
V8 VDDCORE W19 VDDCORE AA4 PE2RN00 AB15 PE0RP03
V9 VSS W20 VDDCORE AA5 PE2RP00 AB16 VSS
V10 VSS W21 VSS AA6 VSS AB17 PE0RP02
V11 VDDCORE W22 PE4RP06 AA7 VSS AB18 VDDPEA
V12 VDDCORE W23 PE4RN06 AA8 VSS AB19 PE0RP01
V13 VSS W24 VDDPETA AA9 VSS AB20 VSS
V14 VSS W25 PE4TP06 AA10 VSS AB21 PE0RP00
V15 VDDCORE W26 PE4TN06 AA11 VSS AB22 VSS
V16 VDDCORE Y1 REFRES2 AA12 NC AB23 VDDCORE
V17 VSS Y2 VSS AA13 VSS AB24 VDDCORE
V18 VSS Y3 VDDPEHA AA14 VSS AB25 VSS
V19 VDDCORE Y4 VDDPEHA AA15 VSS AB26 VSS
V20 VDDCORE Y5 VSS AA16 NC AC1 VSS
V21 VSS Y6 VSS AA17 VSS AC2 VSS
V22 VDDPEA Y7 VDDCORE AA18 VSS AC3 VDDCORE
V23 VDDPEA Y8 VDDCORE AA19 VSS AC4 VDDCORE
V24 VDDPEA Y9 VSS AA20 VSS AC5 VDDCORE
V25 VSS Y10 VSS AA21 VSS AC6 VDDPEHA
V26 VDDCORE Y11 VDDCORE AA22 PE4RP07 AC7 PE0RN07
W1 PE2TN01 Y12 VDDCORE AA23 PE4RN07 AC8 VDDPEA
Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt
Table 26 PES24T3G2 (27x27mm 676-Pin) Signal Pin-Out (Part 4 of 5)
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IDT 89HPES24T3G2 Data Sheet
AC9 PE0RN06 AD7 VSS AE5 VSS AF3 VDDCORE
AC10 VDDPEA AD8 VDDPETA AE6 VSS AF4 VDDCORE
AC11 PE0RN05 AD9 VSS AE7 PE0TP07 AF5 VDDCORE
AC12 VDDPEHA AD10 VDDPETA AE8 VSS AF6 VSS
AC13 PE0RN04 AD11 VDDPETA AE9 PE0TP06 AF7 PE0TN07
AC14 VDDPEHA AD12 VDDPEHA AE10 VSS AF8 REFRES1
AC15 PE0RN03 AD13 VDDPETA AE11 PE0TP05 AF9 PE0TN06
AC16 VDDPEA AD14 VDDPEHA AE12 VSS AF10 VDDCORE
AC17 PE0RN02 AD15 VDDPETA AE13 PE0TP04 AF11 PE0TN05
AC18 VDDPEA AD16 VDDPEA AE14 VSS AF12 VDDCORE
AC19 PE0RN01 AD17 VSS AE15 PE0TP03 AF13 PE0TN04
AC20 VDDPEHA AD18 VDDPETA AE16 VSS AF14 VDDCORE
AC21 PE0RN00 AD19 VDDPETA AE17 PE0TP02 AF15 PE0TN03
AC22 VSS AD20 VDDPEHA AE18 VSS AF16 VDDCORE
AC23 VDDCORE AD21 VDDPETA AE19 PE0TP01 AF17 PE0TN02
AC24 VDDCORE AD22 VSS AE20 VSS AF18 REFRES0
AC25 VSS AD23 VDDCORE AE21 PE0TP00 AF19 PE0TN01
AC26 VSS AD24 VDDCORE AE22 VSS AF20 VSS
AD1 VSS AD25 VSS AE23 VDDCORE AF21 PE0TN00
AD2 VSS AD26 VSS AE24 VDDCORE AF22 VSS
AD3 VDDCORE AE1 VSS AE25 VSS AF23 VDDCORE
AD4 VDDCORE AE2 VSS AE26 VSS AF24 VDDCORE
AD5 VDDCORE AE3 VDDCORE AF1 VSS AF25 VSS
AD6 VDDPEHA AE4 VDDCORE AF2 VSS AF26 VSS
Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt
Table 26 PES24T3G2 (27x27mm 676-Pin) Signal Pin-Out (Part 5 of 5)
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IDT 89HPES24T3G2 Data Sheet
Option B Package Core Power Pins (27x27mm 676-Pin Package)
VDDCore VDDCore VDDCore VDDCore VDDCore VDDCore
C4 H7 L16 P20 V7 AB24
C14 H8 L19 P26 V8 AC3
C16 H11 L20 R7 V11 AC4
D5 H12 M1 R8 V12 AC5
D6 H15 M7 R11 V15 AC23
D8 H16 M8 R12 V16 AC24
D10 H19 M11 R15 V19 AD3
D12 H20 M12 R16 V20 AD4
D13 J7 M15 R19 V26 AD5
D15 J8 M16 R20 W7 AD23
D17 J11 M19 T1 W8 AD24
D18 J12 M20 T7 W11 AE3
D19 J15 M26 T8 W12 AE4
D21 J16 N7 T11 W15 AE23
D22 J19 N8 T12 W16 AE24
E6 J20 N11 T15 W19 AF3
E7 K7 N12 T16 W20 AF4
E9 K8 N15 T19 Y7 AF5
E11 K11 N16 T20 Y8 AF10
E13K12N19T26Y11AF12
E15 K15 N20 U7 Y12 AF14
E17 K16 P1 U8 Y15 AF16
E19 K19 P7 U11 Y16 AF23
E20 K20 P8 U12 Y19 AF24
E21 L7 P11 U15 Y20
F1 L8 P12 U16 AB3
F2 L11 P15 U19 AB4
F25 L12 P16 U20 AB5
F26 L15 P19 V1 AB23
Table 27 PES24T3G2 (27x27mm 676-Pin) Core Power Pins
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IDT 89HPES24T3G2 Data Sheet
Opti on B P a ckage I/O, PCIe, and Transmitter Power Pi ns (2 7x2 7m m 676-Pin)
VDDI/O VDDPEA VDDPEHA VDDPETA
B3 F3 H3 G3
B17 F24 H4 G24
B24 K3 H23 J3
C5 K4 H24 J24
C7 K5 M3 L3
C9 K22 M4 L24
C11 K23 M23 N3
C13 K24 M24 N24
C15 T3 P3 R3
C17 T4 P4 R24
C19 T23 P23 U3
C21 T24 P24 U24
C23 V3 Y3 W3
F6 V4 Y4 W24
V5 Y23 AA3
V22 Y24 AA24
V23 AC6 AD8
V24 AC12 AD10
AB10 AC14 AD11
AB14 AC20 AD13
AB18 AD6 AD15
AC8 AD12 AD18
AC10 AD14 AD19
AC16 AD20 AD21
AC18
AD16
Table 28 PES24T3G2 (27x27mm 676-Pin) I/O, PCIe, Transmitter Power Pins
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IDT 89HPES24T3G2 Data Sheet
Option B Package Ground Pins (27x27mm 676-Pin)
Vss Vss V
ss V
ss V
ss V
ss V
ss V
ss
A1 E1 G7 J17 N13 T25 Y17 AD1
A2 E2 G8 J18 N14 U6 Y18 AD2
A3 E3 G9 J21 N17 U9 Y21 AD7
A14 E4 G10 K2 N18 U10 Y22 AD9
A23 E5 G11 K6 N21 U13 Y25 AD17
A25 E8 G12 K9 P2 U14 AA6 AD22
A26 E10 G13 K10 P5 U17 AA7 AD25
B1 E12 G14 K13 P6 U18 AA8 AD26
B2 E14 G15 K14 P9 U21 AA9 AE1
B13 E16 G16 K17 P10 V2 AA10 AE2
B16 E18 G17 K18 P13 V6 AA11 AE5
B25 E22 G18 K21 P14 V9 AA13 AE6
B26 E23 G19 K25 P17 V10 AA14 AE8
C2 E24 G20 L6 P18 V13 AA15 AE10
C3 E25 G21 L9 P21 V14 AA17 AE12
C6 E26 H1 L10 P22 V17 AA18 AE14
C8 F4 H2 L13 P25 V18 AA19 AE16
C10 F5 H5 L14 R6 V21 AA20 AE18
C12 F7 H6 L17 R9 V25 AA21 AE20
C18 F8 H9 L18 R10 W6 AB1 AE22
C20 F9 H10 L21 R13 W9 AB2 AE25
C24 F10 H13 M2 R14 W10 AB6 AE26
C25 F11 H14 M5 R17 W13 AB8 AF1
D2 F13 H17 M9 R18 W14 AB12 AF2
D3 F14 H18 M10 R21 W17 AB16 AF6
D4 F15 H21 M13 T2 W18 AB20 AF20
D7 F17 H22 M14 T5 W21 AB22 AF22
D9 F18 H25 M17 T9 Y2 AB25 AF25
D11 F19 H26 M18 T10 Y5 AB26 AF26
D14 F20 J6 M22 T13 Y6 AC1
D16 F21 J9 M25 T14 Y9 AC2
D20 F22 J10 N6 T17 Y10 AC22
D24 F23 J13 N9 T18 Y13 AC25
D25 G6 J14 N10 T22 Y14 AC26
Table 29 PES24T3G2 (27x27mm 676-Pin) Ground Pins
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IDT 89HPES24T3G2 Data Sheet
Option B Package Alternate Signal Functions (27x27mm 676-Pin)
Option B Package No Connect Pins (27x27mm 676-Pin)
Pin GPIO Alternate
B18 GPIO[0] P2RSTN
A19 GPIO[1] P4RSTN
B19 GPIO[2] IOEXPINTN0
A20 GPIO[3] IOEXPINTN1
B20 GPIO[4] IOEXPINTN2
A22 GPIO[7] GPEN
Table 30 PES24T3G2 (27x27mm 676-Pin) Alternate Signal Functions
NC Pins
A16
C26
D26
F12
F16
M6
M21
T6
T21
AA12
AA16
Table 31 PES24T3G2 (27x27mm 676-Pin) No Connect Pins
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IDT 89HPES24T3G2 Data Sheet
Opti on B Package Si gn als List e d Alph abet i ca l ly (27x27 m m 67 6-Pi n )
Signal Name I/O Type Location Signal Category
CCLKDS I A13 System
CCLKUS I A12
GPIO_00 I/O B18 General Purpose Input/Output
GPIO_01 I/O A19
GPIO_02 I/O B19
GPIO_03 I/O A20
GPIO_04 I/O B20
GPIO_05 I/O A21
GPIO_06 I/O B21
GPIO_07 I/O A22
GPIO_08 I/O D23
GPIO_09 I/O A24
GPIO_10 I/O C22
JTAG_TCK I B4 JTAG
JTAG_TDI I A4
JTAG_TDO O B5
JTAG_TMS I A5
JTAG_TRST_N I B6
MSMBADDR_1 I A6 SMBus
MSMBADDR_2 I B7
MSMBADDR_3 I A7
MSMBADDR_4 I B8
MSMBCLK I/O A8
MSMBDAT I/O B9
MSMBSMODE I B22 System
NO CONNECT See Table 31 for a list of No Connect pins.
Table 32 PES24T3G2 (27x27mm 676-Pin) Alphabetical Signal List (Part 1 of 5)
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IDT 89HPES24T3G2 Data Sheet
PE0RN00 I AC21 PCI Express
PE0RN01 I AC19
PE0RN02 I AC17
PE0RN03 I AC15
PE0RN04 I AC13
PE0RN05 I AC11
PE0RN06 I AC9
PE0RN07 I AC7
PE0RP00 I AB21
PE0RP01 I AB19
PE0RP02 I AB17
PE0RP03 I AB15
PE0RP04 I AB13
PE0RP05 I AB11
PE0RP06 I AB9
PE0RP07 I AB7
PE0TN00 O AF21
PE0TN01 O AF19
PE0TN02 O AF17
PE0TN03 O AF15
PE0TN04 O AF13
PE0TN05 O AF11
PE0TN06 O AF9
PE0TN07 O AF7
PE0TP00 O AE21
PE0TP01 O AE19
PE0TP02 O AE17
PE0TP03 O AE15
PE0TP04 O AE13
PE0TP05 O AE11
PE0TP06 O AE9
PE0TP07 O AE7
PE2RN00 I AA4
PE2RN01 I W4
PE2RN02 I U4
PE2RN03 I R4
Signal Name I/O Type Location Signal Category
Table 32 PES24T3G2 (27x27mm 676-Pin) Alphabetical Signal List (Part 2 of 5)
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IDT 89HPES24T3G2 Data Sheet
PE2RN04 I N4 PCI Express (cont.)
PE2RN05 I L4
PE2RN06 I J4
PE2RN07 I G4
PE2RP00 I AA5
PE2RP01 I W5
PE2RP02 I U5
PE2RP03 I R5
PE2RP04 I N5
PE2RP05 I L5
PE2RP06 I J5
PE2RP07 I G5
PE2TN00 O AA1
PE2TN01 O W1
PE2TN02 O U1
PE2TN03 O R1
PE2TN04 O N1
PE2TN05 O L1
PE2TN06 O J1
PE2TN07 O G1
PE2TP00 O AA2
PE2TP01 O W2
PE2TP02 O U2
PE2TP03 O R2
PE2TP04 O N2
PE2TP05 O L2
PE2TP06 O J2
PE2TP07 O G2
PE4RN00 I G23
PE4RN01 I J23
PE4RN02 I L23
PE4RN03 I N23
PE4RN04 I R23
PE4RN05 I U23
PE4RN06 I W23
PE4RN07 I AA23
Signal Name I/O Type Location Signal Category
Table 32 PES24T3G2 (27x27mm 676-Pin) Alphabetical Signal List (Part 3 of 5)
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IDT 89HPES24T3G2 Data Sheet
PE4RP00 I G22 PCI Express (cont.)
PE4RP01 I J22
PE4RP02 I L22
PE4RP03 I N22
PE4RP04 I R22
PE4RP05 I U22
PE4RP06 I W22
PE4RP07 I AA22
PE4TN00 O G26
PE4TN01 O J26
PE4TN02 O L26
PE4TN03 O N26
PE4TN04 O R26
PE4TN05 O U26
PE4TN06 O W26
PE4TN07 O AA26
PE4TP00 O G25
PE4TP01 O J25
PE4TP02 O L25
PE4TP03 O N25
PE4TP04 O R25
PE4TP05 O U25
PE4TP06 O W25
PE4TP07 O AA25
PEREFCLKN I C1
PEREFCLKP I D1
PERSTN I A17 System
REFCLKM I B23 PCI Express
REFRES0 I/O AF18 SerDes Reference Resistors
REFRES1 I/O AF8
REFRES2 I/O Y1
REFRES3 I/O K1
REFRES4 I/O K26
REFRES5 I/O Y26
RSTHALT I A18 System
Signal Name I/O Type Location Signal Category
Table 32 PES24T3G2 (27x27mm 676-Pin) Alphabetical Signal List (Part 4 of 5)
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IDT 89HPES24T3G2 Data Sheet
SSMBADDR_1 I A9 SMBus
SSMBADDR_2 I B10
SSMBADDR_3 I A10
SSMBADDR_5 I B11
SSMBCLK I/O A11
SSMBDAT I/O B12
SWMODE_0 I B14 System
SWMODE_1 I A15
SWMODE_2 I B15
VDDCORE, VDDI/O,
VDDPEA, VDDPEHA,
VDDPETA
See Tables 27 and 28 for a listing of power pins.
VSS See Table 29 for a listing of ground pins.
Signal Name I/O Type Location Signal Category
Table 32 PES24T3G2 (27x27mm 676-Pin) Alphabetical Signal List (Part 5 of 5)
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IDT 89HPES24T3G2 Data Sheet
Option B Pack age Pinout (27x27mm) — Top View
1 2 3 4 5 6 7 8 910111213141516
Vss (Ground)
VDDCore (Power)
A
B
VDDI/O (Power)
17 18 19 20 21 22 23 24 25 26
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
VDDPETA (Transmitter Power)
VDDPEA (Analog Power)
VDDPEHA (High Analog Power)
Signals
1 2 3 4 5 6 78 910111213141516
17 18 19 20 21 22 23 24 25 26
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
X
No Connect
XX
XXXXXXX X
X
X
XX
X
X
XX
X
X
XX
X
X
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IDT 89HPES24T3G2 Data Sheet
27x27mm Package Drawing — 676-Pin BL676/BR676
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IDT 89HPES24T3G2 Data Sheet
27x27mm Package Dr awing — Page Two
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IDT 89HPES24T3G2 Data Sheet
Revision History
January 15, 2009: Publication of final data sheet.
February 11, 2009: R e vised AC Timing Characteristics table and DC Electrical Characteristics table to correct typos.
March 6, 2009: Added industrial temperature.
April 7, 2009: In Valid Combinations, changed ZB to ZC silicon for commercial temperature.
February 2, 2010: Added new section Absolute Maximum Voltage Rating with table.
September 13, 2010: In Table 8, changed Buffer type for PCI Express from CML to PCIe differential and changed reference clocks to HCSL.
September 29, 2010: Corrected typo in Ordering Code for 324-ball Green FCBGA package, Industrial Temperature.
January 20, 2011: A dded new Table 25, Package Trace Length for 19x19mm FCBGA package.
March 30, 2011: In Table 13, added VddPETA to footnote #1.
June 1, 2012: Changed ZC to ZF silicon on the Ordering page.
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for SALES:
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fax: 408-284-2775
www.idt.com
for Tech Support:
email: ssdhelp@idt.com
phone: 408-284-8208
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Ordering Information
Valid Combinations
Option A (19x19mm)
Option B (27x27mm)
89HPES24T3G2ZFAL 324-ball FCBGA package, Commercial Temperature
89HPES24T3G2ZFALG 324-ball Green FCBGA package, Commercial Temperature
89HPES24T3G2ZFALI 324-ball FCBGA package, Industrial Temperature
89HPES24T3G2ZFALGI 324-ball Green FCBGA package, Industrial Temperature
89HPES24T3G2ZFBL 676-ball FCBGA package, Commercial Temperature
89HPES24T3G2ZFBLG 676-ball Green FCBGA package, Commercial Temperature
89HPES24T3G2ZFBLI 676-ball FCBGA package, Industrial Temperature
89HPES24T3G2ZFBLGI 676-ball Green FCBGA package, Industrial Temperature