PS024009-0506 Disclaimer
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Telephone: 408.558.8500
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names mentioned herein may be trademarks of the companies with which they are associated.
Document Disclaimer
© 2006 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology
described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR
PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED
IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY
INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED
HEREIN OR OTHERWISE. Except with the express written approval ZiLOG, use of information, devices, or technology as
critical components of life support systems is not authorized. No licenses or other rights are conveyed, implicitly or otherwise, by
this document under any intellectual property rights.
PS024009-0506 Revision History
ZGR163L
Product Specification
iii
Revision History
Each instance in the Revision History table reflects a change to this document from its
previous revision. For more details, refer to the corresponding pages or appropriate link in
the table.
Date
Revision
Level
Description
Page
No.
December
2004
02 Updated to incorporate minor changes to Figure 44 and Figure 47.
Added 4 K Parts information in the Ordering Section.
67, 69
81
Removed mask option note, and changed temperature ranges in Table 6
and Table 11. Added characterization data to Table 7 and added new
Tables 8 and 9.
2, 7, 8,
9, 10,
11, 14
Removed Preliminary designation All
January
2005
03
Changed low power consumption value to 5 mW. Changed STOP and
HALT mode current values
to 1.3
mA and 0.5 mA respectively. Minor
corrections to Tables 7, 8, 9.
1, 9,
10, 11
March
2005
04 Minor correction/addition to the Ordering section. 84
June
2005
05 Incorporated 1 K and 2 K parts. All
June
2005
06 Changed part number for emulator/programmer. 85
October
2005
07 Updated
Ordering Information
on page 83
.84
November
2005
08 Updated
Ordering Information
on page 83, added Caution for I/O ports 0
and 2 on pages 15 and 16, and added new Clock information on pages
50 and 51.
15, 16,
50, 51,
84
May
2006
09
Added pin P22 to the SMR block input, Figure 30.48
ZGR163L
Product Specification
PS024009-0506 Table of Contents
iv
Table of Contents
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
XTAL1 Crystal 1 (Time-Based Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
XTAL2 Crystal 2 (Time-Based Output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Port 3 (P37–P30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Expanded Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Counter/Timer Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Ping-Pong Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Expanded Register File Control Registers (0D) . . . . . . . . . . . . . . . . . . . . . . 55
Expanded Register File Control Registers (0F) . . . . . . . . . . . . . . . . . . . . . . 60
Standard Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
ZGR163L
Product Specification
PS024009-0506 Table of Contents
v
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Document Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
ZGR163L
Product Specification
PS024009-0506 List of Figures
vi
List of Figures
Figure 1. ZGR163L MCU Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Counter/Timers Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. 20-Pin DIP/SOIC/SSOP Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. 28-Pin DIP/SOIC/SSOP Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. Port 0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Port 2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. Port 3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. Port 3 Counter/Timer Output Configuration . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 9. Program Memory Map for ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10. Expanded Register File Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11. Register Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12. Register Pointer—Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 13. Glitch Filter Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 14. Transmit Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 15. 8-Bit Counter/Timer Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 16. T8_OUT in Single-Pass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 17. T8_OUT in Modulo-N Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 18. Demodulation Mode Count Capture Flowchart . . . . . . . . . . . . . . . . . . . . . 34
Figure 19. Demodulation Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 20. 16-Bit Counter/Timer Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 21. T16_OUT in Single-Pass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 22. T16_OUT in Modulo-N Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 23. Ping-Pong Mode Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 24. Output Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 25. Interrupt Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 26. Oscillator Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 27. Port Configuration Register (PCON) (Write Only). . . . . . . . . . . . . . . . . . . 45
Figure 28. Stop Mode Recovery Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 29. SCLK Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 30. Stop Mode Recovery Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 31. Stop Mode Recovery Register 2 ((0F) DH:D2–D4, D6 Write Only) . . . . . 50
Figure 32. Watch-Dog Timer Mode Register (Write Only) . . . . . . . . . . . . . . . . . . . . . 51
Figure 33. Resets and WDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
ZGR163L
Product Specification
PS024009-0506 List of Figures
vii
Figure 34. TC8 Control Register ((0D) 00H: Read/Write Except Where Noted) . . . . 55
Figure 35. T8 and T16 Common Control Functions ((0D) 01H: Read/Write) . . . . . . 56
Figure 36. T16 Control Register ((0D) 02H: Read/Write Except Where Noted) . . . . 57
Figure 37. T8/T16 control Register (0D) 03H: Read/Write (Except Where Noted) . . 58
Figure 38. Voltage Detection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 39. Port Configuration Register (PCON) ((0F)00H: Write Only . . . . . . . . . . . 60
Figure 40. Stop Mode Recovery Register ((0F) 0BH: D6–D0=Write Only, D7=Read
Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 41. Stop Mode Recovery Register 2 ((0F) 0DH: D2–D4, D6 Write Only) . . . 62
Figure 42. Watch-Dog Timer Register ((0F) 0FH: Write Only). . . . . . . . . . . . . . . . . . 63
Figure 43. Port 2 Mode Register (F6H: Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 44. Port 3 Mode Register (F7H: Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 45. Port 0 Register (F8H: Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 46. Interrupt Priority Register (F9H: Write Only) . . . . . . . . . . . . . . . . . . . . . . 66
Figure 47. Interrupt Request Register (FAH: Read/Write) . . . . . . . . . . . . . . . . . . . . . 67
Figure 48. Interrupt Mask Register (FBH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 49. Flag Register (FCH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 50. Register Pointer (FDH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 51. Stack Pointer High (FEH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 52. Stack Pointer Low (FFH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 53. Test Load Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 54. AC Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 55. 20-Pin DIP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 56. 20-Pin SOIC Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 57. 20-Pin SSOP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 58. 28-Pin SOIC Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 59. 28-Pin DIP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 60. 28-Pin SSOP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
ZGR163L
Product Specification
PS024009-0506 List of Tables
viii
List of Tables
Table 1. Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. ZGR163L MCU Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table 3. 20-Pin DIP/SOIC/SSOP Pin Identification . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. 28-Pin DIP/SOIC/SSOP Pin Identification. . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Port 3 Pin Function Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 6. CTR0(0D)00h Counter/Timer8 Control Register . . . . . . . . . . . . . . . . . . . . 23
Table 7. CTR1(0D)01h T8 and T16 Common Functions . . . . . . . . . . . . . . . . . . . . . 25
Table 8. CTR2(0D)02h: Counter/Timer16 Control Register . . . . . . . . . . . . . . . . . . . 28
Table 9. CTR3(0D)03h T8/T16 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 10. Interrupt Types, Sources, and Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 11. IRQ Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 12. SMR2(F)0DH:Stop Mode Recovery Register 2*. . . . . . . . . . . . . . . . . . . . . 47
Table 13. Stop Mode Recovery Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 14. Watchdog Timer Time Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 15. ROM Selectable Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 16. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 17. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 18. ZGR163LS DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 19. ZGR163LE DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 20. ZGR163LA DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 21. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
ZGR163L
Product Specification
PS024009-0506
1
Architectural Overview
The ZGR163L is a ROM-based member of the MCU family of general purpose
microcontrollers. With 1 KB to 16 KB of Program Memory and 237 B of general purpose
RAM, ZiLOG’s CMOS microcontrollers offer fast-executing, efficient use of memory,
sophisticated interrupts, input/output bit manipulation capabilities, automated pulse
generation/reception, and internal key-scan pull-up transistors.
The ZGR163L architecture (see Figure 1) is based on ZiLOG’s 8-bit microcontroller core
with an Expanded Register File allowing access to register-mapped peripherals, input/
output (I/O) circuits, and powerful counter/timer circuitry. The Z8® core offers a flexible
I/O scheme, an efficient register and address space structure, and a number of ancillary
features that are useful in many consumer, automotive, computer peripheral, and battery-
operated hand-held applications.
There are three basic address spaces available to support a wide range of configurations:
Program Memory, Register File and Expanded Register File. The register file is composed
of 256 B of RAM. It includes three I/O port registers, 16 control and status registers, and
237 general-purpose registers. The Expanded Register File consists of two additional
register groups (F and D).
To unburden the program from coping with such real-time problems as generating com-
plex waveforms or receiving and demodulating complex waveform/pulses, the ZGR163L
offers a new intelligent counter/timer architecture with 8-bit and 16-bit counter/timers
(see Figure 2). Also included are a large number of user-selectable modes and two
on-board comparators to process analog signals with separate reference voltages.
Power connections use the conventional descriptions listed in Table 1.
Table 1. Power Connections
Connection Circuit Device
Power V
CC
V
DD
Ground GND V
SS
ZGR163L
Product Specification
PS024009-0506 Features
2
Features
Table 2 lists the features of the ZiLOG’s ZGR163L members. Additional features are
listed below the table.
The additional features include:
•
Low power consumption–5 mW (typical)
•
T = Temperature
S = Standard, 0 °C to +70 °C
E = Extended, -40 °C to +105 °C
A = Automotive, -40 °C to +125 °C
•
Speed, 8 MHz
•
Three standby modes:
–
STOP—1.3 μA (typical)
–
HALT—0.5 mA (typical)
–
Low voltage reset
•
Special architecture to automate both generation and reception of complex pulses or
signals:
–
One programmable 8-bit counter/timer with two capture registers and two load
registers
–
One programmable 16-bit counter/timer with one 16-bit capture register pair and
one 16-bit load register pair
–
Programmable input glitch filter for pulse reception
•
Six priority interrupts
–
Three external
–
Two assigned to counter/timers
–
One low-voltage detection interrupt
•
Low voltage detection and high voltage detection flags
Table 2. ZGR163L MCU Features
Device ROM RAM* (Bytes) I/O Lines Voltage Range
ZGR163L ROM MCU
Family
1 K, 2 K,
4 K, 8 K,
16 K
237 16, 24 2.0 –3.6 V
* General purpose
ZGR163L
Product Specification
PS024009-0506 Features
3
•
Programmable Watchdog Timer (WDT)
•
Power-on reset (POR)
•
Two independent comparators with programmable interrupt polarity
•
Selectable pull-up transistors on ports 0, 2, and 3
•
Mask options
•
Port 0: 0–3 pull-ups
•
Port 0: 4–7 pull-ups
•
Port 2: 0–7 pull-ups
•
Port 3: 0–3 pull-ups
•
Watchdog Timer at Power-on reset
ZGR163L
Product Specification
PS024009-0506 Features
4
Functional Block Diagram
Figure 1 illustrates the ZGR163L MCU functional block diagram.
Figure 1. ZGR163L MCU Functional Block Diagram
Z8® Core
Port 2
Port 0
P21
P22
P23
P24
P25
P26
P27
P20
I/O Bit
Programmable
P04
P05
P06
P07
P00
P01
P02
P03
I/O Nibble
Programmable
Register File
256 x 8-Bit
Register Bus
Internal
Address Bus
Internal
Data Bus
Expanded
Register
File
Expanded
Register Bus
Z8
®
Core
Counter/Timer 8
8-Bit
Counter/Timer 16
16-Bit
V
DD
V
SS
XTAL
Pref1/P30
P31
P32
P33
P34
P35
P36
P37
Port 3
Machine
Timing &
Instruction
Control
Power
4
4
ROM
Up to 16K x 8
Watch-Dog
Timer
Low Voltage
Detection
High Voltage
Detection
2-Comparators
Note: Refer to the specific package for available pins.
Power-On
Reset
ZGR163L
Product Specification
PS024009-0506 Features
5
Figure 2. Counter/Timers Diagram
HI16 LO16
16-Bit
T16
TC16H TC16L
HI8 LO8
And/Or
Logic
Clock
Divider
Glitch
Filter
Edge
Detect
Circuit 8-Bit
T8
TC8H
TC8L
88
16
8
Input
SCLK
1248
Timer 16
Timer 8/16
Timer 8
88
88
8
ZGR163L
Product Specification
PS024009-0506 Features
6
Pin Description
The pin configuration for the 20-pin DIP/SOIC/SSOP is illustrated in Figure 3 and
described in Table 3. The pin configuration for the 28-pin DIP/SOIC/SSOP are illustrated
in Figure 4 and described in Table 4.
Figure 3. 20-Pin DIP/SOIC/SSOP Pin Configuration
Table 3. 20-Pin DIP/SOIC/SSOP Pin Identification
Pin No. Symbol Function Direction
1–3 P25–P27 Port 2, Bits 5,6,7 Input/Output
4 P07 Port 0, Bit 7 Input/Output
5V
DD
Power Supply
6 XTAL2 Crystal Oscillator Clock Output
7 XTAL1 Crystal Oscillator Clock Input
8–10 P31–P33 Port 3, Bits 1,2,3 Input
11,12 P34, P36 Port 3, Bits 4,6 Output
13 P00/Pref1/P30 Port 0, Bit 0/Analog reference input
Port 3, Bit 0
Input/Output for P00
Input for Pref1/P30
14 P01 Port 0, Bit 1 Input/Output
15 V
SS
Ground
16–20 P20–P24 Port 2, Bits 0,1,2,3,4 Input/Output
P25
P26
P27
P07
VDD
XTAL2
XTAL1
P31
P32
P33
P24
P23
P22
P21
P20
VSS
P01
P00/Pref1/P30
P36
P34
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
20-Pin
DIP
SOIC
SSOP
ZGR163L
Product Specification
PS024009-0506 Features
7
Figure 4. 28-Pin DIP/SOIC/SSOP Pin Configuration
Table 4. 28-Pin DIP/SOIC/SSOP Pin Identification
Pin No. Symbol Direction Description
1-3 P25-P27 Input/Output Port 2, Bits 5,6,7
4-7 P04-P07 Input/Output Port 0, Bits 4,5,6,7
8V
DD Power supply
9 XTAL2 Output Crystal, oscillator clock
10 XTAL1 Input Crystal, oscillator clock
11–13 P31-P33 Input Port 3, Bits 1,2,3
14 P34 Output Port 3, Bit 4
15 P35 Output Port 3, Bit 5
16 P37 Output Port 3, Bit 7
17 P36 Output Port 3, Bit 6
18 Pref1 Input Analog ref input; connect to VCC if not used
Port 3 Bit 0
19-21 P00-P02 Input/Output Port 0, Bits 0,1,2
22 VSS Ground
23 P03 Input/Output Port 0, Bit 3
24-28 P20-P24 Input/Output Port 2, Bits 0-4
P24
P23
P22
P21
P20
P03
VSS
P02
P01
P00
Pref1/P30
P36
P37
P35
P25
P26
P27
P04
P05
P06
P07
VDD
XTAL2
XTAL1
P31
P32
P33
P34
1
28-Pin
PDIP
SOIC
SSOP
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ZGR163L
Product Specification
PS024009-0506 Pin Functions
8
Pin Functions
XTAL1 Crystal 1 (Time-Based Input)
This pin connects a parallel-resonant crystal, ceramic resonator, or LC to the on-chip oscil-
lator input. Additionally, an external single-phase clock can be connected to the on-chip
oscillator input.
XTAL2 Crystal 2 (Time-Based Output)
This pin connects a parallel-resonant crystal or ceramic resonant to the on-chip oscillator
output.
Input/Output Ports
Input/Output ports are described in the following sections.
The CMOS input buffer for each port 0 or 2 pin is always connected to the pin, even when
the pin is configured as an output. If the pin is configured as an open-drain output and no
signal is applied, a High output state can cause the CMOS input buffer to float. This might
lead to excessive leakage current of more than 100 μA. To prevent this leakage, connect the
pin to an external signal with a defined logic level or insure its output state is Low,
especially during STOP mode.
Internal pull-ups are disabled on any given pin or group of port pins when programmed into
output mode.
Port 0 and 2 have both input and output capability. The input logic is always present no mat-
ter whether the port is configured as input or output. When doing a READ instruction, it
will read the actual value at the input logic not from the output buffer. In addition, the in-
struction of "OR", "AND", "XOR" are read-modify-write instructions. It will first read the
port and then modify the value and load back to the port.
Precaution should be taken if the port is configured as open-drain output or driving some
circuit that may make the voltage different from the desired output logic. For example, pins
P00-P07 are not connecting to anything else. If it is configured as open-drain output with
outputting logic ONE, it is a floating port and will read back as ZERO. The following in-
struction will set P00-P07 all LOW.
AND P0,#%F0
Caution:
ZGR163L
Product Specification
PS024009-0506 Pin Functions
9
Port 0 (P07–P00)
Port 0 is an 8-bit, bidirectional, and CMOS-compatible port. These eight I/O lines are
configured under software control as a nibble I/O port. The output drivers are push-pull or
open-drain controlled by bit D2 in the PCON register.
If one or both nibbles are required for I/O operation, they must be configured by writing to
the Port 0 mode register. After a hardware reset, Port 0 is configured (see Figure 5) as an
input port.
An optional pull-up transistor is available as a OTP/mask option on all Port 0 bits with
nibble select.
Internal pull-ups are disabled on any given pin or group of port pins when programmed
into Output mode.
The Port 0 direction is reset to its default state following an SMR.
Figure 5. Port 0 Configuration
Note:
4
4
Z8
®
Port 0 (I/O)
Pad
In
Out
I/O
Open-Drain
Resistive
Transistor
Pull-up
V
CC
Mask
Option
ZGR163L
Product Specification
PS024009-0506 Pin Functions
10
Port 2 (P27–P20)
Port 2 is an 8-bit, bidirectional, CMOS-compatible I/O port (see Figure 6). These eight I/O
lines can be independently configured under software control as inputs or outputs. Port 2
is always available for I/O operation. A mask option connects eight pull-up transistors on
this port. Bits programmed as outputs are globally programmed as either push-pull or
open-drain. The POR resets with the eight bits of Port 2 configured as inputs.
Port 2 also has an 8-bit input OR and AND gate, which can be used to wake up the part.
P20 can be programmed to access the edge-detection circuitry in Demodulation mode.
Figure 6. Port 2 Configuration
Port 2 (I/O)
Pad
In
Out
I/O
Open-Drain Resistive
Transistor
Pull-up
VCC
Mask
Option
Z8
®
ZGR163L
Product Specification
PS024009-0506 Pin Functions
11
Port 3 (P37–P30)
Port 3 is an 8-bit, CMOS-compatible fixed I/O port (see Figure 7). Port 3 consists of four
fixed input (P33–P30) and four fixed output (P37–P34), which are configured under
software control for interrupt and as output from the counter/timers. P30, P31, P32, and
P33 are standard CMOS inputs; P34, P35, P36, and P37 are push-pull outputs.
Figure 7. Port 3 Configuration
-
Port 3 (I/O)
P32 (AN2)
P31 (AN1)
Pref1
From Stop Mode Recovery Source of SMR
P33
IRQ2, P31 Data
Pref1/P30
P31
P32
P33
P34
P35
P36
P37
D1 1 = Analog
0 = Digital
R247 = P3M
+
-
+IRQ0, P32 Data
IRQ1, P33 Data
Comp
1
Comp2
Dig.
An.
Z8
®
ZGR163L
Product Specification
PS024009-0506 Pin Functions
12
Two on-board comparators process analog signals on P31 and P32, with reference to the
voltage on Pref1 and P33. The analog function is enabled by programming the Port 3
Mode Register (bit 1). P31 and P32 are programmable as rising, falling, or both edge trig-
gered interrupts (IRQ register bits 6 and 7). Pref1 and P33 are the comparator reference
voltage inputs. Access to the Counter Timer edge-detection circuit is through P31 or P20
(see “T8 and T16 Common Functions—T8 and T16 Common Functions—CTR1(0D)01h
on page 25). Other edge detect and IRQ modes are described in Table 5.
Comparators are powered down by entering STOP Mode. For P31–P33 to be used in a
Stop Mode Recovery (SMR) source, these inputs must be placed into Digital mode.
2
Port 3 also provides output for each of the counter/timers and the AND/OR Logic
(see Figure 8). Control is performed by programming bits D5–D4 of CTR1, bit 0 of CTR0,
and bit 0 of CTR2.
Table 5. Port 3 Pin Function Summary
Pin No. I/O Counter/Timers Comparator Interrupt
Pref1/P30 IN RF1
P31 IN IN AN1 IRQ2
P32 IN AN2 IRQ0
P33 IN RF2 IRQ1
P34 OUT T8 AO1
P35 OUT T16
P36 OUT T8/16
P37 OUT AO2
P20 I/O IN
Note:
ZGR163L
Product Specification
PS024009-0506 Pin Functions
13
Figure 8. Port 3 Counter/Timer Output Configuration
Pad
P34
Comp
1
V
DD
MUX
PCON, D0
MU
X
CTR0, D0
P31
P30 (Pref
1)
P34
data
T8_Out
+
Pad
P35
V
DD
MUX
CTR2,
Out 35
T16_Out
Pad
P36
V
DD
MUX
CTR1, D6
Out 36
T8/
Pad
P3
V
DD
MUX
PCON, D0
P37
data
-
P31
P3M D1
Comp
2
P32
P33
+
-
P32
P3M D1
ZGR163L
Product Specification
PS024009-0506 Pin Functions
14
Comparator Inputs
In ANALOG mode, P31 and P32 have a comparator front end. The comparator reference
is supplied to P33 and Pref1. In this mode, the P33 internal data latch and its
corresponding IRQ1 are diverted to the SMR sources (excluding P31, P32, and P33) as
indicated in Figure 7 on page 11. In digital mode, P33 is used as D3 of the Port 3 input
register, which then generates IRQ1.
Comparators are powered down by entering STOP mode. For P31–P33 to be used in a
STOP Mode Recovery source, these inputs must be placed into Digital mode.
Comparator Outputs
These channels are programmed to be output on P34 and P37 through the PCON register.
Note:
ZGR163L
Product Specification
PS024009-0506 Pin Functions
15
Functional Description
These devices incorporate special functions to enhance the functionality of Z8® in
consumer and battery-operated applications.
Program Memory
These devices address from 1 KB to16 KB of Program Memory. The first 12 Bytes are
reserved for interrupt vectors. These locations contain the six 16-bit vectors that
correspond to the six available interrupts.
RAM
The ZGR163L product family features 237 Bytes of general-purpose RAM. See Figure 9.
ZGR163L
Product Specification
PS024009-0506 Pin Functions
16
Figure 9. Program Memory Map for ROM
Expanded Register File
The register file has been expanded to allow for additional system control registers and for
mapping of additional peripheral devices into the register address area. The Z8® register
address space (0 through15 (OFh) has been implemented as 16 banks, with 16 registers
per bank. These register banks are known as the ERF (Expanded Register File). Bits 7–4
On-Chip
ROM
Reset Start
IRQ5
IRQ5
IRQ4
IRQ4
IRQ3
IRQ3
IRQ2
IRQ2
IRQ1
IRQ1
IRQ0
IRQ0
12
11
10
9
8
7
6
5
4
3
2
1
0
Location of
first Byte of
instruction
executed
after RESET
Interrupt
Vector (Lower
Interrupt
Vector (Upper
Not Accessible
Maximum ROM size
ZGR163L
Product Specification
PS024009-0506 Pin Functions
18
Figure 10. Expanded Register File Architecture
UUUUUUU0
00000000
00000000
00000000
00
0F
7F
F0
FF
FF SPL
00000000
UUUUUUUU
00000000
UUUUUUUU
UUUUUUUU
UUUUUUUU
11111111
00000000
11001111
UUUUUUUU
UUUUUUUU
UUUUUUUU
UUUUUUUU
UUUUUUUU
FE SPH
FD RP
FC FLAGS
FB IMR
FA IRQ
F9 IPR
F8 P01M
F7 P3M
F6 P2M
F5 Reserved
F4 Reserved
F3 Reserved
F2 Reserved
F1 Reserved
F0 Reserved
D7
D6 D5 D4 D3 D2 D1 D
0
UU001101
U01000U0
11111110
(F) 0F WDTMR
(F) 0E Reserved
(F) 0D SMR2
(F) 0C Reserved
(F) 0B SMR
(F) 0A Reserved
(F) 09 Reserved
(F) 08 Reserved
(F) 07 Reserved
(F) 06 Reserved
(F) 05 Reserved
(F) 04 Reserved
(F) 03 Reserved
(F) 02 Reserved
(F) 01 Reserved
(F) 00 PCON
76543210
Expanded Register
Bank Pointer
Working Register
UUUUUUUU
UUUUUUUU
00000000
(D) 0C LVD
(D) 0B HI8
(D) 0A LO8
(D) 09 HI16
(D) 08 LO16
(D) 07 TC16H
(D) 06 TC16L
(D) 05 TC8H
(D) 04 TC8L
(D) 03 CTR3
(D) 02 CTR2
(D) 01 CTR1
(D) 00 CTR0
Group Pointer
Register File (Bank 0)**
00011111
*
*
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
U = Unknown
* Is not reset with a Stop Mode Recovery
** All addresses are in hexadecimal
↑ Is not reset with a Stop Mode Recovery, except Bit 0
↑↑ Bit 5 is not reset with a Stop Mode Recovery
↑↑↑ Bits 5,4,3,2 not reset with a Stop Mode Recovery
↑↑↑↑ Bits 5 and 4 not reset with a Stop Mode Recovery
↑↑↑↑↑ Bits 5,4,3,2,1 not reset with a Stop Mode Recovery
Expanded Reg. Bank 0/Group (0)
(0) 03 P3
(0) 02 P2
(0) 00 P0
0U
U
U
↑↑↑↑↑
↑↑↑↑
↑↑↑
↑↑
*
*
*
*
*
*
*
*
*
*
*
Expanded Reg. Bank F/Group 0**
Register**
Register Pointer
Z8® Standard Control Registers
Expanded Reg. Bank D/Group 0
↑
Reset Condition
ZGR163L
Product Specification
PS024009-0506 Pin Functions
19
The upper nibble of the register pointer (see Figure 11) selects which working register
group, of 16 bytes in the register file, is accessed out of the possible 256. The lower nibble
selects the expanded register file bank and banks 0, F, and D are implemented. A 0h in the
lower nibble allows the normal register file (bank 0) to be addressed. Any other value
from 1h to Fh exchanges the lower 16 registers to the selected expanded register bank.
Figure 11. Register Pointer
Example: (See Figure 10 on page 18)
R253 RP = 00h
R0 = Port 0
R2 = Port 2
R3 = Port 3
But if:
R253 RP = 0Dh
R0 = CTRL0
R1 = CTRL1
R2 = CTRL2
R3 = Reserved
R253 RP
D7 D6 D5 D4 D3 D2 D1 D0
Expanded Register
File Pointer
Working Register
Pointer
Default Setting After Reset = 0000 0000
ZGR163L
Product Specification
PS024009-0506 Pin Functions
20
The counter/timers are mapped into ERF group D. Access is easily performed using the
following:
LD RP, #0Dh ;Select ERF D for
access to bank D
;(working register group 0)
LD R0,#xx ;load CTR0
LD 1, #xx ;load CTR1
LD R1, 2 ;CTR2→CTR1
LD RP, #0Dh ;Select ERF D for
access to bank D
;(working register group 0)
LD RP, #7Dh ;Select expanded register bank D and
working
;register group 7 of bank 0 for access.
LD 71h, 2 ;CTRL2→register 71h
LD R1, 2 ;CTRL2→register 71h
Register File
The register file (bank 0) consists of 3 I/O port registers, 237 general-purpose registers, 14
control and status registers (R0, R2, R3, R4–R239, and R240–R255, respectively), and
two expanded register Banks D (see Table 6) and F. Instructions can access registers
directly or indirectly through an 8-bit address field, thereby allowing a short, 4-bit register
address to use the Register Pointer (see Figure 12). In the 4-bit mode, the register file is
divided into 16 working register groups, each occupying 16 continuous locations. The
Register Pointer addresses the starting location of the active working register group.
Register address E0h–EFh can only be accessed through working registers and indirect
addressing modes.
Note:
ZGR163L
Product Specification
PS024009-0506 Pin Functions
21
Figure 12. Register Pointer—Detail
Stack
The internal register file is used for the stack. An 8-bit Stack Pointer SPL (R255) is used
for the internal stack that resides in the general-purpose registers (R4–R239). SPH (R254)
can be used as a general-purpose register.
Timers
T8_Capture_HI—HI8(0D)0Bh
This register holds the captured data from the output of the 8-bit Counter/Timer0.
Typically, this register holds the number of counts when the input signal is 1.
Field Bit Position Description
T8_Capture_HI [7:0] R/W Captured Data - No Effect
R
7
R
6
R
5
R
4
R
3
R
2
R
1
R
The upper nibble of the register file address
provided by the register pointer specifies the
active working-register group.
Specified Working
Register Group
Register Group 1
Register Group 0
I/O Ports
R253
The lower nibble of the
register file address provided
by the instruction points to
the specified register.
* RP = 00: Selects Register Bank 0, Working Register Group 0
R15 to R0
R15 to R4 *
R3 to R0 *
40
3F
30
2F
20
1F
10
0F
00
Register Group 2
FF
F0
ZGR163L
Product Specification
PS024009-0506 Pin Functions
22
T8_Capture_LO—L08(0D)0Ah
This register holds the captured data from the output of the 8-bit Counter/Timer0. Typi-
cally, this register holds the number of counts when the input signal is 0.
T16_Capture_HI—HI16(0D)09h
This register holds the captured data from the output of the 16-bit Counter/Timer16. This
register holds the MS-Byte of the data.
T16_Capture_LO—L016(0D)08h
This register holds the captured data from the output of the 16-bit Counter/Timer16. This
register holds the LS-Byte of the data.
Counter/Timer2 MS-Byte Hold Register—TC16H(0D)07h
Counter/Timer2 LS-Byte Hold Register—TC16L(0D)06h
Field Bit Position Description
T8_Capture_L0 [7:0] R/W Captured Data - No Effect
Field Bit Position Description
T16_Capture_HI [7:0] R/W Captured Data - No Effect
Field Bit Position Description
T16_Capture_L
O
[7:0] R/W Captured Data - No Effect
Field Bit Position Description
T16_Data_HI [7:0] R/W Data
Field Bit Position Description
T16_Data_LO [7:0] R/W Data
ZGR163L
Product Specification
PS024009-0506 Pin Functions
23
Counter/Timer8 High Hold Register—TC8H0(D)05h
Counter/Timer8 Low Hold Register—TC8L(0D)04h
CTR0 Counter/Timer8 Control Register—CTR0(0D)00h
Table 6 lists and briefly describes the fields for this register.
Field Bit Position Description
T8_Level_HI [7:0] R/W Data
Field Bit Position Description
T8_Level_LO [7:0] R/W Data
Table 6. CTR0(0D)00h Counter/Timer8 Control Register
Field Bit Position Value Description
T8_Enable 7------- R/W 0*
1
0
1
Counter Disabled
Counter Enabled
Stop Counter
Enable Counter
Single/Modulo-N -6------- R/W 0*
1
Modulo-N
Single Pass
Time_Out --5------ R/W 0**
1
0
1
No Counter Time-Out
Counter Time-Out Occurred
No Effect
Reset Flag to 0
T8 _Clock ---43--- R/W 0 0**
0 1
1 0
1 1
SCLK
SCLK/2
SCLK/4
SCLK/8
Capture_INT_Mask -----2-- R/W 0**
1
Disable Data Capture Interrupt
Enable Data Capture Interrupt
ZGR163L
Product Specification
PS024009-0506 Pin Functions
24
T8 Enable
This field enables T8 when set (written) to 1.
Single/Modulo-N
When set to 0 (Modulo-N), the counter reloads the initial value when the terminal count is
reached. When set to 1 (Single-Pass), the counter stops when the terminal count is
reached.
Timeout
This bit is set when T8 times out (terminal count reached). To reset this bit, write a 1 to its
location.
Writing a 1 is the only way to reset the Terminal Count status condition. Reset this bit
before using/enabling the counter/timers.
The first clock of T8 might not have complete clock width and can occur any time when
enabled.
Take care when using the OR or AND commands to manipulate CTR0, bit 5 and CTR1,
bits 0 and 1 (Demodulation Mode). These instructions use a Read-Modify-Write sequence
in which the current status from the CTR0 and CTR1 registers is ORed or ANDed with the
designated value and then written back into the registers.
T8 Clock
This bit defines the frequency of the input signal to T8.
Counter_INT_Mask ------1- R/W 0**
1
Disable Time-Out Interrupt
Enable Time-Out Interrupt
P34_Out -------0 R/W 0*
1
P34 as Port Output
T8 Output on P34
Note:
*
Indicates the value at Power-on reset.
*
*Indicates the value at Power-on reset. Not reset with a Stop Mode Recovery.
Table 6. CTR0(0D)00h Counter/Timer8 Control Register (Continued)
Field Bit Position Value Description
Caution:
Note:
ZGR163L
Product Specification
PS024009-0506 Pin Functions
25
Capture_INT_Mask
Set this bit to allow an interrupt when data is captured into either LO8 or HI8 upon a posi-
tive or negative edge detection in Capture Mode.
Counter_INT_Mask
Set this bit to allow an interrupt when T8 has a timeout.
P34_Out
This bit defines whether P34 is used as a normal output pin or the T8 output.
T8 and T16 Common Functions—CTR1(0D)01h
This register controls the functions in common with the T8 and T16.
Table 7 lists and briefly describes the fields for this register
.
Table 7. CTR1(0D)01h T8 and T16 Common Functions
Field Bit Position Value Description
Mode
7-------
R/W 0*
1
Transmit Mode
Demodulation Mode
P36_Out/
Capture_Input
-6------
R/W
0*
1
0*
1
Transmit Mode
Port Output
T8/T16 Output
Demodulation Mode
P31
P20
T8/T16_Logic/
Edge _Detect
--54----
R/W
00**
01
10
11
00**
01
10
11
Transmit Mode
AND
OR
NOR
NAND
Demodulation Mode
Falling Edge
Rising Edge
Both Edges
Reserved
ZGR163L
Product Specification
PS024009-0506 Pin Functions
26
Mode
If the result is 0, the counter/timers are in Transmit mode; otherwise, they are in
Demodulation Mode.
P36_Out/Capture_Input
In Transmit Mode, this bit defines whether P36 is used as a normal output pin or the
combined output of T8 and T16.
In Demodulation Mode, this bit defines whether the input signal to the Counter/Timers is
from P20 or P31.
Transmit_Submode/
Glitch_Filter
----32--
R/W
00
01
10
11
00
01
10
11
Transmit Mode
Normal Operation
Ping-Pong Mode
T16_Out = 0
T16_Out = 1
Demodulation Mode
No Filter
4 SCLK Cycle
8 SCLK Cycle
Reserved
Initial_T8_Out/
Rising Edge
------1-
R/W
R
W
0
1
0
1
0
1
Transmit Mode
T8_OUT is 0 Initially
T8_OUT is 1 Initially
Demodulation Mode
No Rising Edge
Rising Edge Detected
No Effect
Reset Flag to 0
Initial_T16_Out/
Falling_Edge
-------0
R/W
R
W
0
1
0
1
0
1
Transmit Mode
T16_OUT is 0 Initially
T16_OUT is 1 Initially
Demodulation Mode
No Falling Edge
Falling Edge Detected
No Effect
Reset Flag to 0
Note:
*Default at Power-on reset
**Indicates value upon Power-on reset. Not reset with a Stop Mode Recovery.
Table 7. CTR1(0D)01h T8 and T16 Common Functions (Continued)
Field Bit Position Value Description
ZGR163L
Product Specification
PS024009-0506 Pin Functions
27
If the input signal is from Port 31, a capture event may also generate an IRQ2 interrupt. To
prevent generating an IRQ2, either disable the IRQ2 interrupt by clearing its IMR bit D2
or use P20 as the input.
T8/T16_Logic/Edge_Detect
In Transmit Mode, this field defines how the outputs of T8 and T16 are combined (AND,
OR, NOR, NAND).
In Demodulation Mode, this field defines which edge should be detected by the edge
detector.
Transmit_Submode/Glitch Filter
In Transmit Mode, this field defines whether T8 and T16 are in the Ping-Pong mode or in
independent normal operation mode. Setting this field to “Normal Operation Mode” ter-
minates the “Ping-Pong Mode” operation. When set to 10, T16 is immediately forced to a
0; a setting of 11 forces T16 to output a 1.
In Demodulation Mode, this field defines the width of the glitch that must be filtered out.
Initial_T8_Out/Rising_Edge
In Transmit Mode, if 0, the output of T8 is set to 0 when it starts to count. If 1, the output
of T8 is set to 1 when it starts to count. When the counter is not enabled and this bit is set
to 1 or 0, T8_OUT is set to the opposite state of this bit. This ensures that when the clock
is enabled, a transition occurs to the initial state set by CTR1, D1.
In Demodulation Mode, this bit is set to 1 when a rising edge is detected in the input sig-
nal. In order to reset the mode, a 1 should be written to this location.
Initial_T16 Out/Falling _Edge
In Transmit Mode, if it is 0, the output of T16 is set to 0 when it starts to count. If it is 1,
the output of T16 is set to 1 when it starts to count. This bit is effective only in Normal or
Ping-Pong Mode (CTR1, D3; D2). When the counter is not enabled and this bit is set,
T16_OUT is set to the opposite state of this bit. This ensures that when the clock is
enabled, a transition occurs to the initial state set by CTR1, D0.
In Demodulation Mode, this bit is set to 1 when a falling edge is detected in the input sig-
nal. In order to reset it, a 1 should be written to this location.
Modifying CTR1 (D1 or D0) while the counters are enabled causes unpredictable output
from T8/16_OUT.
Note:
ZGR163L
Product Specification
PS024009-0506 Pin Functions
28
CTR2 Counter/Timer 16 Control Register—CTR2(0D)02h
Table 8 lists and briefly describes the fields for this register.
T16_Enable
This field enables T16 when set to 1.
Table 8. CTR2(0D)02h: Counter/Timer16 Control Register
Field Bit Position Value Description
T16_Enable
7-------
R
W
0*
1
0
1
Counter Disabled
Counter Enabled
Stop Counter
Enable Counter
Single/Modulo-N
-6------
R/W
0
1
0
1
Transmit Mode
Modulo-N
Single Pass
Demodulation Mode
T16 Recognizes Edge
T16 Does Not Recognize
Edge
Time_Out
--5-----
R
W
0**
1
0
1
No Counter Timeout
Counter Timeout
Occurred
No Effect
Reset Flag to 0
T16 _Clock
---43---
R/W 00**
01
10
11
SCLK
SCLK/2
SCLK/4
SCLK/8
Capture_INT_Mask
-----2--
R/W 0**
1
Disable Data Capture Int.
Enable Data Capture Int.
Counter_INT_Mask
------1-
R/W 0*
1
Disable Timeout Int.
Enable Timeout Int.
P35_Out
-------0
R/W 0*
1
P35 as Port Output
T16 Output on P35
Note:
*Indicates the value upon Power-on reset.
**Indicates the value upon Power-on reset. Not reset with a Stop Mode Recovery.
ZGR163L
Product Specification
PS024009-0506 Pin Functions
29
Single/Modulo-N
In Transmit Mode, when set to 0, the counter reloads the initial value when it reaches the
terminal count. When set to 1, the counter stops when the terminal count is reached.
In Demodulation Mode, when set to 0, T16 captures and reloads on detection of all the
edges. When set to 1, T16 captures and detects on the first edge but ignores the subsequent
edges. For details, see the description of T16 Demodulation Mode on page 37.
Time_Out
This bit is set when T16 times out (terminal count reached). To reset the bit, write a 1 to
this location.
T16_Clock
This bit defines the frequency of the input signal to Counter/Timer16.
Capture_INT_Mask
This bit is set to allow an interrupt when data is captured into LO16 and HI16.
Counter_INT_Mask
Set this bit to allow an interrupt when T16 times out.
P35_Out
This bit defines whether P35 is used as a normal output pin or T16 output.
CTR3 T8/T16 Control Register—CTR3(0d)03h
Table 9 lists and briefly describes the fields for this register. This register allow the T8 and
T16 counters to be synchronized.
Table 9. CTR3(0D)03h T8/T16 Control Register
T16_Enable
7-------
R
R
WW
0*
1
0
1
Counter Disabled
Counter Enabled
Stop Counter
Enable Counter
T8 Enable
-6------
R/W 0**
1
0
1
Counter Disabled
Counter Enabled
Stop Counter
Enable Counter
ZGR163L
Product Specification
PS024009-0506 Pin Functions
30
Counter/Timer Functional Blocks
Input Circuit
The edge detector monitors the input signal on P31 or P20. Based on CTR1 D5–D4, a
pulse is generated at the Pos Edge or Neg Edge line when an edge is detected. Glitches in
the input signal that have a width less than specified (CTR1 D3, D2) are filtered out
(see Figure 13).
Figure 13. Glitch Filter Circuitry
T8 Transmit Mode
Before T8 is enabled, the output of T8 depends on CTR1, D1. If it is 0, T8_OUT is 1; if it
is 1, T8_OUT is 0. See Figure 14.
Sync Mode
--5-----
R/W 0*
1
Disable Sync Mode
Enable Sync Mode
Reserved
---43210
R/W 1
x
Always reads
11111
No Effect
Note:
*Indicates the value upon Power-on reset.
**Indicates the value upon Power-on reset. Not reset with a Stop Mode Recovery.
Table 9. CTR3(0D)03h T8/T16 Control Register
MUX Glitch
Filter
Edge
Detector
P31
P20
Pos
Edge
Neg
Edge
CTR1
D5,D4
CTR1
D6
CTR1
D3, D2
ZGR163L
Product Specification
PS024009-0506 Pin Functions
31
Figure 14. Transmit Mode Flowchart
Set Timeout Status Bit
(CTR0 D5) and Generate
Timeout_Int if Enabled
Set Timeout Status Bit
(CTR0 D5) and Generate
Timeout_Int if Enabled
T8 (8-Bit)
Transmit Mode
No T8_Enable Bit Set
CTR0, D7
Yes
CTR1, D1
Value
Reset T8_Enable Bit
01
Load TC8L
Reset T8_OUT
Load TC8H
Set T8_OUT
Enable T8
No T8_Timeout
Yes
Single Pass Single
Modulo-N
T8_OUT Value 0
Enable T8
No T8_Timeout
Yes
Pass?
Load TC8H
Set T8_OUT
Load TC8L
Reset T8_OUT
1
ZGR163L
Product Specification
PS024009-0506 Pin Functions
32
When T8 is enabled, the output T8_OUT switches to the initial value (CTR1, D1). If the
initial value (CTR1, D1) is 0, TC8L is loaded; otherwise, TC8H is loaded into the counter.
In Single-Pass Mode (CTR0, D6), T8 counts down to 0 and stops, T8_OUT toggles, the
timeout status bit (CTR0, D5) is set, and a timeout interrupt can be generated if it is
enabled (CTR0, D1). In Modulo-N Mode, upon reaching terminal count, T8_OUT is tog-
gled, but no interrupt is generated. From that point, T8 loads a new count (if the T8_OUT
level now is 0), TC8L is loaded; if it is 1, TC8H is loaded. T8 counts down to 0, toggles
T8_OUT, and sets the timeout status bit (CTR0, D5), thereby generating an interrupt if
enabled (CTR0, D1). One cycle is complete. T8 then loads from TC8H or TC8L according
to the T8_OUT level and repeats the cycle. See Figure 15.
Figure 15. 8-Bit Counter/Timer Circuits
The values in TC8H or TC8L can be modified at any time. The new values take effect
when they are loaded.
To ensure known operation do not write these registers at the time the values are to be
loaded into the counter/timer. An initial count of 1 is not allowed (a non-function oc-
curs). An initial count of 0 causes TC8 to count from 0 to FFh to FEh.
The letter h denotes hexadecimal values.
Transition from 0 to FFh is not a timeout condition.
CTR0 D1
Negative Edge
Positive Edge
Z8
®
Data Bus
IRQ4
CTR0 D2
SCLK
Z8
®
Data Bus
CTR0 D4,
Clock
T8_OUT
LO8
TC8H TC8L
Clock
Select
8-Bit
Counter T8
HI8
Caution:
Note:
ZGR163L
Product Specification
PS024009-0506 Pin Functions
33
Using the same instructions for stopping the counter/timers and setting the status bits is
not recommended.
Two successive commands are necessary. First, the counter/timers must be stopped.
Second, the status bits must be reset. These commands are required because it takes one
counter/timer clock interval for the initiated event to actually occur. See Figure 16 and
Figure 17.
Figure 16. T8_OUT in Single-Pass Mode
Figure 17. T8_OUT in Modulo-N Mode
T8 Demodulation Mode
You must program TC8L and TC8H to FFh. After T8 is enabled, when the first edge (ris-
ing, falling, or both depending on CTR1, D5; D4) is detected, it starts to count down.
When a subsequent edge (rising, falling, or both depending on CTR1, D5; D4) is detected
during counting, the current value of T8 is complemented and put into one of the capture
registers. If it is a positive edge, data is put into LO8; if it is a negative edge, data is put
into HI8. From that point, one of the edge detect status bits (CTR1, D1; D0) is set, and an
interrupt can be generated if enabled (CTR0, D2). Meanwhile, T8 is loaded with FFh and
starts counting again. If T8 reaches 0, the timeout status bit (CTR0, D5) is set, and an
interrupt can be generated if enabled (CTR0, D1). T8 then continues counting from FFh
(see Figure 19 and Figure 19).
Caution:
TC8H
Counts
Counter Enable Command;
T8_OUT Switches to Its
Initial Value (CTR1 D1)
T8_OUT Toggles;
Timeout Interrupt
Counter Enable
Command; T8_OUT
Switches to Its
Timeout
Interrupt
Timeout
Interrupt
T8_OUT
T8_OUT Toggles
TC8L TC8 TC8 TC8LTC8L
. . .
ZGR163L
Product Specification
PS024009-0506 Pin Functions
34
Figure 18. Demodulation Mode Count Capture Flowchart
T8 (8-Bit)
Count Capture
T8 Enable
(Set by User)
No
Yes
Edge Present
What Kind
of Edge
T8 HI8
No
Yes
Negative
FFh T8
Positive
T8 LO8
ZGR163L
Product Specification
PS024009-0506 Pin Functions
35
Figure 19. Demodulation Mode Flowchart
T8 (8-Bit)
Capture Mode
T8 Enable
CTR0, D7
No
Yes
FFh→ TC8
First
Edge Present
Enable TC8
T8_Enable
Bit Set
Edge Present
T8 Timeout
Set Edge Present Status
Bit and Trigger Data
Capture Int. If Enabled
Set Timeout Status
Bit and Trigger
Timeout Int. If Enabled
Continue Counting
Disable TC8
No
Yes
No
Yes
Yes
Yes
No
No
ZGR163L
Product Specification
PS024009-0506 Pin Functions
36
T16 Transmit Mode
In Normal or Ping-Pong mode, the output of T16 when not enabled, is dependent on
CTR1, D0. If it is a 0, T16_OUT is a 1; if it is a 1, T16_OUT is 0. You can force the output
of T16 to either a 0 or 1 whether it is enabled or not by programming CTR1 D3; D2 to a 10
or 11.
When T16 is enabled, TC16H * 256 + TC16L is loaded, and T16_OUT is switched to its
initial value (CTR1, D0). When T16 counts down to 0, T16_OUT is toggled (in NOR-
MAL or PING-PONG mode), an interrupt (CTR2, D1) is generated (if enabled), and a
status bit (CTR2, D5) is set. See Figure 20.
Figure 20. 16-Bit Counter/Timer Circuits
Global interrupts override this function as described in Interrupts on page 40.
If T16 is in Single-Pass mode, it is stopped at this point (see Figure 21). If it is in
Modulo-N Mode, it is loaded with TC16H * 256 + TC16L, and the counting continues
(see Figure 22).
The values in TC16H and TC16L can be modified at any time. The new values take effect
when they are loaded.
CTR2 D1
Negative Edge
Positive Edge
Z8
®
Data Bus
IRQ3
CTR2 D2
SCLK
Z8
®
Data Bus
CTR2 D4,
Clock
T16_OUT
LO16
TC16 TC16
Clock
Select
16-Bit
Counter T16
HI16
Note:
ZGR163L
Product Specification
PS024009-0506 Pin Functions
37
Do not load these registers at the time the values are to be loaded into the counter/timer
to ensure known operation. An initial count of 1 is not allowed. An initial count of 0
causes T16 to count from 0 to FFFFh to FFFEh. Transition from 0 to FFFFh is not a tim-
eout condition.
Figure 21. T16_OUT in Single-Pass Mode
Figure 22. T16_OUT in Modulo-N Mode
T16 Demodulation Mode
The user must program TC16L and TC16H to FFh. After T16 is enabled, and the first
edge (rising, falling, or both depending on CTR1 D5; D4) is detected, T16 captures HI16
and LO16, reloads, and begins counting.
If D6 of CTR2 Is 0
When a subsequent edge (rising, falling, or both depending on CTR1, D5; D4) is detected
during counting, the current count in T16 is complemented and put into HI16 and LO16.
When data is captured, one of the edge detect status bits (CTR1, D1; D0) is set, and an
interrupt is generated if enabled (CTR2, D2). T16 is loaded with FFFFh and starts again.
This T16 mode is generally used to measure space time, the length of time between bursts
of carrier signal (marks).
Caution:
TC16H*256+TC16L Counts
“Counter Enable” Command
T16_OUT Switches to Its
Initial Value (CTR1 D0)
T16_OUT Toggles,
Timeout Interrupt
TC16H*256+TC16L
TC16H*256+TC16
TC16H*256+TC16
T16_OUT Toggles,
Timeout Interrupt
T16_OUT Toggles,
Timeout Interrupt
“Counter Enable” Command,
T16_OUT Switches to Its
Initial Value (CTR1 D0)
TC16_OUT
. . .
ZGR163L
Product Specification
PS024009-0506 Pin Functions
38
If D6 of CTR2 Is 1
T16 ignores the subsequent edges in the input signal and continues counting down. A tim-
eout of T8 causes T16 to capture its current value and generate an interrupt if enabled
(CTR2, D2). In this case, T16 does not reload and continues counting. If the D6 bit of
CTR2 is toggled (by writing a 0 then a 1 to it), T16 captures and reloads on the next edge
(rising, falling, or both depending on CTR1, D5; D4), continuing to ignore subsequent
edges.
This T16 mode generally measures mark time, the length of an active carrier signal burst.
If T16 reaches 0, T16 continues counting from FFFFh. Meanwhile, a status bit (CTR2 D5)
is set, and an interrupt timeout can be generated if enabled (CTR2 D1).
Ping-Pong Mode
This operation mode is only valid in Transmit Mode. T8 and T16 must be programmed in
Single-Pass mode (CTR0, D6; CTR2, D6), and Ping-Pong mode must be programmed in
CTR1, D3; D2. The user can begin the operation by enabling either T8 or T16 (CTR0, D7
or CTR2, D7). For example, if T8 is enabled, T8_OUT is set to this initial value (CTR1,
D1). According to T8_OUT's level, TC8H or TC8L is loaded into T8. After the terminal
count is reached, T8 is disabled, and T16 is enabled. T16_OUT then switches to its initial
value (CTR1, D0), data from TC16H and TC16L is loaded, and T16 starts to count. After
T16 reaches the terminal count, it stops, T8 is enabled again, repeating the entire cycle.
Interrupts can be allowed when T8 or T16 reaches terminal control (CTR0, D1; CTR2,
D1). To stop the ping-pong operation, write 00 to bits D3 and D2 of CTR1. See Figure 23.
Enabling ping-pong operation while the counter/timers are running might cause
intermittent counter/timer function. Disable the counter/timers and reset the status flags
before instituting this operation.
Figure 23. Ping-Pong Mode Diagram
Note:
Enabl
TC8
Enable
Timeout
TC16
Ping-Pong
CTR1
Timeout
ZGR163L
Product Specification
PS024009-0506 Pin Functions
39
Initiating Ping-Pong Mode
First, make sure both counter/timers are not running. Set T8 into Single-Pass mode
(CTR0, D6), set T16 into Single-Pass mode (CTR2, D6), and set the Ping-Pong mode
(CTR1, D2; D3). These instructions can be in random order. Finally, start Ping-Pong mode
by enabling either T8 (CTR0, D7) or T16 (CTR2, D7). See Figure 24.
Figure 24. Output Circuit
The initial value of T8 or T16 must not be 1. If you stop the timer and restart the timer,
reload the initial value to avoid an unknown previous value.
T16_OUT
MUX
CTR1 D3
T8_OUT
P34
AND/OR/NOR/
NAND
MUX
MUX
MUX
P35
P36
P34_Internal
CTR1 D5, D4
P36_Internal
P35_Internal
CTR1,
CTR0 D0
CTR1 D6
CTR2 D0
ZGR163L
Product Specification
PS024009-0506 Pin Functions
40
During Ping-Pong Mode
The enable bits of T8 and T16 (CTR0, D7; CTR2, D7) are set and cleared alternately by
hardware. The timeout bits (CTR0, D5; CTR2, D5) are set every time the counter/timers
reach the terminal count.
Interrupts
The ZGR163L features six different interrupts (see Table 10). The interrupts are maskable
and prioritized (see Figure 25). The six sources are divided as follows: three sources are
claimed by Port 3 lines P33–P31, two by the counter/timers (see Table 10) and one for low
voltage detection. The Interrupt Mask Register (globally or individually) enables or dis-
ables the six interrupt requests.
The source for IRQ is determined by bit 1 of the Port 3 mode register (P3M). When in dig-
ital mode, Pin P33 is the source. When in Analog mode the output of the Stop Mode
Recovery source logic is used as the source for the interrupt. See Figure 30 on page 48
ZGR163L
Product Specification
PS024009-0506 Pin Functions
41
Figure 25. Interrupt Block Diagram
Low-
Voltage
Timer 8
Timer 16
Interrupt
Edge
IMR
IPR
Priority
Logic
IRQ
6
IRQ2 IRQ IRQ IRQ3 IRQ4 IRQ5
P31 P32
IRQ Register
D6, D7
Global
Interrupt
Enable
Interrupt
Request
Vector Select
D1 of P3M Register
P33
01
Stop Mode Recovery Source
ZGR163L
Product Specification
PS024009-0506 Pin Functions
42
When more than one interrupt is pending, priorities are resolved by a programmable prior-
ity encoder controlled by the Interrupt Priority Register. An interrupt machine cycle acti-
vates when an interrupt request is granted. As a result, all subsequent interrupts are
disabled, and the Program Counter and Status Flags are saved. The cycle then branches to
the program memory vector location reserved for that interrupt. All ZGR163L interrupts
are vectored through locations in the program memory. This memory location and the next
byte contain the 16-bit address of the interrupt service routine for that particular interrupt
request. To accommodate polled interrupt systems, interrupt inputs are masked, and the
Interrupt Request register is polled to determine which of the interrupt requests require
service.
An interrupt resulting from AN1 is mapped into IRQ2, and an interrupt from AN2 is
mapped into IRQ0. Interrupts IRQ2 and IRQ0 can be rising, falling, or both edge trig-
gered. These interrupts are programmable by the user. The software can poll to identify the
state of the pin.
Programming bits for the Interrupt Edge Select are located in the IRQ Register (R250),
bits D7 and D6. The configuration is indicated in Table 11.
Table 10. Interrupt Types, Sources, and Vectors
Name Source Vector Location Comments
IRQ0 P32 0,1 External (P32), Rising, Falling Edge Triggered
IRQ1 P33 2,3 External (P33), Falling Edge Triggered
IRQ2 P31, T
IN
4,5 External (P31), Rising, Falling Edge Triggered
IRQ3 T16 6,7 Internal
IRQ4 T8 8,9 Internal
IRQ5 LVD 10,11 Internal
Table 11. IRQ Register
IRQ Interrupt Edge
D7 D6 IRQ2 (P31) IRQ0 (P32)
00F F
01F R
10R F
11R/F R/F
Note: F = Falling Edge; R = Rising Edge
ZGR163L
Product Specification
PS024009-0506 Clock
43
Clock
The device’s on-chip oscillator has a high-gain, parallel-resonant amplifier, for connection
to a crystal, ceramic resonator, or any suitable external clock source (XTAL1 = Input,
XTAL2 = Output). The crystal must be AT cut, 1 MHz to 8 MHz maximum, with a series
resistance (RS) less than or equal to 100 Ω. The on-chip oscillator can be driven with a
suitable external clock source.
The crystal must be connected across XTAL1 and XTAL2 using the recommended capac-
itors from each pin to ground. The typical capacitor value is 10 pF for 8 MHz. Please also
check with the crystal supplier for the optimum capacitance.
Figure 26. Oscillator Configuration
The ZiLOG’s ZGR163L supports crystal, resonator, and oscillator. Most resonators have a
frequency tolerance of less than +/-0.5% which is adequate for remote control applica-
tions. The typical resonator has a very fast start up time on the order of a few hundred
microseconds.
Most crystals have a frequency tolerance of less than 50 ppm (+/-0.005%). Crystal oscilla-
tors, however, require a much longer start-up time because the large loading capacitance
slows down oscillation start-up. ZiLOG recommends using loading capacitors of no more
than 10 pF for crystal oscillators. If the stray capacitance of the PCB or the crystal is high,
the loading capacitance C1 and C2 should be further reduced to ensure stable oscillation
before TPOR. (Power-on reset Time is typically 5-6 mS. see Table 21, “AC Characteris-
tics,” on page 77)
C1
C2
XTAL
XTAL
XTAL
XTAL
Crystal
f = 8MHz;
C1, C2 = 10pF Typ *
* Preliminary value including pin parasitics
External Clock
XTAL
XTAL
Ceramic Resonator
f = 8 MHz
ZGR163L
Product Specification
PS024009-0506 Power Management
44
For Stop Mode Recovery operation, Bit 5 of the SMR register allows user to select the
STOP mode recovery delay (TPOR). If it is not selected, the MCU will execute instruction
immediately after it wakes up from STOP mode. The STOP mode recovery delay must be
selected (bit 5 of SMR = 1) if resonator or crystal is used as clock source.
For both resonator and crystal oscillation, the oscillation ground must go directly to the
ground pin of the microcontroller. It should use the shortest distant and isolate from other
connection.
Power Management
Power-On Reset
A timer circuit clocked by a dedicated on-board RC-oscillator is used for the Power-on
reset (POR) timer function. The POR time allows VDD and the oscillator circuit to stabi-
lize before instruction execution begins.
The POR timer circuit is a one-shot timer triggered by one of three conditions:
•
Power Fail to Power OK status, including Waking up from VBO Standby
•
Stop Mode Recovery (if D5 of SMR = 1)
•
WDT Timeout
The POR timer is 1 ms minimum. Bit 5 of the Stop-Mode Register determines whether the
POR timer is bypassed after Stop Mode Recovery (typical for external clock).
Halt Mode
This instruction turns off the internal CPU clock, but not the XTAL oscillation. The
counter/timers and external interrupts IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, and IRQ5 remain
active. The devices are recovered by interrupts, either externally or internally generated.
An interrupt request must be executed (enabled) to exit Halt Mode. After the interrupt ser-
vice routine, the program continues from the instruction after the Halt.
Stop Mode
This instruction turns off the internal clock and external crystal oscillation, reducing the
standby current to 10 μA or less. Stop Mode is terminated only by a reset, such as WDT
timeout, POR or SMR. This condition causes the processor to restart the application pro-
gram at address 000Ch. In order to enter Stop (or Halt) mode, first flush the instruction
pipeline to avoid suspending execution in mid-instruction. Execute an NOP instruction
(Opcode = FFh) immediately before the appropriate sleep instruction, as follows:
FF NOP ; clear the pipeline
6F STOP ; enter Stop Mode
ZGR163L
Product Specification
PS024009-0506 Power Management
45
or
FF NOP ; clear the pipeline
7F HALT ; enter Halt Mode
Port Configuration Register
The Port Configuration (PCON) register (see Figure 27) configures the comparator output
on Port 3. It is located in the expanded register file at Bank F, location 00.
PCON (0F) 00H
Figure 27. Port Configuration Register (PCON) (Write Only)
Comparator Output Port 3 (D0)
Bit 0 controls the comparator used in Port 3. A 1 in this location brings the comparator
outputs to P34 and P37, and a 0 releases the Port to its standard I/O configuration.
Port 0 Output Mode (D2)
Bit 2 controls the output mode of port 0. A 1 in this location sets the output to push-pull,
and a 0 sets the output to open-drain.
Stop Mode Recovery Register (SMR)
This register selects the clock divide value and determines the mode of Stop Mode Recov-
ery (see Figure 28). All bits are write only except bit 7, which is read only. Bit 7 is a flag
bit that is hardware set on the condition of Stop recovery and reset by a power-on cycle.
D7 D6 D5 D4 D3 D2 D1 D0
Comparator Output Port 3
0 P34, P37 Standard Output*
1 P34, P37 Comparator Output
Reserved (Must be 1)
Port 0
0: Open-Drain
1: Push-Pull*
Reserved (Must be 1)
* Default setting after reset
ZGR163L
Product Specification
PS024009-0506 Power Management
46
Bit 6 controls whether a low level or a high level at the XOR-gate input (see Figure 30 on
page 48) is required from the recovery source. Bit 5 controls the reset delay after recovery.
Bits D2, D3, and D4 of the SMR register specify the source of the Stop Mode Recovery
signal. Bits D0 determines if SCLK/TCLK are divided by 16 or not. The SMR is located
in Bank F of the Expanded Register File at address 0Bh.
SMR (0F) 0BH
Figure 28. Stop Mode Recovery Register
SCLK/TCLK Divide-by-16 Select (D0)
D0 of the SMR controls a divide-by-16 prescaler of SCLK/TCLK (see Figure 29). This
control selectively reduces device power consumption during normal processor execution
D7 D6 D5 D4 D3 D2 D1 D0
SCLK/TCLK Divide-by-16
0 OFF * *
1 ON
Reserved (Must be 0)
Stop Mode Recovery Source
000 POR Only *
001 Reserved
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
Stop Delay
0 OFF
1 ON * * * *
Stop Recovery Level * * *
0 Low *
1 High
Stop Flag
0 POR *
1 Stop Recovery * *
* Default after Power-on reset or Watch-Dog Reset
* * Default setting after Reset and Stop Mode Recovery
* * * At the XOR gate input
* * * * Default setting after reset. Must be 1 if using a crystal or resonator clock source.
ZGR163L
Product Specification
PS024009-0506 Power Management
47
(SCLK control) and/or Halt Mode (where TCLK sources interrupt logic). After Stop-
Mode Recovery, this bit is set to 0.
Figure 29. SCLK Circuit
Stop-Mode Recovery Register 2—SMR2(0F)0DH
Table 12 lists and describes the fields for this register.
Table 12. SMR2(F)0DH:Stop Mode Recovery Register 2*
Field Bit Position Value Description
Reserved
7-------
0 Reserved (Must be 0)
Recovery Level
-6------
W0
†
1
Low
High
Reserved
--5-----
0 Reserved (Must be 0)
Source
---432--
W000
†
001
010
011
100
101
110
111
A. POR Only
B. NAND of P23–P20
C. NAND of P27–P20
D. NOR of P33–P31
E. NAND of P33–P31
F. NOR of P33–P31, P00, P07
G. NAND of P33–P31, P00, P07
H. NAND of P33–P31, P22–P20
Reserved
------10
00 Reserved (Must be 0)
Notes:
* Port pins configured as outputs are ignored as an SMR recovery source.
†
Indicates the value at Power-on reset
SCL
TCLKSMR, D0
2÷
OSC
16÷
ZGR163L
Product Specification
PS024009-0506 Power Management
48
Stop Mode Recovery Source (D2, D3, and D4)
These three bits of the SMR specify the wake-up source of the Stop recovery
(see Figure 30 and Table 13).
Figure 30. Stop Mode Recovery Source
SMR2 D4 D3 D2
1 0 0
SMR2 D4 D3 D2
1 1 1
SMR D4 D3 D2
0 1 0
SMR D4 D3 D2
1 1 1
SMR D4 D3 D2
1 0 1
SMR D4 D3 D2
1 0 0
SMR D4 D3 D2
0 1 1
SMR D4 D3 D2
0 0 0
SMR D4 D3 D2
1 1 0
VCC
P31
P32
P33
P27
P20
P23
P20
P27
SMR2 D4 D3 D2
0 0 1
SMR2 D4 D3 D2
0 0 0
SMR2 D4 D3 D2
0 1 0
SMR2 D4 D3 D2
0 1 1
SMR2 D4 D3 D2
1 0 1
SMR2 D4 D3 D2
1 1 0
VCC
P20
P23
P20
P27
P31
P32
P33
P31
P32
P33
P31
P32
P33
P00
P07
P31
P32
P33
P00
P07
P31
P32
P33
P20
P21
P22
SMR D6
SMR2 D6
To RESET and WDT
Circuitry (Active
ZGR163L
Product Specification
PS024009-0506 Power Management
49
Any Port 2 bit defined as an output drives the corresponding input to the default state. This
condition allows the remaining inputs to control the AND/OR function. See Stop Mode
Recovery Register 2 (SMR2) on page 50 for other recover sources.
Stop Mode Recovery Delay Select (D5)
This bit, if Low, disables the TPOR delay after Stop Mode Recovery. The default
configuration of this bit is 1. If the “fast” wake up is selected, the Stop Mode Recovery
source must be kept active for at least 5 TpC.
This bit must be set to 1 if using a crystal or resonator clock source. The TPOR delay
allows the clock source to stabilize before executing instructions.
Stop Mode Recovery Edge Select (D6)
A 1 in this bit position indicates that a High level on any one of the recovery sources
wakes the Z8 GPTM MCU from Stop Mode. A 0 indicates Low level recovery. The default
is 0 on POR.
Cold or Warm Start (D7)
This bit is read only. It is set to 1 when the device is recovered from Stop Mode. The bit is
set to 0 when the device reset is other than Stop Mode Recovery (SMR).
Table 13. Stop Mode Recovery Source
SMR:432 Operation
D4 D3 D2 Description of Action
0 0 0 POR and/or external reset recovery
001 Reserved
0 1 0 P31 transition
0 1 1 P32 transition
1 0 0 P33 transition
1 0 1 P27 transition
1 1 0 Logical NOR of P20 through P23
1 1 1 Logical NOR of P20 through P27
Note:
Note:
ZGR163L
Product Specification
PS024009-0506 Power Management
50
Stop Mode Recovery Register 2 (SMR2)
This register determines the mode of Stop Mode Recovery for SMR2 (see Figure 31).
SMR2 (0F) DH
Figure 31. Stop Mode Recovery Register 2 ((0F) DH:D2–D4, D6 Write Only)
If SMR2 is used in conjunction with SMR, either of the specified events causes a Stop
Mode Recovery.
Port pins configured as outputs are ignored as an SMR or SMR2 recovery source. For
example, if the NAND or P23–P20 is selected as the recovery source and P20 is
configured as an output, the remaining SMR pins (P23–P21) form the NAND equation.
D7 D6 D5 D4 D3 D2 D1 D0
Reserved (Must be 0)
Reserved (Must be 0)
Stop-Mode Recovery Source 2
000 POR Only *
001 NAND P20, P21, P22, P23
010 NAND P20, P21, P22, P23, P24, P25, P26, P27
011 NOR P31, P32, P33
100 NAND P31, P32, P33
101 NOR P31, P32, P33, P00, P07
110 NAND P31, P32, P33, P00, P07
111 NAND P31, P32, P33, P20, P21, P22
Reserved (Must be 0)
Recovery Level * *
0 Low *
1 High
Reserved (Must be 0)
Note: If used in conjunction with SMR, either of the two specified events causes a Stop Mode Recovery.
* Default setting after reset
* * At the XOR gate input
Note:
ZGR163L
Product Specification
PS024009-0506 Power Management
51
Watch-Dog Timer Mode Register (WDTMR)
The Watch-Dog Timer (WDT) is a retriggerable one-shot timer that resets the Z8® if it
reaches its terminal count. The WDT must initially be enabled by executing the WDT
instruction. On subsequent executions of the WDT instruction, the WDT is refreshed. The
WDT circuit is driven by an on-board RC-oscillator. The WDT instruction affects the Zero
(Z), Sign (S), and Overflow (V) flags.
The POR clock source the internal RC-oscillator. Bits 0 and 1 of the WDT register control
a tap circuit that determines the minimum timeout period. Bit 2 determines whether the
WDT is active during HALT, and Bit 3 determines WDT activity during STOP. Bits 4
through 7 are reserved (see Figure 32). This register is accessible only during the first 60
processor cycles (120 XTAL clocks) from the execution of the first instruction after
Power-on reset, Watch-Dog Reset, or a Stop Mode Recovery (see Figure 31). After this
point, the register cannot be modified by any means (intentional or otherwise). The
WDTMR cannot be read. The register is located in Bank F of the Expanded Register File
at address location 0Fh. It is organized as illustrated in Figure 32.
WDTMR (0F) 0FH
Figure 32. Watch-Dog Timer Mode Register (Write Only)
WDT Time Select (D0, D1)
This bit selects the WDT time period. It is configured as indicated in Table 14.
D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP INT RC OSC
00 10 ms min.
01* 20 ms min.
10 40 ms min.
11 160 ms min.
WDT During Halt
0 OFF
1 ON *
WDT During Stop
0 OFF
1 ON *
Reserved (Must be 0)
* Default setting after reset
ZGR163L
Product Specification
PS024009-0506 Power Management
52
WDTMR During Halt (D2)
This bit determines whether or not the WDT is active during Halt Mode. A 1 indicates
active during Halt. The default is 1. See Figure 33.
Figure 33. Resets and WDT
Table 14. Watchdog Timer Time Select
D1 D0 Timeout of Internal RC-Oscillator
0 0 10 ms min.
0 1 20 ms min.
1 0 40 ms min.
1 1 160 ms min.
-
* CLR1 and CLR2 enable the WDT/POR and 18 Clock Reset timers respectively upon a Low-to-
+
From Stop
Mode
Recovery
Stop Delay
Select
5 Clock *CLR2 18 Clock
RESET RESE
WDT
POR 10 ms 20 ms 40 ms 160
CL
*CLR WDT/POR Counter
Internal
RC
Oscillator.
WDT
V
DD
Low
VBO
V
DD
Interna
l
RESE
T
12-ns Glitch
XTAL
ZGR163L
Product Specification
PS024009-0506 Power Management
53
WDTMR During Stop (D3)
This bit determines whether or not the WDT is active during Stop Mode. A 1 indicates
active during Stop. The default is 1.
ROM Selectable Options
There are five ROM Selectable Options to choose from based on ROM code requirements.
These options are listed in Table 15.
Voltage Brown-Out/Standby
An on-chip Voltage Comparator checks that the VDD is at the required level for correct
operation of the device. Reset is globally driven when VDD falls below VBO. A small drop
in VDD causes the XTAL1 and XTAL2 circuitry to stop the crystal or resonator clock. If
the VDD is allowed to stay above VRAM, the RAM content is preserved. When the power
level is returned to above VBO, the device performs a POR and functions normally.
Low-Voltage Detection Register—LVD(0D)0CH
Voltage detection does not work at Stop mode. It must be disabled during Stop mode in
order to reduce current.
Table 15. ROM Selectable Options
Port 00–03 Pull-Ups On/Off
Port 04–07 Pull-Ups On/Off
Port 20–27 Pull-Up Port 3 Pull-Ups On/Off
Port 3 Pull-Ups On/Off
Watch-Dog Timer at Power-on reset On/Off
Field Bit Position Description
LVD 765432--- Reserved
-----2 R 1
0*
HVD flag set
HVD flag reset
------1- R 1
0*
LVD flag set
LVD flag reset
-------0 R/W 1
0*
Enable VD
Disable VD
*
Default after POR
Note:
ZGR163L
Product Specification
PS024009-0506 Power Management
54
Do not modify register P01M while checking a low-voltage condition. Switching noise of
both ports 0 and 1 together might trigger the LVD flag.
Voltage Detection and Flags
The Voltage Detection register (LVD, register 0Ch at the expanded register bank 0Dh)
offers an option of monitoring the VCC voltage. The Voltage Detection is enabled when bit
0 of LVD register is set. When Voltage Detection is enabled, the the VCC level is moni-
tored in real time. The flags in the LVD register valid 20uS after Voltage Detection is
enabled. The HVD flag (bit 2 of the LVD register) is set only if VCC is lower than the
VHVD. When Voltage Detection is enabled, the LVD flag also triggers IRQ5. The IRQ bit
5 latches the low voltage condition until it is cleared by instructions or reset. The IRQ5
interrupt is served if it is enabled in the IMR register. Otherwise, bit 5 of IRQ register is
latched as a flag only.
If it is necessary to receive an LVD interrupt upon power-up at an operating voltage lower
than the low battery detect threshold, enable interrupts using the Enable Interrupt
instruction (EI) prior to enabling the voltage detection.
Note:
Note:
ZGR163L
Product Specification
PS024009-0506 Expanded Register File Control Registers (0D)
55
Expanded Register File Control Registers (0D)
The expanded register file control registers (0D) are depicted in Figure 34 through
Figure 38.
Figure 34. TC8 Control Register ((0D) 00H: Read/Write Except Where Noted)
CTR0 (0D) 00H
D7 D6 D5 D4 D3 D2 D1 D0
0 P34 as Port Output *
1 Timer8 Output
0 Disable T8 Timeout Interrupt**
1 Enable T8 Timeout Interrupt
0 Disable T8 Data Capture
Interrupt**
1 Enable T8 Data Capture Interrupt
00 SCLK on T8**
01 SCLK/2 on T8
10 SCLK/4 on T8
11 SCLK/8 on T8
R 0 No T8 Counter Timeout**
R 1 T8 Counter Timeout Occurred
W 0 No Effect
W 1 Reset Flag to 0
0 Modulo-N*
1 Single Pass
R 0 T8 Disabled *
R 1 T8 Enabled
W 0 Stop T8
W 1 Enable T8
* Default setting after reset.
**Default setting after Reset. Not reset with a Stop Mode recovery.
ZGR163L
Product Specification
PS024009-0506 Expanded Register File Control Registers (0D)
56
Figure 35. T8 and T16 Common Control Functions ((0D) 01H: Read/Write)
CTR1 (0D) 01H
D7 D6 D5 D4 D3 D2 D1 D0
Transmit Mode*
R/W 0 T16_OUT is 0 initially*
1 T16_OUT is 1 initially
Capture Mode
R 0 No Falling Edge Detection
R 1 Falling Edge Detection
W 0 No Effect
W 1 Reset Flag to 0
Transmit Mode*
R/W 0 T8_OUT is 0 initially*
1 T8_OUT is 1 initially
Capture Mode
R 0 No Rising Edge Detection
R 1 Rising Edge Detection
W 0 No Effect
W 1 Reset Flag to 0
Transmit Mode*
0 0 Normal Operation*
0 1 Ping-Pong Mode
1 0 T16_OUT = 0
1 1 T16_OUT = 1
Capture Mode
0 0 No Filter
0 1 4 SCLK Cycle Filter
1 0 8 SCLK Cycle Filter
1 1 Reserved
Transmit Mode/T8/T16 Logic
0 0 AND**
0 1 OR
1 0 NOR
1 1 NAND
Capture Mode
0 0 Falling Edge Detection
0 1 Rising Edge Detection
1 0 Both Edge Detection
1 1 Reserved
Transmit Mode
0 P36 as Port Output *
1 P36 as T8/T16_OUT
Capture Mode
0 P31 as Demodulator Input
1 P20 as Demodulator Input
Transmit/Capture Mode
0 Transmit Mode *
1 Capture Mode
* Default setting after reset.
**Default setting after Reset. Not reset with a Stop Mode
Recovery
ZGR163L
Product Specification
PS024009-0506 Expanded Register File Control Registers (0D)
57
Take care in differentiating the Transmit Mode from Capture Mode. Depending on which
of these two modes is operating, the CTR1 bit has different functions.
Changing from one mode to another cannot be performed without disabling the counter/
timers.
CTR2 (0D) 02H
Figure 36. T16 Control Register ((0D) 02H: Read/Write Except Where Noted)
D7 D6 D5 D4 D3 D2 D1 D0
0 P35 is Port Output *
1 P35 is TC16 Output
0 Disable T16 Timeout Interrupt*
1 Enable T16 Timeout Interrupt
0 Disable T16 Data Capture
Interrupt**
1 Enable T16 Data Capture Interrupt
0 0 SCLK on T16**
0 1 SCLK/2 on T16
1 0 SCLK/4 on T16
1 1 SCLK/8 on T16
R 0 No T16 Timeout**
R 1 T16 Timeout Occurs
W 0 No Effect
W 1 Reset Flag to 0
Transmit Mode
0 Modulo-N for T16*
1 Single Pass for T16
Capture Mode
0 T16 Recognizes Edge
1 T16 Does Not Recognize Edge
R 0 T16 Disabled*
R 1 T16 Enabled
W 0 Stop T16
W 1 Enable T16
* Default setting after reset.
**Default setting after Reset. Not reset with a
Stop Mode Recovery.
Note:
ZGR163L
Product Specification
PS024009-0506 Expanded Register File Control Registers (0D)
58
CTR3 (0D) 03H
Figure 37. T8/T16 control Register (0D) 03H: Read/Write (Except Where Noted)
If Sync Mode is enabled, the first pulse of T8 (carrier) is always synchronized with T16
(demodulated signal). It can always provide a full carrier pulse.
D7 D6 D5 D4 D3 D2 D1 D0
Reserved
No effect when written
Always reads
11111
Sync Mode
0* Disable Sync Mode**
1 Enable Sync Mode
T
8
Enable
R 0* T
8
Disabled
R 1 T8 Enabled
W0 Stop T8
W1 Enable T8
T
16
Enable
R 0* T
16
Disabled
R 1 T16 Enabled
W 0 Stop T16
W 1 Enable T16
* Default setting after reset.
**Default setting after Reset. Not reset with a
Stop Mode Recovery.
Note:
ZGR163L
Product Specification
PS024009-0506 Expanded Register File Control Registers (0D)
59
LVD (0D) 0CH
Figure 38. Voltage Detection Register
D7 D6 D5 D4 D3 D2 D1 D0
Voltage Detection
0: Disable *
1: Enable
LVD Flag (Read only)
0: LVD flag reset *
1: LVD flag set
HVD Flag (Read only)
0: HVD flag reset *
1: HVD flag set
Reserved (Must be 0)
* Default
ZGR163L
Product Specification
PS024009-0506 Expanded Register File Control Registers (0F)
60
Expanded Register File Control Registers (0F)
The expanded register file control registers (0F) are depicted in Figure 39 through
Figure 52.
PCON (0F) 00H
Figure 39. Port Configuration Register (PCON) ((0F)00H: Write Only
D7 D6 D5 D4 D3 D2 D1 D0
Comparator Output Port 3
0 P34, P37 Standard Output *
1 P34, P37 Comparator Output
Reserved. (Must be 1)
Port 0
0: Open-Drain
1: Push-Pull *
Reserved (Must be 1)
* Default setting after reset
ZGR163L
Product Specification
PS024009-0506 Expanded Register File Control Registers (0F)
61
SMR (0F) 0BH
Figure 40. Stop Mode Recovery Register ((0F) 0BH: D6–D0=Write Only, D7=Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
SCLK/TCLK Divide-by-16
0 OFF *
1 ON
Reserved (Must be 0)
Stop Mode Recovery Source
000 POR Only * *
001 Reserved
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0–3
111 P2 NOR 0–7
Stop Delay
0 OFF
1 ON * * * *
Stop Recovery Level * * *
0 Low * *
1 High
Stop Flag
0 POR * * * * *
1 Stop Recovery * *
* Default setting after Reset
* * Set after STOP Mode Recovery
* * * At the XOR gate input
* * * * Default setting after reset. Must be 1 if using a crystal or resonator clock source.
Not reset with a Stop Mode recovery.
* * * * * Default setting after Power-on reset.
ZGR163L
Product Specification
PS024009-0506 Expanded Register File Control Registers (0F)
62
SMR2 (0F) 0DH
Figure 41. Stop Mode Recovery Register 2 ((0F) 0DH: D2–D4, D6 Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Reserved (Must be 0)
Reserved (Must be 0)
Stop-Mode Recovery Source 2
000 POR Only *
001 NAND P20, P21, P22, P23
010 NAND P20, P21, P22, P23, P24, P25, P26, P27
011 NOR P31, P32, P33
100 NAND P31, P32, P33
101 NOR P31, P32, P33, P00, P07
110 NAND P31, P32, P33, P00, P07
111 NAND P31, P32, P33, P20, P21, P22
Reserved (Must be 0)
Recovery Level * *
0 Low
1 High
Reserved (Must be 0)
Note: If used in conjunction with SMR, either of the two specified events causes a Stop Mode Recovery.
* Default setting after reset. Not reset with a Stop Mode Recovery.
* * At the XOR gate input
ZGR163L
Product Specification
PS024009-0506 Standard Control Registers
63
WDTMR (0F) 0FH
Figure 42. Watch-Dog Timer Register ((0F) 0FH: Write Only)
Standard Control Registers
R246 P2M (F6H)
Figure 43. Port 2 Mode Register (F6H: Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP INT RC OSC
00—10 ms min.
01—20 ms min.*
10—40 ms min.
11—80 ms min.
WDT During Halt
0 OFF
1 ON *
WDT During Stop
0 OFF
1 ON *
Reserved (Must be 0)
* Default setting after reset. Not reset with a Stop Mode Recovery.
D7 D6 D5 D4 D3 D2 D1 D0
P27–P20 I/O Definition
0 Defines bit as OUTPUT
1 Defines bit as INPUT *
* Default setting after reset. Not reset with a Stop Mode Recovery.
ZGR163L
Product Specification
PS024009-0506 Standard Control Registers
64
R247 P3M (F7H)
Figure 44. Port 3 Mode Register (F7H: Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
0: Port 2 Open Drain *
1: Port 2 Push-Pull
0= P31, P32 Digital Mode*
1= P31, P32 Analog Mode
Reserved (Must be 0)
* Default setting after reset. Not reset with a Stop Mode Recovery.
ZGR163L
Product Specification
PS024009-0506 Standard Control Registers
65
R248 P01M (F8H)
Figure 45. Port 0 Register (F8H: Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
P00–P03 Mode
0: Output
1: Input *
Reserved (Must be 0)
Reserved (Must be 1)
Reserved (Must be 0)
P07–P04 Mode
0: Output
1: Input *
Reserved (Must be 0)
* Default setting after reset; only P00, P01 and P07 are available on 20-pin
configurations.
ZGR163L
Product Specification
PS024009-0506 Standard Control Registers
66
R249 IPR (F9H)
Figure 46. Interrupt Priority Register (F9H: Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Interrupt Group Priority
000 Reserved
001 C > A > B
010 A > B >C
011 A > C > B
100 B > C > A
101 C > B > A
110 B > A > C
111 Reserved
IRQ1, IRQ4, Priority
(Group C)
0: IRQ1 > IRQ4
1: IRQ4 > IRQ1
IRQ0, IRQ2, Priority
(Group B)
0: IRQ2 > IRQ0
1: IRQ0 > IRQ2
IRQ3, IRQ5, Priority
(Group A)
0: IRQ5 > IRQ3
1: IRQ3 > IRQ5
Reserved; must be 0
ZGR163L
Product Specification
PS024009-0506 Standard Control Registers
67
R250 IRQ (FAH)
Figure 47. Interrupt Request Register (FAH: Read/Write)
R251 IMR (FBH)
Figure 48. Interrupt Mask Register (FBH: Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
IRQ0 = P32 Input
IRQ1 = P33 Input
IRQ2 = P31 Input
IRQ3 = T16
IRQ4 = T8
IRQ5 = LVD
Inter Edge
P31
↓
P32
↓
= 00
P31
↓
P32
↑
= 01
P31
↑
P32
↓
= 10
P31
↑↓
P32
↑↓
= 11
D7 D6 D5 D4 D3 D2 D1 D0
1 Enables IRQ5–IRQ0
(D0 = IRQ0)
Reserved (Must be 0)
0 Master Interrupt Disable *
1 Master Interrupt Enable * *
* Default setting after reset
* * Only by using EI, DI instruction; DI is required before changing the IMR register
ZGR163L
Product Specification
PS024009-0506 Standard Control Registers
68
R252 Flags (FCH)
Figure 49. Flag Register (FCH: Read/Write)
R253 RP (FDH)
Figure 50. Register Pointer (FDH: Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
User Flag F1
User Flag F2
Half Carry Flag
Decimal Adjust Flag
Overflow Flag
Sign Tag
Zero Flag
Carry Flag
D7 D6 D5 D4 D3 D2 D1 D0
Expanded Register Bank Pointer
Working Register Pointer
Default setting after reset = 0000 0000
ZGR163L
Product Specification
PS024009-0506 Standard Control Registers
69
R254 SPH (FEH)
Figure 51. Stack Pointer High (FEH: Read/Write)
R255 SPL (FFH)
Figure 52. Stack Pointer Low (FFH: Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
General-Purpose Register
D7 D6 D5 D4 D3 D2 D1 D0
Stack Pointer Low
Byte (SP7–SP0)
ZGR163L
Product Specification
PS024009-0506 Absolute Maximum Ratings
70
Electrical Characteristics
Absolute Maximum Ratings
Stresses greater than those listed in Table 16 might cause permanent damage to the device.
This rating is a stress rating only. Functional operation of the device at any condition
above those indicated in the operational sections of these specifications is not implied.
Exposure to absolute maximum rating conditions for an extended period might affect
device reliability.
Standard Test Conditions
The characteristics listed in this product specification apply for standard test conditions as
noted. All voltages are referenced to GND. Positive current flows into the referenced pin
(see Figure 53).
Table 16. Absolute Maximum Ratings
Parameter Minimum Maximum Units Notes
Ambient temperature under bias –40 +125 C
Storage temperature –65 +150 C
Voltage on any pin with respect to V
SS
–0.3 +4.0 V 1
Voltage on V
DD
pin with respect to V
SS
–0.3 +3.6 V
Maximum current on input and/or inactive output pin –5 +5 mA
Maximum output current from active output pin -25 +25 mA
Maximum current into V
DD
or out of V
SS
75 mA
Note:
1. This voltage applies to all pins except the following: VDD.
ZGR163L
Product Specification
PS024009-0506 DC Characteristics
71
Figure 53. Test Load Diagram
Capacitance
Table 17 lists the capacitances.
DC Characteristics
Table 17. Capacitance
Parameter Maximum
Input capacitance 12 pF
Output capacitance 12 pF
I/O capacitance 12 pF
Note: TA = 25 °C, VCC = GND = 0 V, f = 1.0 MHz, unmeasured pins
returned to GND
Table 18. ZGR163LS DC Characteristics
TA= 0 °C to +70 °C
Units Conditions NotesSymbol Parameter VCC Min Typ(7) Max
V
CC
Supply Voltage 2.0 V 3.6 V See Note 5 5
V
CH
Clock Input High
Voltage
2.0-3.6V 0.8 V
CC
V
CC
+0.3 V Driven by External
Clock Generator
V
CL
Clock Input Low
Voltage
2.0-3.6V V
SS
–0.3 0.5 V Driven by External
Clock Generator
V
IH
Input High Voltage 2.0-3.6V 0.7 V
CC
V
CC
+0.3 V
V
IL
Input Low Voltage 2.0-3.6V V
SS
–0.3 0.2 V
CC
V
V
OH1
Output High Voltage 2.0-3.6V V
CC
–0.4 V I
OH
= –0.5mA
From Output
Under Test
150 pF
ZGR163L
Product Specification
PS024009-0506 DC Characteristics
72
V
OH2
Output High Voltage
(P36, P37, P00, P01)
2.0-3.6 V V
CC
–0.8 V I
OH
= –7 mA
V
OL1
Output Low Voltage 2.0-3.6 V 0.4 V I
OL
= 4.0 mA
V
OL2
Output Low Voltage
(P00, P01, P36, P37)
2.0-3.6 V 0.8 V I
OL
= 10 mA
V
OFFSET
Comparator Input
Offset Voltage
2.0-3.6 V 25 mV
V
REF
Comparator
Reference
Voltage
2.0-3.6 V 0 V
DD
-1.75
V
I
IL
Input Leakage 2.0-3.6 V –1 1
μ
AV
IN
= 0 V, V
CC
Pull-ups disabled
R
PU
Pull-up Resistance 2.0 V 225 675 K
Ω
VIN = 0 V; Pullups selected by
mask option
3.6 V 75 275 K
Ω
I
OL
Output Leakage 2.0-3.6 V –1 1
μ
AV
IN
= 0V, V
CC
I
CC
Supply Current 2.0 V
3.6 V
1.2
2.1
3
5
mA
mA
at 8.0 MHz
at 8.0 MHz
1, 2
1, 2
I
CC1
Standby Current
(HALT Mode)
2.0 V
3.6 V
0.5
0.8
1.6
2.0
mA
mA
V
IN
= 0V, Clock
at 8.0 MHz
Same as above
1, 2,6
I
CC2
Standby Current
(STOP Mode)
2.0 V
3.6 V
2.0 V
3.6 V
1.2
1.4
3.5
6.5
8
10
20
30
μ
A
μ
A
μ
A
μ
A
V
IN
= 0 V, V
CC
WDT is not
Running
V
IN
= 0 V, V
CC
WDT is Running
3
3
I
LV
Standby Current
(Low Voltage)
0.8 6
μ
A Measured at 1.3 V 4
V
BO
V
CC
Low Voltage
Protection
1.8 2.0 V 8 MHz maximum
Ext. CLK Freq.
V
LVD
Vcc Low Voltage
Detection
2.4 V
V
HVD
Vcc High Voltage
Detection
2.7 V
Notes:
1. All outputs unloaded, inputs at rail.
2. CL1 = CL2 = 100 pF.
3. Oscillator stopped.
4. Oscillator stops when VCC falls below VBO limit.
5. It is strongly recommended to add a filter capacitor (min., 0.1 μF), physically close to VCC and VSS pins if operating voltage
fluctuations are anticipated, such as those resulting from driving an IR LED.
6. Comparator and Timers are on. Interrupt disabled.
7. Typical values shown are at 25°C
Table 18. ZGR163LS DC Characteristics (Continued)
TA= 0 °C to +70 °C
Units Conditions NotesSymbol Parameter VCC Min Typ(7) Max
ZGR163L
Product Specification
PS024009-0506 DC Characteristics
73
Table 19. ZGR163LE DC Characteristics
TA= –40 °C to +105 °C
Units Conditions NotesSymbol Parameter VCC Min Typ(7) Max
V
CC
Supply Voltage 2.0 V 3.6 V See Note 5 5
V
CH
Clock Input High
Voltage
2.0-3.6 V 0.8 V
CC
V
CC
+0.3 V Driven by External
Clock Generator
V
CL
Clock Input Low
Voltage
2.0-3.6 V V
SS
–0.3 0.5 V Driven by External
Clock Generator
V
IH
Input High Voltage 2.0-3.6 V 0.7 V
CC
V
CC
+0.3 V
V
IL
Input Low Voltage 2.0-3.6 V V
SS
–0.3 0.2 V
CC
V
V
OH1
Output High Voltage 2.0-3.6 V V
CC
–0.4 V I
OH
= –0.5 mA
V
OH2
Output High Voltage
(P36, P37, P00, P01)
2.0-3.6 V V
CC
–0.8 V I
OH
= –7 mA
V
OL1
Output Low Voltage 2.0-3.6 V 0.4 V I
OL
= 4.0 mA
V
OL2
Output Low Voltage
(P00, P01, P36, P37)
2.0-3.6 V 0.8 V I
OL
= 8.0 mA
V
OFFSET
Comparator Input
Offset Voltage
2.0-3.6 V 25 mV
V
REF
Comparator
Reference
Voltage
2.0-3.6V 0 V
DD
-1.75 V
I
IL
Input Leakage 2.0-3.6 V –1 1
μ
AV
IN
= 0 V, V
CC
Pull-ups disabled
R
PU
Pull-up Resistance 2.0 V 200 700 K
Ω
VIN = 0 V; Pullups selected by
mask option
3.6 V 50 300 K
Ω
I
OL
Output Leakage 2.0-3.6 V –1 1
μ
AV
IN
= 0V, V
CC
I
CC
Supply Current 2.0 V
3.6 V
1.2
2.1
3
5
mA
mA
at 8.0 MHz
at 8.0 MHz
1, 2
1, 2
I
CC1
Standby Current
(HALT Mode)
2.0 V
3.6 V
0.5
0.8
1.6
2.0
mA
mA
V
IN
= 0 V, Clock
at 8.0 MHz
Same as above
1, 2,6
I
CC2
Standby Current
(STOP Mode)
2.0 V
3.6 V
2.0 V
3.6 V
1.2
1.4
3.5
6.5
12
15
30
40
μ
A
μ
A
μ
A
μ
A
V
IN
= 0 V, V
CC
WDT is not
Running
V
IN
= 0 V, V
CC
WDT is Running
3
3
I
LV
Standby Current
(Low Voltage)
0.8 6
μ
A Measured at 1.3 V 4
ZGR163L
Product Specification
PS024009-0506 DC Characteristics
74
V
BO
V
CC
Low Voltage
Protection
1.8 2.15 V 8 MHz maximum
Ext. CLK Freq.
V
LVD
Vcc Low Voltage
Detection
2.4 V
V
HVD
Vcc High Voltage
Detection
2.7 V
Notes:
1. All outputs unloaded, inputs at rail.
2. CL1 = CL2 = 100 pF.
3. Oscillator stopped.
4. Oscillator stops when VCC falls below VBO limit.
5. It is strongly recommended to add a filter capacitor (min., 0.1 μF), physically close to VCC and VSS pins if operating voltage
fluctuations are anticipated, such as those resulting from driving an IR LED.
6. Comparator and Timers are on. Interrupt disabled.
7. Typical values shown are at 25 °C
Table 20. ZGR163LA DC Characteristics
TA= –40 °C to +125 °C
Units Conditions NotesSymbol Parameter VCC Min Typ(7) Max
V
CC
Supply Voltage 2.0 V 3.6 V See Note 5 5
V
CH
Clock Input High
Voltage
2.0-3.6 V 0.8 V
CC
V
CC
+0.3 V Driven by External
Clock Generator
V
CL
Clock Input Low
Voltage
2.0-3.6 V V
SS
–0.3 0.5 V Driven by External
Clock Generator
V
IH
Input High Voltage 2.0-3.6 V 0.7 V
CC
V
CC
+0.3 V
V
IL
Input Low Voltage 2.0-3.6 V V
SS
–0.3 0.2 V
CC
V
V
OH1
Output High Voltage 2.0-3.6 V V
CC
–0.4 V I
OH
= –0.5 mA
V
OH2
Output High Voltage
(P36, P37, P00, P01)
2.0-3.6 V V
CC
–0.8 V I
OH
= –7 mA
V
OL1
Output Low Voltage 2.0-3.6 V 0.4 V I
OL
= 4. 0mA
V
OL2
Output Low Voltage
(P00, P01, P36, P37)
2.0-3.6 V 0.8 V I
OL
= 8.0 mA
V
OFFSET
Comparator Input
Offset Voltage
2.0-3.6 V 25 mV
Table 19. ZGR163LE DC Characteristics (Continued)
TA= –40 °C to +105 °C
Units Conditions NotesSymbol Parameter VCC Min Typ(7) Max
ZGR163L
Product Specification
PS024009-0506 DC Characteristics
75
V
REF
Comparator
Reference
Voltage
2.0-3.6 V 0 V
DD
-1.75 V
I
IL
Input Leakage 2.0-3.6 V –1 1
μ
AV
IN
= 0 V, V
CC
Pull-ups disabled
R
PU
Pull-up Resistance 2.0 V 200 700 K
Ω
VIN = 0 V; Pullups selected by
mask option
3.6 V 50 300 K
Ω
I
OL
Output Leakage 2.0-3.6 V –1 1
μ
AV
IN
= 0 V, V
CC
I
CC
Supply Current 2.0 V
3.6 V
1.2
2.1
3
5
mA
mA
at 8.0 MHz
at 8.0 MHz
1, 2
1, 2
I
CC1
Standby Current
(HALT Mode)
2.0 V
3.6 V
0.5
0.8
1.6
2.0
mA
mA
V
IN
= 0V, Clock
at 8.0 MHz
Same as above
1, 2,6
I
CC2
Standby Current
(STOP Mode)
2.0 V
3.6 V
2.0 V
3.6 V
1.2
1.4
3.5
6.5
15
20
30
40
μ
A
μ
A
μ
A
μ
A
V
IN
= 0 V, V
CC
WDT is not
Running
V
IN
= 0 V, V
CC
WDT is Running
3
3
I
LV
Standby Current
(Low Voltage)
0.8 6
μ
A Measured at 1.3 V 4
V
BO
V
CC
Low Voltage
Protection
1.8 2.15 V 8 MHz maximum
Ext. CLK Freq.
V
LVD
Vcc Low Voltage
Detection
2.4 V
V
HVD
Vcc High Voltage
Detection
2.7 V
Notes:
1. All outputs unloaded, inputs at rail.
2. CL1 = CL2 = 100 pF.
3. Oscillator stopped.
4. Oscillator stops when VCC falls below VBO limit.
5. It is strongly recommended to add a filter capacitor (min., 0.1 μF), physically close to VCC and VSS pins if operating voltage
fluctuations are anticipated, such as those resulting from driving an IR LED.
6. Comparator and Timers are on. Interrupt disabled.
7. Typical values shown are at 25 °C
Table 20. ZGR163LA DC Characteristics (Continued)
TA= –40 °C to +125 °C
Units Conditions NotesSymbol Parameter VCC Min Typ(7) Max
ZGR163L
Product Specification
PS024009-0506 AC Characteristics
77
Table 21. AC Characteristics
TA= 0 °C to +70 °C (S)
–40 °C to +105 °C (E)
–40 °C to +125 °C (A)
8.0 MHz
Watch-Dog
Timer Mode
Register
(D1, D0)No Symbol Parameter VCC Minimum Maximum Units Notes
1 TpC Input Clock Period 2.0–3.6 121 DC ns 1
2 TrC,TfC Clock Input Rise
and Fall Times
2.0–3.6 25 ns 1
3 TwC Input Clock Width 2.0–3.6 37 ns 1
4 TwTinL Timer Input
Low Width
2.0
3.6
100
70
ns 1
5 TwTinH Timer Input High
Width
2.0–3.6 3TpC 1
6 TpTin Timer Input Period 2.0–3.6 8TpC 1
7 TrTin,TfTin Timer Input Rise
and Fall Timers
2.0–3.6 100 ns 1
8 TwIL Interrupt Request
Low Time
2.0
3.6
100
70
ns 1, 2
9 TwIH Interrupt Request
Input High Time
2.0–3.6 5TpC 1, 2
10 Twsm Stop-Mode
Recovery Width
Spec
2.0–3.6 12
5TpC
ns 3
4
11 Tost Oscillator
Start-Up Time
2.0–3.6 5TpC 4
12 Twdt Watch-Dog Timer
Delay Time
2.0–3.6
2.0–3.6
2.0–3.6
2.0–3.6
5
10
20
80
ms
ms
ms
ms
0, 0
0, 1
1, 0
1, 1
13 T
POR
Power-on reset 2.0–3.6 2.5 10 ms
Notes:
1. Timing Reference uses 0.9 V
CC
for a logic 1 and 0.1 V
CC
for a logic 0.
2. Interrupt request through Port 3 (P33–P31).
3. SMR – D5 = 1.
4. SMR – D5 = 0.
ZGR163L
Product Specification
PS024009-0506 AC Characteristics
79
Figure 57. 20-Pin SSOP Package Diagram
ZGR163L
Product Specification
PS024009-0506 AC Characteristics
80
Figure 58. 28-Pin SOIC Package Diagram
ZGR163L
Product Specification
PS024009-0506 AC Characteristics
81
Figure 59. 28-Pin DIP Package Diagram
ZGR163L
Product Specification
PS024009-0506 AC Characteristics
82
Figure 60. 28-Pin SSOP Package Diagram
Please check with ZiLOG® on the actual bonding diagram and coordinate for chip-on-board
assembly.
SYMBOL
A
A1
B
C
A2
e
MILLIMETER INCH
MIN MAX MIN MAX
1.73
0.05
1.68
0.25
5.20
0.65 TYP
0.09
10.07
7.65
0.63
1.86
0.0256 TYP
0.13
10.20
1.73
7.80
5.30
1.99
0.21
1.78
0.75
0.068
0.002
0.066
0.010
0.205
0.004
0.397
0.301
0.025
0.073
0.005
0.068
0.209
0.006
0.402
0.307
0.030
0.078
0.008
0.070
0.015
0.212
0.008
0.407
0.311
0.037
0.38
0.20
10.33
5.38
7.90
0.95
NOM NOM
D
E
H
L
CONTROLLING DIMENSIONS: MM
LEADS ARE COPLANAR WITHIN .004 INCHES.
H
C
DETAIL A
E
D
28 15
114
SEATING PLANE
A2
e
A
Q1
A1
B
L
0 - 8
DETAIL 'A'
Note:
ZGR163L
Product Specification
PS024009-0506 AC Characteristics
83
Ordering Information
16 KB Standard Temperature: 0°C to +70°C
Part Number Description Part Number Description
ZGR163LSH2816G 28-pin SSOP 16 K ROM ZGR163LSH2016G 20-pin SSOP 16 K ROM
ZGR163LSP2816G 28-pin PDIP 16 K ROM ZGR163LSP2016G 20-pin PDIP 16 K ROM
ZGR163LSS2816G 28-pin SOIC 16 K ROM ZGR163LSS2016G 20-pin SOIC 16 K ROM
16 KB Extended Temperature: –40°C to +105°C
Part Number Description Part Number Description
ZGR163LEH2816G 28-pin SSOP 16 K ROM ZGR163LEH2016G 20-pin SSOP 16 K ROM
ZGR163LEP2816G 28-pin PDIP 16 K ROM ZGR163LEP2016G 20-pin PDIP 16 K ROM
ZGR163LES2816G 28-pin SOIC 16 K ROM ZGR163LES2016G 20-pin SOIC 16 K ROM
16 KB Automotive Temperature: –40°C to +125°C
Part Number Description Part Number Description
ZGR163LAH2816G 28-pin SSOP 16 K ROM ZGR163LAH2016G 20-pin SSOP 16 K ROM
ZGR163LAP2816G 28-pin PDIP 16 K ROM ZGR163LAP2016G 20-pin PDIP 16 K ROM
ZGR163LAS2816G 28-pin SOIC 16 K ROM ZGR163LAS2016G 20-pin SOIC 16 K ROM
ZGR163L
Product Specification
PS024009-0506 AC Characteristics
84
8 KB Standard Temperature: 0°C to +70°C
Part Number Description Part Number Description
ZGR163LSH2808G 28-pin SSOP 8 K ROM ZGR163LSH2008G 20-pin SSOP 8 K ROM
ZGR163LSP2808G 28-pin PDIP 8 K ROM ZGR163LSP2008G 20-pin PDIP 8 K ROM
ZGR163LSS2808G 28-pin SOIC 8 K ROM ZGR163LSS2008G 20-pin SOIC 8 K ROM
8 KB Extended Temperature: –40°C to +105°C
Part Number Description Part Number Description
ZGR163LEH2808G 28-pin SSOP 8 K ROM ZGR163LEH2008G 20-pin SSOP 8 K ROM
ZGR163LEP2808G 28-pin PDIP 8 K ROM ZGR163LEP2008G 20-pin PDIP 8 K ROM
ZGR163LES2808G 28-pin SOIC 8 K ROM ZGR163LES2008G 20-pin SOIC 8 K ROM
8 KB Automotive Temperature: –40°C to +125°C
Part Number Description Part Number Description
ZGR163LAH2808G 28-pin SSOP 8 K ROM ZGR163LAH2008G 20-pin SSOP 8 K ROM
ZGR163LAP2808G 28-pin PDIP 8 K ROM ZGR163LAP2008G 20-pin PDIP 8 K ROM
ZGR163LAS2808G 28-pin SOIC 8 K ROM ZGR163LAS2008G 20-pin SOIC 8 K ROM
ZGR163L
Product Specification
PS024009-0506 AC Characteristics
85
4 KB Standard Temperature: 0°C to +70°C
Part Number Description Part Number Description
ZGR163LSH2804G 28-pin SSOP 4 K ROM ZGR163LSH2004G 20-pin SSOP 4 K ROM
ZGR163LSP2804G 28-pin PDIP 4 K ROM ZGR163LSP2004G 20-pin PDIP 4 K ROM
ZGR163LSS2804G 28-pin SOIC 4 K ROM ZGR163LSS2004G 20-pin SOIC 4 K ROM
4 KB Extended Temperature: –40°C to +105°C
Part Number Description Part Number Description
ZGR163LEH2804G 28-pin SSOP 4 K ROM ZGR163LEH2004G 20-pin SSOP 4 K ROM
ZGR163LEP2804G 28-pin PDIP 4 K ROM ZGR163LEP2004G 20-pin PDIP 4 K ROM
ZGR163LES2804G 28-pin SOIC 4 K ROM ZGR163LES2004G 20-pin SOIC 4 K ROM
4 KB Automotive Temperature: –40°C to +125°C
Part Number Description Part Number Description
ZGR163LAH2804G 28-pin SSOP 4 K ROM ZGR163LAH2004G 20-pin SSOP 4 K ROM
ZGR163LAP2804G 28-pin PDIP 4 K ROM ZGR163LAP2004G 20-pin PDIP 4 K ROM
ZGR163LAS2804G 28-pin SOIC 4 K ROM ZGR163LAS2004G 20-pin SOIC 4 K ROM
ZGR163L
Product Specification
PS024009-0506 AC Characteristics
86
2 KB Standard Temperature: 0°C to +70°C
Part Number Description Part Number Description
ZGR163LSH2802G 28-pin SSOP 2 K ROM ZGR163LSH2002G 20-pin SSOP 2 K ROM
ZGR163LSP2802G 28-pin PDIP 2 K ROM ZGR163LSP2002G 20-pin PDIP 2 K ROM
ZGR163LSS2802G 28-pin SOIC 2 K ROM ZGR163LSS2002G 20-pin SOIC 2 K ROM
2 KB Extended Temperature: –40°C to +105°C
Part Number Description Part Number Description
ZGR163LEH2802G 28-pin SSOP 2 K ROM ZGR163LEH2002G 20-pin SSOP 2 K ROM
ZGR163LEP2802G 28-pin PDIP 2 K ROM ZGR163LEP2002G 20-pin PDIP 2 K ROM
ZGR163LES2802G 28-pin SOIC 2 K ROM ZGR163LES2002G 20-pin SOIC 2 K ROM
2 KB Automotive Temperature: –40°C to +125°C
Part Number Description Part Number Description
ZGR163LAH2802G 28-pin SSOP 2 K ROM ZGR163LAH2002G 20-pin SSOP 2 K ROM
ZGR163LAP2802G 28-pin PDIP 2 K ROM ZGR163LAP2002G 20-pin PDIP 2 K ROM
ZGR163LAS2802G 28-pin SOIC 2 K ROM ZGR163LAS2002G 20-pin SOIC 2 K ROM
ZGR163L
Product Specification
PS024009-0506 AC Characteristics
87
1 KB Standard Temperature: 0°C to +70°C
Part Number Description Part Number Description
ZGR163LSH2801G 28-pin SSOP 1 K ROM ZGR163LSH2001G 20-pin SSOP 1 K ROM
ZGR163LSP2801G 28-pin PDIP 1K ROM ZGR163LSP2001G 20-pin PDIP 1 K ROM
ZGR163LSS2801G 28-pin SOIC 1K ROM ZGR163LSS2001G 20-pin SOIC 1 K ROM
1 KB Extended Temperature: –40°C to +105°C
Part Number Description Part Number Description
ZGR163LEH2801G 28-pin SSOP 1 K ROM ZGR163LEH2001G 20-pin SSOP 1 K ROM
ZGR163LEP2801G 28-pin PDIP 1 K ROM ZGR163LEP2001G 20-pin PDIP 1 K ROM
ZGR163LES2801G 28-pin SOIC 1 K ROM ZGR163LES2001G 20-pin SOIC 1 K ROM
1 KB Automotive Temperature: –40°C to +125°C
Part Number Description Part Number Description
ZGR163LAH2801G 28-pin SSOP 1 K ROM ZGR163LAH2001G 20-pin SSOP 1 K ROM
ZGR163LAP2801G 28-pin PDIP 1 K ROM ZGR163LAP2001G 20-pin PDIP 1 K ROM
ZGR163LAS2801G 28-pin SOIC 1 K ROM ZGR163LAS2001G 20-pin SOIC 1 K ROM
Additional Components
Part Number Description Part Number Description
Visit the ZiLOG website (
www.zilog.com)
for ordering information on additional components
and development tools for ZGR163L.
ZGR163L
Product Specification
PS024009-0506 AC Characteristics
88
For fast results, contact your local ZiLOG sales office for assistance in ordering the part
desired.
Example
ZG R 163 L S P 28 16 G
Molding Compound
Memory Size
Number of Pins
Package Type:
E = CDIP
P = PDIP
H = SSOP
S = SOIC
Temperature:
S = Standard
E = Extended
A = Automotive
Voltage:
L = 2.0 V t0 3.6 V
Family Designation
ROM
ZiLOG General-Purpose
Family
ZGR163L
Product Specification
PS024009-0506 AC Characteristics
89
Document Number Description
The Document Control Number that appears in the footer of each page of this document
contains unique identifying attributes, as indicated in the following table:
PS Product Specification
0240 Unique Document Number
09 Revision Number
0506 Month and Year Published
ZGR163L
Product Specification
PS024009-0506 AC Characteristics
90
Customer Support
If you experience any problems while operating this product, please check the ZiLOG Knowledge Base:
http://kb.zilog.com/kb/oKBmain.asp
If you cannot find an answer or have further questions, please see the ZiLOG Technical Support web page:
http://support.zilog.com
ZGR163L
Product Specification
PS024009-0506 Index
91
Index
Numerics
16-bit counter/timer circuits 36
20-pin DIP package diagram 79
20-pin SSOP package diagram 80
28-pin DIP package diagram 82
28-pin SOIC package diagram 81
28-pin SSOP package diagram 83
8-bit counter/timer circuits 32
A
absolute maximum ratings 71
AC
characteristics 77
timing diagram 77
address spaces, basic 1
architecture 1
expanded register file 18
B
basic address spaces 1
block diagram, ZLR16300 functional 4
C
capacitance 72
capture_INT_mask 24, 29
characteristics
AC 77
DC 72
clock 43
comparator inputs/outputs 14
configuration
port 0 9
port 3 11
port 3 counter/timer 13
counter/timer
16-bit circuits 36
8-bit circuits 32
brown-out voltage/standby 54
clock 43
demodulation mode count capture flowchart 34
demodulation mode flowchart 35
EPROM selectable options 54
glitch filter circuitry 30
halt instruction 44
input circuit 30
interrupt block diagram 41
interrupt types, sources and vectors 42
oscillator configuration 43
output circuit 39
ping-pong mode 38
port configuration register 46
resets and WDT 53
SCLK circuit 48
stop instruction 44
stop mode recovery register 47
stop mode recovery register 2 51
stop mode recovery source 49
T16 demodulation mode 37
T16 transmit mode 36
T16_OUT in modulo-N mode 37
T16_OUT in single-pass mode 37
T8 demodulation mode 33
T8 transmit mode 30
T8_OUT in modulo-N mode 33
T8_OUT in single-pass mode 33
transmit mode flowchart 31
voltage detection and flags 55
watch-dog timer mode register 51
watch-dog timer time select 53
counter/timer functional blocks
input circuit 30
T8 transmit mode 30
counter_INT_mask 29
crt3 T8/T16 control register
register 29
CTR(D)01h T8 and T16 common functions 25
ZGR163L
Product Specification
PS024009-0506 Index
92
CTR1 (0D)01 24
CTR3 T8/T16 control CTR3(0D)03h 29
D
DC characteristics 72
demodulation mode
count capture flowchart 34
flowchart 35
T16 37
T8 33
description
functional 15
general 4
pin 6
E
EPROM
selectable options 54
expanded register file 16
expanded register file architecture 18
expanded register file control registers 60
flag 69
interrupt mask register 68
interrupt priority register 67
interrupt request register 68
port 0 and 1 mode register 66
port 2 configuration register 64
port 3 mode register 65
port configuration register 64
register pointer 69
stack pointer high register 70
stack pointer low register 70
stop-mode recovery register 62
stop-mode recovery register 2 63
T16 control register 58
T8 and T16 common control functions register
57
TC8 control register 56
watch-dog timer register 64
F
features
standby modes 2
functional description
counter/timer functional blocks 30
CTR0(0D)00h register 23
CTR1(0D)01h register 25
CTR2(0D)02h register 28
expanded register file 16
expanded register file architecture 18
HI16(0D)09h register 22
HI8(0D)0Bh register 21
L08(0D)0Ah register 22
L0I6(0D)08h register 22
program memory map 16
RAM 15
register description 54
register file 20
register pointer 19
register pointer detail 21
stack 21
TC16H(0D)07h register 22
TC16L(0D)06h register 22
TC8H(0D)05h register 23
TC8L(0D)04h register 23
TC8L(D)04h register 23
G
glitch filter circuitry 30
H
halt instruction, counter/timer 44
I
input circuit 30
interrupt block diagram, counter/timer 41
interrupt types, sources and vectors 42
ZGR163L
Product Specification
PS024009-0506 Index
93
L
low-voltage detection register 54
M
memory, program 15
modulo-N mode
T16_OUT 37
T8_OUT 33
O
oscillator configuration 43
output circuit, counter/timer 39
P
P34_out 24
P35_out 29
P36_out/demodulator input 26
package information
20-pin DIP package diagram 79
20-pin SSOP package diagram 80
28-pin DIP package diagram 82
28-pin SOIC package diagram 81
28-pin SSOP package diagram 83
pin configuration
20-pin DIP/SOIC/SSOP 6
28-pin DIP/SOIC/SSOP 7
pin functions
port 0 (P07 - P00) 9
port 0 configuration 9
port 2 (P27 - P20) 10
port 2 (P37 - P30) 11
port 3 configuration 11
port 3 counter/timer configuration 13
XTAL1 (time-based input 8
XTAL2 (time-based output) 8
ping-pong mode 38
port 0
configuration 9
pin function 9
port 2
pin function 10
port 3
configuration 11
counter/timer configuration 13
port 3 pin function 11
port configuration register 46
power connections 1
power supply 6
program memory 15
map 16
R
ratings, absolute maximum 71
register 51
CTR0(0D)00h 23
CTR1 (0D) 01 24
CTR1(0D)01h 25
CTR2(0D)02h 28
flag 69
HI16(0D)09h 22
HI8(0D)0Bh 21
interrupt priority 67
interrupt request 68
interruptmask 68
L016(0D)08h 22
L08(0D)0Ah 22
LVD(D)0Ch 54
pointer 69
port 0 and 1 66
port 2 configuration 64
port 3 mode 65
port configuration 46, 64
stack pointer high 70
stack pointer low 70
stop mode recovery 47
stop mode recovery 2 51
stop-mode recovery 62
stop-mode recovery 2 63
T16 control 58
T8 and T16 common control functions 57
TC16H(0D)07h 22
TC16L(0D)06h 22
TC8 control 56
ZGR163L
Product Specification
PS024009-0506 Index
94
TC8H(0D)05h 23
TC8L(0D)04h 23
TC8L(D)04h 23
voltage detection 60
watch-dog timer 64
register description
counter/timer2 LS-Byte hold 22
counter/timer2 MS-Byte hold 22
counter/timer8 control 23
counter/timer8 High hold 23
counter/timer8 Low hold 23
CTR2 counter/timer 16 control 28
T16_capture_LO 22
T8 and T16 common functions 25
T8_Capture_HI 21
T8_capture_LO 22
register file 20
expanded 16
register pointer 19
detail 21
resets and WDT 53
S
SCLK circuit 48
single/modulo-N 24, 28
single-pass mode
T16_OUT 37
T8_OUT 33
stack 21
standard test conditions 71
standby modes 2
stop instruction, counter/timer 44
stop mode recovery
2 register 51
source 49
stop mode recovery 2 51
stop mode recovery register 47
T
T 16 clock 29
T16 enable 28
T16 initial out/falling edge 27
T16 transmit mode 36
T16_capture_HI 22
T8 and T16 common functions 24
t8 clock 24
T8 enable 24
T8 intiial out/rising edge 27
T8 transmit mode 30
T8/T16_logic/edge_detect 27
T8_Capture_HI 21
test conditions, standard 71
test load diagram 72
time_out 29
timeout 24
timers
counter/timer2 LS-byte hold 22
counter/timer2 MS-byte hold 22
counter/timer8 high hold 23
counter/timer8 low hold 23
CTR0 counter/timer8 control 23
T16_Capture_HI 22
T16_Capture_LO 22
T8_Capture_HI 21
T8_Capture_LO 22
timing diagram, AC 77
transmit mode flowchart 31
transmit_submode/glitch filter 27
V
VCC 6
voltage
brown-out/standby 54
detection and flags 55
voltage detection register 60
W
watch-dog timer
mode registerwatch-dog timer mode register 51
time select 53
X
XTAL1 6
