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Ver 1.0
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Description
DescriptionDescription
Description
Transcend PTM510-44V series is designed to install
on host with 44pin, 2.0mm pitch IDE interface. With
compact size and high quality NAND flash memory,
PTM510 is ideal for harsh environments such as
Industrial PCs, Set-Top Boxes, etc.
Placeme
PlacemePlaceme
Placement
ntnt
nt
Features
FeaturesFeatures
Features
•
RoHS compliant
• Built-in 13/24-bit ECC (Error Correction Code) functionality
and wear-leveling
- 13bit BCH ECC (2k+64 / 4k+128 byte per page flash)
- 24 bit BCH ECC (4k+208 / 8k+436 byte per page flash)
• Support global wear-leveling algorithm which ensures
maximum lifespan.
• Supports
Ultra DMA Mode 0 to 5
Multiword DMA mode 0 to 2
PIO Mode 0 to 4
• Supports Security Commands
• Support S.M.A.R.T function (self-definition)
• Support Host Protected Area
• Durability of Connector: 100 cycles
• MTBF: 1,000,000 hours (in 25
o
C)
Dimensions
DimensionsDimensions
Dimensions
Side
Millimeters Inches
A 52.00 ± 0.40 2.047 ± 0.016
B 29.5 ± 0.50 1.162 ± 0.020
C* 7.20 ± 0.20 0.284 ± 0.008
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Pin
Pin Pin
Pin Assignments
AssignmentsAssignments
Assignments
Pin
No.
Pin
Name
Pin
No.
Pin
Name
Pin
No
Pin
Name
Pin
No.
Pin
Name
01
-RESET
12
HD12
23
IOWB
34
PDIAGB
02
GND 13
HD2 24
GND
35
HA0
03
HD7 14
HD13
25
IORB
36
HA2
04
HD8 15
HD1 26
GND
37
CE1B
05
HD6 16
HD14
27
IORDY
38
CE2B
06
HD9 17
HD0 28
NC 39
DASPB
07
HD5 18
HD15
29
-DMACK
40
GND
08
HD10
19
GND 30
GND
41
VCC
09
HD4 20
NC 31
IREQ
42
VCC
10
HD11
21
DMARQ
32
IOIS16B
43
GND
11
HD3 22
GND 33
HA1 44
GND
Pin
Pin Pin
Pin Layout
LayoutLayout
Layout
Pin Definition
Pin DefinitionPin Definition
Pin Definition
Symbol Function
HD0 ~ HD15 Data Bus (Bi-directional)
HA0 ~ HA2 Address Bus (Input)
-RESET Device Reset (Input)
IORB Device I/O Read (Input)
IOWB Device I/O Write (Input)
IOIS16B Transfer Type 8/16 bit (Output)
CE1B, CE2B Chip Select (Input)
PDIAGB Pass Diagnostic (Bi-directional)
DASPB Disk Active/Slave Present
(Bi-directional)
DMARQ DMA request
DMACK- DMA acknowledge
IREQ Interrupt Request (Output)
NC No Connection
GND Ground
VCC Vcc Power Input
Pin1 Pin43
Pin2 Pin44
Bulge
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Ver 1.0
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Block Diagram
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Ver 1.0
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More Functions to extend product life
1. Global Wear Leveling – Advanced algorithm to enhance the Wear-Leveling Efficiency
There are 3 main processes in global wear leveling approaches:
(1) Record the block erase count and save in the wear-leveling table.
(2) Find the static-block and save it in wear-leveling pointer.
(3) Check the erase count when the block popped from spare pool. If the
block erase count is bigger
than WEARCNT, then swapped the static-block and over-count-block.
After actual test, global wear leveling successfully even the erase
count of every block; hence, it can
extend the life expectancy of Flash product.
2. StaticDataRefresh Technology – Keeping Data Healthy
There are many variants that would disturb the charge inside a Flash cell. These variants can be:
time,
read operations, undesired charge, heat, etc; each variant would create a charge loss, and the conte
nts
shift in their charge levels slightly. In our everyday usage –
more than 60% are repeated read operations,
the accumulated charge loss would eventually result in the data loss.
Normally, ECC engine corrections are taken place without affecting the host normal
operations. As
time passes by, the number of error bits accumulated in the read transaction
exceeds the correcting
capability of the ECC engine, resulting in corrupted data being sent to the host.
To prevent this, Transcend’s CF200I monitor the error bit levels at each read
operation; when it
reaches the preset threshold value, the controller automatically performs
data refresh to “restore” the
correct charge levels in the cell. This implementation practically restores the data to its original, error-
free
state, and hence, lengthening the life of the data.
3. EarlyRetirement – Avoiding Data Loss Due to Weak Block
The StaticDataRefresh feature functions well when the cells in a block are still healthy. As
the block
ages over time, it cannot store charge reliably anymore, EarlyRetirement enters the scene.
EarlyRetirement works by moving the static data to another block (a health block) before
the previously
used block becomes completely incapable of holding charges for data. When the charge loss error
level
exceeds another threshold value (higher from that for
StaticDataRefresh), the controller automatically
moves its data to another block. In addition,
the original block is then marked as a bad block, which
prevents its further use, and thus the block enters the state of “EarlyRetirement.”
Note that, through this
process, the incorrect data are detected and effectively corrected by
the ECC engine, thus the data in the
new block is stored error-free.
4. Advanced Power Shield – Avoiding Data Loss during Power Failure
When a power failure takes place, the line voltage drops. When it reaches the first Logic-
Freeze
Threshold, the core controller is held at a steady state. Here are some
implications. First, it ceases the
communication with the host. This prevents the host from
sending in further address/instructions/data that
may be corrupted. During power
disturbance, the host is likely experiencing a voltage drop, so the
transmission integrity cannot be guaranteed. Second, it stops the information sending to
the Flash. This
prevents the controller from corrupting the address/data being transmitted to the Flash, and
corrupting the
Flash contents inadvertently.
Further more, Advanced Power Shield cut off the connection between host power and turn off the
controller to reserve most of the energy for NAND Flash to complete programming. Due to S
LC structure,
an interrupted programming may damage a paired page which cause the previous written data lost.
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Absolute Maximum Rating
Absolute Maximum RatingAbsolute Maximum Rating
Absolute Maximum Ratings
ss
s
Symbol Parameter Min Max Unit
VDD-VSS DC Power Supply -0.6 +6 V
Ta Operating Temperature 0 +70 °C
Tst Storage Temperature -40 +85 °C
Recommended Operating Conditions
Recommended Operating ConditionsRecommended Operating Conditions
Recommended Operating Conditions
Symbol Parameter Min Max Units
VDD Power supply 3.0 5.5 V
VIN Input voltage 0 VDD+0.3 V
Ta Operating Temperature 0 +70 °C
DC Characteristics
DC Characteristics DC Characteristics
DC Characteristics
(Ta=0
o
C to +70
o
C, Vcc = 5.0V ±
±±
±10%)
Parameter Symbol
Min Max Unit Remark
Supply Voltage V
CC
4.5 5.5 V
High level output voltage V
OH
V
CC
-0.8 -- V
Low level output voltage V
OL
-- 0.8 V
4.0 --
V
Non-schmitt trigger
High level input voltage
V
IH
2.92 --
V
Schmitt trigger
1
-- 0.8
V
Non-schmitt trigger
Low level input voltage
V
IL
-- 1.70
V
Schmitt trigger
1
(Ta=0
o
C to +70
o
C, Vcc = 3.3V ±
±±
±5%)
Parameter Symbol
Min Max Unit Remark
Supply Voltage V
CC
3.135 3.465 V
High level output voltage V
OH
V
CC
-0.8 -- V
Low level output voltage V
OL
-- 0.8 V
2.4 --
V
Non-schmitt trigger
High level input voltage
V
IH
2.05 --
V
Schmitt trigger
1
-- 0.6
V
Non-schmitt trigger
Low level input voltage
V
IL
-- 1.25
V
Schmitt trigger
1
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True IDE PIO Mode Read/Write Timing
Item Mode
0
Mode
1
Mode
2
Mode
3
Mode
4
t
0
Cycle time (min)
1
600 383 240 180 120
t
1
Address Valid to -IORD/-IOWR setup (min)
70 50 30 30 25
t
2
-IORD/-IOWR (min)
1
165 125 100 80 70
t
2
-IORD/-IOWR (min) Register (8 bit)
290 290 290 80 70
t
2i
-IORD/-IOWR recovery time (min)
-- -- -- 70 25
t
3
-IOWR data setup (min)
60 45 30 30 20
t
4
-IOWR data hold (min)
30 20 15 10 10
t
5
-IORD data setup (min)
50 35 20 20 20
t
6
-IORD data hold (min)
5 5 5 5 5
t
6Z
-IORD data tristate (max)
2
30 30 30 30 30
t
7
Address valid to IOCS16 assertion (max)
4
90 50 40 N/A N/A
t
8
Address valid to IOCS16 released (max)
4
60 45 30 N/A N/A
t
9
-IORD/-IOWR to address valid hold
20 15 10 10 10
t
RD
Read Data Valid to IORDY active (min), if
IORDY initially low after tA
0 0 0 0 0
t
A
IORDY Setup time
3
35 35 35 35 35
t
B
IORDY Pulse Width (max)
1250
1250
1250
1250
1250
t
C
IORDY assertion to release (max)
5 5 5 5 5
Notes: All timings are in nanoseconds. The maximum load on -IOCS16 is 1 LSTTL with a 50 pF (40pF below
120nsec Cycle Time) total load. All times are in nanoseconds. Minimum time from -IORDY high to -IORD
high is 0 nsec, but minimum -IORD width shall still be met.
(1) t
0
is the minimum total cycle time, t
2
is the minimum command active time, and t
2i
is the minimum
command recovery time or command inactive time. The actual cycle time equals the sum of the actual
command active time and the actual command inactive time. The three timing requirements of t0, t
2
, and
t
2i
shall be met. The minimum total cycle time requirement is greater than the sum of t
2
and t
2i
. This means
a host implementation can lengthen either or both t
2
or t
2i
to ensure that t
0
is equal to or greater than the
value reported in the device’s identify device data.
(2) This parameter specifies the time from the negation edge of -IORD to the time that the data bus is
released by the device.
(3) The delay from the activation of -IORD or -IOWR until the state of IORDY is first sampled. If IORDY is
inactive then the host shall wait until IORDY is active before the PIO cycle can be completed. If the device
is not driving IORDY negated at t
A
after the activation of -IORD or -IOWR, then t
5
shall be met and t
RD
is
not applicable. If the device is driving IORDY negated at the time t
A
after the activation of -IORD or -IOWR,
then t
RD
shall be met and t5 is not applicable.
(4) t
7
and t
8
apply only to modes 0, 1 and 2. For other modes, this signal is not valid.
(5) IORDY is not supported in this mode.
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True IDE PIO Mode Timing Diagram
Figure 1:
True IDE PIO Mode Timing Diagram
Notes:
(1) Device address consists of -CS0, -CS1, and A[02::00]
(2) Data consists of D[15::00] (16-bit) or D[07::00] (8 bit)
(3) -IOCS16 is shown for PIO modes 0, 1 and 2. For other modes, this signal is ignored.
(4) The negation of IORDY by the device is used to extend the PIO cycle. The determination of whether the cycle
is to be extended is made by the host after t
A
from the assertion of -IORD or -IOWR. The assertion and
negation of IORDY is described in the following three cases:
(4-1) Device never negates IORDY: No wait is generated.
(4-2) Device starts to drive IORDY low before t
A
, but causes IORDY to be asserted before t
A
: No wait
generated.
(4-3) Device drives IORDY low before t
A
: wait generated. The cycle completes after IORDY is reasserted. For
cycles where a wait is generated and -IORD is asserted, the device shall place read data on D15-D00 for
t
RD
before causing IORDY to be asserted.
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True IDE Multiword DMA Mode Read/Write Timing Specification
Item Mode 0
(ns)
Mode 1
(ns)
Mode 2
(ns)
t
0
Cycle time (min)
1
480 150 120
t
D
-IORD / -IOWR asserted width(min)
1
215 80 70
t
E
-IORD data access (max) 150 60 50
t
F
-IORD data hold (min) 5 5 5
t
G
-IORD/-IOWR data setup (min) 100 30 20
t
H
-IOWR data hold (min) 20 15 10
t
I
DMACK to –IORD/-IOWR setup (min)
0 0 0
t
J
-IORD / -IOWR to -DMACK hold (min)
20 5 5
t
KR
-IORD negated width (min)
1
50 50 25
t
KW
-IOWR negated width (min)
1
215 50 25
t
LR
-IORD to DMARQ delay (max) 120 40 35
t
LW
-IOWR to DMARQ delay (max) 40 40 35
t
M
CS(1:0) valid to –IORD / -IOWR 50 30 25
t
N
CS(1:0) hold 15 10 10
t
Z
-DMACK 20 25 25
Notes:
(1) t
0
is the minimum total cycle time and t
D
is the minimum command active time, while t
KR
and t
KW
are the
minimum command recovery time or command inactive time for input and output cycles respectively. The
actual cycle time equals the sum of the actual command active time and the actual command inactive
time. The three timing requirements of t
0
, t
D
, t
KR
, and t
KW
shall be met. The minimum total cycle time
requirement is greater than the sum of t
D
and t
KR
or t
KW
.for input and output cycles respectively. This
means a host implementation can lengthen either or both of t
D
and either of t
KR
, and t
KW
as needed to
ensure that t
0
is equal to or greater than the value reported in the device’s identify device data.
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Ver 1.0
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True IDE Multiword DMA Mode Read/Write Timing Diagram
Figure 2: True IDE Multiword DMA Mode Read/Write Timing Diagram
Notes:
(1) If the Card cannot sustain continuous, minimum cycle time DMA transfers, it may negate DMARQ within the
time specified from the start of a DMA transfer cycle to suspend the DMA transfers in progress and reassert
the signal at a later time to continue the DMA operation.
(2) This signal may be negated by the host to suspend the DMA transfer in progress.
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Ultra DMA Mode Read/Write Timing Specification
Ultra DMA is an optional data transfer protocol used with the READ DMA, and WRITE DMA,
commands. When this protocol is enabled, the Ultra DMA protocol shall be used instead of the Multiword
DMA protocol when these commands are issued by the host. This protocol applies to the Ultra DMA data
burst only. When this protocol is used there are no changes to other elements of the ATA protocol.
UDMA Signal Type TRUE IDE MODE
UDMA
DMARQ Output DMARQ
DMACK Input -DMACK
STOP Input STOP
1
HDMARDY(R)
HSTROBE(W) Input -HDMARDY
1,2
HSTROBE(W)
1,3,4
DDMARDY(W)
DSTROBE(R) Output -DDMARDY(W)
1,3
DSTROBE(R)
1,2,4
DATA Bidir D[15:00]
ADDRESS Input A[02:00]
5
CSEL input -CSEL
INTRQ Output INTRQ
Card Select Input -CS0
-CS1
Notes: 1) The UDMA interpretation of this signal is valid only during an Ultra DMA data burst.
2) The UDMA interpretation of this signal is valid only during and Ultra DMA data burst during a DMA Read command.
3) The UDMA interpretation of this signal is valid only during an Ultra DMA data burst during a DMA Write command.
4) The HSTROBE and DSTROBE signals are active on both the rising and the falling edge.
5) Address lines 03 through 10 are not used in True IDE mode.
Several signal lines are redefined to provide different functions during an Ultra DMA data burst.
These lines assume their UDMA definitions when:
1. an Ultra DMA mode is selected, and
2. a host issues a READ DMA, or a WRITE DMA command requiring data transfer, and
3. the device asserts (-)DMARQ, and
4. the host asserts (-)DMACK.
These signal lines revert back to the definitions used for non-Ultra DMA transfers upon the negation
of -DMACK by the host at the termination of an Ultra DMA data burst.
With the Ultra DMA protocol, the STROBE signal that latches data from D[15:00] is generated by the
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same agent (either host or device) that drives the data onto the bus. Ownership of D[15:00] and this data
strobe signal are given either to the device during an Ultra DMA data-in burst or to the host for an Ultra
DMA data-out burst.
During an Ultra DMA data burst a sender shall always drive data onto the bus, and, after a sufficient
time to allow for propagation delay, cable settling, and setup time, the sender shall generate a STROBE
edge to latch the data. Both edges of STROBE are used for data transfers so that the frequency of
STROBE is limited to the same frequency as the data.
Words in the IDENTIFY DEVICE data indicate support of the Ultra DMA feature and the Ultra DMA
modes the device is capable of supporting. The Set transfer mode subcommand in the SET FEATURES
command shall be used by a host to select the Ultra DMA mode at which the system operates. The Ultra
DMA mode selected by a host shall be less than or equal to the fastest mode of which the device is
capable. Only one Ultra DMA mode shall be selected at any given time. All timing requirements for a
selected Ultra DMA mode shall be satisfied. Devices supporting any Ultra DMA mode shall also support
all slower Ultra DMA modes.
An Ultra DMA capable device shall retain the previously selected Ultra DMA mode after executing a
software reset sequence or the sequence caused by receipt of a DEVICE RESET command if a SET
FEATURES disable reverting to defaults command has been issued. The device may revert to a
Multiword DMA mode if a SET FEATURES enable reverting to default has been issued. An Ultra DMA
capable device shall clear any previously selected Ultra DMA mode and revert to the default non-Ultra
DMA modes after executing a power-on or hardware reset.
Both the host and device perform a CRC function during an Ultra DMA data burst. At the end of an
Ultra DMA data burst the host sends its CRC data to the device. The device compares its CRC data to the
data sent from the host. If the two values do not match, the device reports an error in the error register. If
an error occurs during one or more Ultra DMA data bursts for any one command, the device shall report
the first error that occurred. If the device detects that a CRC error has occurred before data transfer for
the command is complete, the device may complete the transfer and report the error or abort the
command and report the error.
NOTE − If a data transfer is terminated before completion, the assertion of INTRQ should be passed
through to the host software driver regardless of whether all data requested by the command has been
transferred.
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Ultra DMA Data Burst Timing Requirements
UDMA
M
ODE
0
UDMA
M
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1
UDMA
M
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2
UDMA
M
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3
UDMA
M
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4
UDMA
M
ODE
5
Name
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Measure location
(See Note 2)
t
2CYCTYP
240
160
120
90 60 40 Sender
t
CYC
112
73 54 39 25 16.8 Note 3
t
2CYC
230
153
115
86 57 38 Sender
t
DS
15.0
10.0
7.0 7.0 5.0 4.0 Recipient
t
DH
5.0 5.0 5.0 5.0 5.0 4.6 Recipient
t
DVS
70.0
48.0
31.0
20.0
6.7 4.8 Sender
t
DVH
6.2 6.2 6.2 6.2 6.2 4.8 Sender
t
CS
15.0
10.0
7.0 7.0 5.0 5.0 Device
t
CH
5.0 5.0 5.0 5.0 5.0 5.0 Device
t
CVS
70.0
48.0
31.0
20.0
6.7 10.0 Host
t
CVH
6.2 6.2 6.2 6.2 6.2 10.0 Host
t
ZFS
0 0 0 0 0 35 Device
t
DZFS
70.0
48.0
31.0
20.0
6.7 25 Sender
t
FS
230
200
170
130
120
90 Device
t
LI
0 150
0 150
0 150
0 100
0 100
0 75 Note 4
t
MLI
20 20 20 20 20 20 Host
t
UI
0 0 0 0 0 0 Host
t
AZ
10 10 10 10 10 10 Note 5
t
ZAH
20 20 20 20 20 20 Host
t
ZAD
0 0 0 0 0 0 Device
t
ENV
20 70 20 70 20 70 20 55 20 55 20 50 Host
t
RFS
75 70 60 60 60 50 Sender
t
RP
160
125
100
100
100
85 Recipient
t
IORDYZ
20 20 20 20 20 20 Device
t
ZIORDY
0 0 0 0 0 0 Device
t
ACK
20 20 20 20 20 20 Host
t
SS
50 50 50 50 50 50 Sender
Notes: All Timings in ns
(1) All timing measurement switching points (low to high and high to low) shall be taken at 1.5 V.
(2) All signal transitions for a timing parameter shall be measured at the connector specified in the measurement
location column. For example, in the case of t
RFS
, both STROBE and -DMARDY transitions are measured at the
sender connector.
(3) The parameter t
CYC
shall be measured at the recipient’s connector farthest from the sender.
(4) The parameter t
LI
shall be measured at the connector of the sender or recipient that is responding to an
incoming transition from the recipient or sender respectively. Both the incoming signal and the outgoing
response shall be measured at the same connector.
(5) The parameter t
AZ
shall be measured at the connector of the sender or recipient that is driving the bus but must
release the bus to allow for a bus turnaround.
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(6) See Page 14 the AC Timing requirements in Ultra DMA AC Signal Requirements.
Ultra DMA Data Burst Timing Descriptions
Name Comment Notes
t
2CYCTYP
Typical sustained average two cycle time
t
CYC
Cycle time allowing for asymmetry and clock variations (from STROBE edge to STROBE
edge)
t
2CYC
Two cycle time allowing for clock variations (from rising edge to next rising edge or from
falling edge to next falling edge of STROBE)
t
DS
Data setup time at recipient (from data valid until STROBE edge) 2,
t
DH
Data hold time at recipient (from STROBE edge until data may become invalid) 2,
t
DVS
Data valid setup time at sender (from data valid until STROBE edge) 3
t
DVH
Data valid hold time at sender (from STROBE edge until data may become invalid) 3
t
CS
CRC word setup time at device 2
t
CH
CRC word hold time device 2
t
CVS
CRC word valid setup time at host (from CRC valid until -DMACK negation) 3
t
CVH
CRC word valid hold time at sender (from -DMACK negation until CRC may become
invalid)
3
t
ZFS
Time from STROBE output released-to-driving until the first transition of critical timing.
t
DZFS
Time from data output released-to-driving until the first transition of critical timing.
t
FS
First STROBE time (for device to first negate DSTROBE from STOP during a data in burst)
t
LI
Limited interlock time 1
t
MLI
Interlock time with minimum 1
t
UI
Unlimited interlock time 1
t
AZ
Maximum time allowed for output drivers to release (from asserted or negated)
t
ZAH
Minimum delay time required for output
t
ZAD
drivers to assert or negate (from released)
t
ENV
Envelope time (from -DMACK to STOP and -
HDMARDY during data in burst initiation and
from DMACK to STOP during data out burst initiation)
t
RFS
Ready-to-final-STROBE time (no STROBE edges shall be sent this long after negation of
-DMARDY)
t
RP
Ready-to-pause time (that recipient shall wait to pause after negating -DMARDY)
t
IORDYZ
Maximum time before releasing IORDY
t
ZIORDY
Minimum time before driving IORDY 4,
t
ACK
Setup and hold times for -DMACK (before assertion or negation)
t
SS
Time from STROBE edge to negation of DMARQ or assertion of STOP (when sender
terminates a burst)
Notes:
(1) The parameters t
UI
, t
MLI
(in Page 19: Ultra DMA Data-In Burst Device Termination Timing and Page 20: Ultra DMA Data-In
Burst Host Termination Timing), and t
LI
indicate sender-to-recipient or recipient-to-sender interlocks,i.e., one agent (either
sender or recipient) is waiting for the other agent to respond with a signal before proceeding.t
UI
is an unlimited interlock
that has no maximum time value. t
ML
I is a limited time-out that has a defined minimum. t
LI
is a limited time-out that has a
defined maximum.
(2) 80-conductor cabling (see see ATA specification :Annex A)) shall be required in order to meet setup (t
DS
, t
CS
) and hold (t
DH
,
t
CH
) times in modes greater than 2.
(3) Timing for
t
DVS
,
t
DVH
, t
CVS
and t
CVH
shall be met for lumped capacitive loads of 15 and 40 pF at the connector where the
Data and STROBE signals have the same capacitive load value. Due to reflections on the cable, these timing
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measurements are not valid in a normally functioning system.
(4) For all timing modes the parameter t
ZIORDY
may be greater than t
ENV
due to the fact that the host has a pull-up on IORDY-
giving it a known state when released.
Ultra DMA Sender and Recipient IC Timing Requirements
UDMA Mode 0
(ns)
UDMA Mode 1
(ns)
UDMA Mode 2
(ns)
UDMA Mode 3
(ns)
UDMA Mode 4
(ns)
UDMA Mode 5
(ns)
Name
Min Max Min Max Min Max Min Max Min Max Min Max
t
DSIC
14.7 9.7 6.8 6.8 4.8 2.3
t
DHIC
4.8 4.8 4.8 4.8 4.8 2.8
t
DVSIC
72.9 50.9 33.9 22.6 9.5 6.0
t
DVHIC
9.0 9.0 9.0 9.0 9.0 6.0
t
DSIC
Recipient IC data setup time (from data valid until STROBE edge) (see note 2)
t
DHIC
Recipient IC data hold time (from STROBE edge until data may become invalid) (see note 2)
t
DVSIC
Sender IC data valid setup time (from data valid until STROBE edge) (see note 3)
t
DVHIC
Sender IC data valid hold time (from STROBE edge until data may become invalid) (see note 3)
Notes:
(1) All timing measurement switching points(low to high and high to low) shall be taken at 1.5 V.
(2) The correct data value shall be captured by the recipient given input data with a slew rate of 0.4 V/ns rising and
falling and the input STROBE with a slew rate of 0.4 V/ns rising and falling at t
DSIC
and t
DHIC
timing (as
measured through 1.5 V).
(3) The parameters t
DVSIC
and t
DVHIC
shall be met for lumped capacitive loads of 15 and 40 pF at the IC where all
signals have the same capacitive load value. Noise that may couple onto the output signals from external
sources has not been included in these values.
Ultra DMA AC Signal Requirements
Name Comment Min[V/ns] Max [V/ns] Note
S
RISE
Rising Edge Slew Rate for any signal 1.25 1
S
FALL
Falling Edge Slew Rate for any signal 1.25 1
Note:
(1) The sender shall be tested while driving an 18 inch long, 80 conductor cable with PVC insulation material. The
signal under test shall be cut at a test point so that it has not trace, cable or recipient loading after the test
point. All other signals should remain connected through to the recipient. The test point may be located at any
point between the sender’s series termination resistor and one half inch or less of conductor exiting the
connector. If the test point is on a cable conductor rather than the PCB, an adjacent ground conductor shall
also be cut within one half inch of the connector.
The test load and test points should then be soldered directly to the exposed source side connectors. The test
loads consist of a 15 pF or a 40 pF, 5%, 0.08 inch by 0.05 inch surface mount or smaller size capacitor from
the test point to ground. Slew rates shall be met for both capacitor values.
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Measurements shall be taken at the test point using a <1 pF, >100 Kohm, 1 Ghz or faster probe and a 500
MHz or faster oscilloscope. The average rate shall be measured from 20% to 80% of the settled VOH level
with data transitions at least 120 nsec apart. The settled VOH level shall be measured as the average output
high level under the defined testing conditions from 100 nsec after 80% of a rising edge until 20% of the
subsequent falling edge.
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Initiating an Ultra DMA Data-In Burst
(a) An Ultra DMA Data-In burst is initiated by following the steps lettered below. The timing diagram is
shown in below: Ultra DMA Data-In Burst Initiation Timing. The associated timing parameters are
specified in Page 12: Ultra DMA Data Burst Timing Requirements and are described in Page 13: Ultra
DMA Data Burst Timing Descriptions.
(b) The following steps shall occur in the order they are listed unless otherwise specifically allowed:
(c) The host shall keep -DMACK in the negated state before an Ultra DMA data burst is initiated.
(d) The device shall assert DMARQ to initiate an Ultra DMA data burst. After assertion of DMARQ the
device shall not negate DMARQ until after the first negation of DSTROBE.
(e) Steps (c), (d), and (e) may occur in any order or at the same time. The host shall assert STOP.
(f) The host shall negate -HDMARDY.
(g) In True IDE mode, the host shall not assert -CS0, -CS1 and A[02:00].
(h) Steps (c), (d), and (e) shall have occurred at least t
ACK
before the host asserts -DMACK. The host shall
keep -DMACK asserted until the end of an Ultra DMA data burst.
(i) The host shall release D[15:00] within t
AZ
after asserting -DMACK.
(j) The device may assert DSTROBE t
ZIORDY
after the host has asserted -DMACK. While operating in True
IDE mode, once the device has driven DSTROBE, the device shall not release DSTROBE until after
the host has negated -DMACK at the end of an Ultra DMA data burst.
(k) The host shall negate STOP and assert -HDMARDY within t
ENV
after asserting -DMACK. After
negating STOP and asserting -HDMARDY, the host shall not change the state of either signal until
after receiving the first transition of DSTROBE from the device (i.e., after the first data word has been
received).
(l) The device shall drive D[15:00] no sooner than t
ZAD
after the host has asserted -DMACK, negated
STOP, and asserted -HDMARDY.
(m) The device shall drive the first word of the data transfer onto D[15:00]. This step may occur when the
device first drives D[15:00] in step (j).
(n) To transfer the first word of data the device shall negate DSTROBE within t
FS
after the host has
negated STOP and asserted -HDMARDY. The device shall negate DSTROBE no sooner than t
DVS
after driving the first word of data onto D[15:00].
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ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH.
NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM.
Notes:
The definitions for the IORDY:-DDMARDY:DSTROBE, -IORD: -HDMARDY:HSTROBE, and -IOWR:STOP
signal lines are not in effect until DMARQ and -DMACK are asserted. A[02:00], -CS0 & -CS1 are True IDE mode
signal definitions.
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Sustaining an Ultra DMA Data-In Burst
An Ultra DMA Data-In burst is sustained by following the steps lettered below. The timing diagram
is shown in below: Sustained Ultra DMA Data-In Burst Timing. The timing parameters are specified in
Page 12: Ultra DMA Data Burst Timing Requirements and are described in Page 13: Ultra DMA Data
Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
a) The device shall drive a data word onto D[15:00].
b) The device shall generate a DSTROBE edge to latch the new word no sooner than t
DVS
after changing
the state of D[15:00]. The device shall generate a DSTROBE edge no more frequently than t
CYC
for the
selected Ultra DMA mode. The device shall not generate two rising or two falling DSTROBE edges
more frequently than 2t
cyc
for the selected Ultra DMA mode.
c) The device shall not change the state of D[15:00] until at least t
DVH
after generating a DSTROBE edge
to latch the data.
d) The device shall repeat steps (a), (b), and (c) until the data transfer is complete or an Ultra DMA data
burst is paused, whichever occurs first.
Notes: D[15:00] and DSTROBE signals are shown at both the host and the device to emphasize that cable settling
time as well as cable propagation delay shall not allow the data signals to be considered stable at the host
until some time after they are driven by the device.
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Host Pausing an Ultra DMA Data-In Burst
The host pauses a Data-In burst by following the steps lettered below. A timing diagram is shown in
below: Ultra DMA Data-In Burst Host Pause Timing. The timing parameters are specified in Page 12:
Ultra DMA Data Burst Timing Requirements and are described in Page 13: Ultra DMA Data Burst Timing
Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
(a) The host shall not pause an Ultra DMA data burst until at least one data word of an Ultra DMA data
burst has been transferred.
(b) The host shall pause an Ultra DMA data burst by negating -HDMARDY.
(c) The device shall stop generating DSTROBE edges within t
RFS
of the host negating -HDMARDY.
(d) While operating in Ultra DMA modes 2, 1, or 0 the host shall be prepared to receive zero, one or two
additional data words after negating -HDMARDY. While operating in Ultra DMA modes 4 or 3 the host
shall be prepared to receive zero, one, two or three additional data words. The additional data words
are a result of cable round trip delay and t
RFS
timing for the device.
(e) The host shall resume an Ultra DMA data burst by asserting -HDMARDY.
ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH.
NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM.
Notes:
(1) The host may assert STOP to request termination of the Ultra DMA data burst no sooner than t
RP
after
-HDMARDY is negated.
(2) After negating -HDMARDY, the host may receive zero, one, two, or three more data words from the device.
(3) The bus polarity of the (-) DMARQ and (-)DMACK signals is dependent on the active interface mode.
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Device Terminating an Ultra DMA Data-In Burst
The device terminates an Ultra DMA Data-In burst by following the steps lettered below. The timing
diagram is shown in below: Ultra DMA Data-In Burst Device Termination Timing. The timing parameters
are specified in Page 12: Ultra DMA Data Burst Timing Requirements and are described in Page 13: Ultra
DMA Data Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
(a) The device shall not pause an Ultra DMA data burst until at least one data word of an Ultra DMA data
burst has been transferred.
(b) The device shall pause an Ultra DMA data burst by not generating DSTROBE edges.
(c) NOTE − The host shall not immediately assert STOP to initiate Ultra DMA data burst termination
when the device stops generating STROBE edges. If the device does not negate DMARQ, in order to
initiate Ultra DMA data burst termination, the host shall negate -HDMARDY and wait t
RP
before
asserting STOP.
(d) The device shall resume an Ultra DMA data burst by generating a DSTROBE edge.
ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH.
NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM.
Notes: The definitions for the STOP, HDMARDY, and DSTROBE signal lines are no longer in effect after DMARQ
and DMACK are negated. A[02:00], -CS0 & -CS1 are True IDE mode signal definitions.
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Host Terminating an Ultra DMA Data-In Burst
The host terminates an Ultra DMA Data-In burst by following the steps lettered below. The timing
diagram is shown in below: Ultra DMA Data-In Burst Host Termination Timing. The timing parameters are
specified in Page 12: Ultra DMA Data Burst Timing Requirements and are described in Page 13: Ultra
DMA Data Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
(a) The host shall not initiate Ultra DMA data burst termination until at least one data word of an Ultra
DMA data burst has been transferred.
(b) The host shall initiate Ultra DMA data burst termination by negating -HDMARDY. The host shall
continue to negate -HDMARDY until the Ultra DMA data burst is terminated.
(c) The device shall stop generating DSTROBE edges within t
RFS
of the host negating -HDMARDY
(d) While operating in Ultra DMA modes 2, 1, or 0 the host shall be prepared to receive zero, one or two
additional data words after negating -HDMARDY. While operating in Ultra DMA modes 4 or 3 the
host shall be prepared to receive zero, one, two or three additional data words. The additional data
words are a result of cable round trip delay and t
RFS
timing for the device.
(e) The host shall assert STOP no sooner than t
RP
after negating -HDMARDY. The host shall not negate
STOP again until after the Ultra DMA data burst is terminated.
(f) The device shall negate DMARQ within t
LI
after the host has asserted STOP. The device shall not
assert DMARQ again until after the Ultra DMA data burst is terminated.
(g) If DSTROBE is negated, the device shall assert DSTROBE within t
LI
after the host has asserted STOP.
No data shall be transferred during this assertion. The host shall ignore this transition on DSTROBE.
DSTROBE shall remain asserted until the Ultra DMA data burst is terminated.
(h) The device shall release D[15:00] no later than t
AZ
after negating DMARQ.
(i) The host shall drive D[15:00] no sooner than t
ZAH
after the device has negated DMARQ. For this step,
the host may first drive D[15:00] with the result of its CRC calculation (see ATA specification Ultra DMA
CRC Calculation).
(j) If the host has not placed the result of its CRC calculation on D[15:00] since first driving D[15:00]
during (9), the host shall place the result of its CRC calculation on D[15:00] (see ATA specification Ultra
DMA CRC Calculation).
(k) The host shall negate -DMACK no sooner than t
MLI
after the device has asserted DSTROBE and
negated DMARQ and the host has asserted STOP and negated -HDMARDY, and no sooner than t
DVS
after the host places the result of its CRC calculation on D[15:00].
(l) The device shall latch the host’s CRC data from D[15:00] on the negating edge of -DMACK.
(m) The device shall compare the CRC data received from the host with the results of its own CRC
calculation. If a miscompare error occurs during one or more Ultra DMA data burst for any one
command, at the end of the command, the device shall report the first error that occurred (see ATA
specification Ultra DMA CRC Calculation)
(n) While operating in True IDE mode, the device shall release DSTROBE within t
IORDYZ
after the host
negates -DMACK.
(o) The host shall neither negate STOP nor assert -HDMARDY until at least t
ACK
after the host has
negated -DMACK.
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(p) In True IDE mode, the host shall not assert -IORD, -CS0, -CS1, nor A[02:00] until at least t
ACK
after
negating DMACK.
ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH.
NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM.
Notes: The definitions for the STOP, HDMARDY, and DSTROBE signal lines are no longer in effect after DMARQ
and DMACK are negated. A[02:00], -CS0 & -CS1 are True IDE mode signal definitions.
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Initiating an Ultra DMA Data-Out Burst
An Ultra DMA Data-out burst is initiated by following the steps lettered below. The timing diagram is
shown in below: Ultra DMA Data-Out Burst Initiation Timing. The timing parameters are specified in Page
12: Ultra DMA Data Burst Timing Requirements and are described in Page 13:Ultra DMA Data Burst
Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
(a) The host shall keep -DMACK in the negated state before an Ultra DMA data burst is initiated.
(b) The device shall assert DMARQ to initiate an Ultra DMA data burst.
(c) Steps (c), (d), and (e) may occur in any order or at the same time. The host shall assert STOP.
(d) The host shall assert HSTROBE.
(e) In True IDE mode, the host shall not assert -CS0, -CS1, nor A[02:00].
(f) Steps (c), (d), and (e) shall have occurred at least t
ACK
before the host asserts -DMACK.The host shall
keep -DMACK asserted until the end of an Ultra DMA data burst.
(g) The device may negate -DDMARDY t
ZIORDY
after the host has asserted -DMACK. While operating in
True IDE mode, once the device has negated -DDMARDY, the device shall not release -DDMARDY
until after the host has negated DMACK at the end of an Ultra DMA data burst.
(h) The host shall negate STOP within t
ENV
after asserting -DMACK. The host shall not assert STOP until
after the first negation of HSTROBE.
(i) The device shall assert -DDMARDY within t
LI
after the host has negated STOP. After asserting
DMARQ and -DDMARDY the device shall not negate either signal until after the first negation of
HSTROBE by the host.
(j) The host shall drive the first word of the data transfer onto D[15:00]. This step may occur any time
during Ultra DMA data burst initiation.
(k) To transfer the first word of data: the host shall negate HSTROBE no sooner than t
UI
after the device
has asserted -DDMARDY. The host shall negate HSTROBE no sooner than t
DVS
after the driving the
first word of data onto D[15:00].
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ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH.
NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM.
Note: The definitions for the STOP, DDMARDY, and HSTROBE signal lines are not in effect until DMARQ and
DMACK are asserted. A[02:00], -CS0 & -CS1 are True IDE mode signal definitions.
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Sustaining an Ultra DMA Data-Out Burst
An Ultra DMA Data-Out burst is sustained by following the steps lettered below. The timing diagram
is shown in below: Sustained Ultra DMA Data-Out Burst Timing. The associated timing parameters are
specified in Page 12: Ultra DMA Data Burst Timing Requirements and are described in Page 13: Ultra
DMA Data Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
(a) The host shall drive a data word onto D[15:00].
(b) The host shall generate an HSTROBE edge to latch the new word no sooner than t
DVS
after changing
the state of D[15:00]. The host shall generate an HSTROBE edge no more frequently than t
CYC
for the
selected Ultra DMA mode. The host shall not generate two rising or falling HSTROBE edges more
frequently than 2t
cyc
for the selected Ultra DMA mode.
(c) The host shall not change the state of D[15:00] until at least t
DVH
after generating an HSTROBE edge
to latch the data.
(d) The host shall repeat steps (a), (b), and (c) until the data transfer is complete or an Ultra DMA data
burst is paused, whichever occurs first.
Note: Data (D[15:00]) and HSTROBE signals are shown at both the device and the host to emphasize that cable
settling time as well as cable propagation delay shall not allow the data signals to be considered stable at
the device until some time after they are driven by the host.
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Device Pausing an Ultra DMA Data-Out Burst
The device pauses an Ultra DMA Data-Out burst by following the steps lettered below. The timing
diagram is shown in below: Ultra DMA Data-Out Burst Device Pause Timing. The timing parameters are
specified in Page 12: Ultra DMA Data Burst Timing Requirements and are described in Page 13: Ultra
DMA Data Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
(a) The device shall not pause an Ultra DMA data burst until at least one data word of an Ultra DMA data
burst has been transferred.
(b) The device shall pause an Ultra DMA data burst by negating -DDMARDY.
(c) The host shall stop generating HSTROBE edges within t
RFS
of the device negating -DDMARDY.
(d) While operating in Ultra DMA modes 2, 1, or 0 the device shall be prepared to receive zero, one or two
additional data words after negating -HDMARDY. While operating in Ultra DMA modes 4 or 3 the
device shall be prepared to receive zero, one, two or three additional data words. The additional data
words are a result of cable round trip delay and t
RFS
timing for the device.
(e) The device shall resume an Ultra DMA data burst by asserting -DDMARDY.
ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH.
NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM.
Notes:
(1) The device may negate DMARQ to request termination of the Ultra DMA data burst no sooner than t
RP
after -DDMARDY is
negated.
(2) After negating -DDMARDY, the device may receive zero, one, two, or three more data words from the host.
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Device Terminating an Ultra DMA Data-Out Burst
The device terminates an Ultra DMA Data-Out burst by following the steps lettered below. The timing
diagram for the operation is shown in below: Ultra DMA Data-Out Burst Device Termination Timing. The
timing parameters are specified in Page 12: Ultra DMA Data Burst Timing Requirements and are
described in Page 13: Ultra DMA Data Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
(a) The device shall not initiate Ultra DMA data burst termination until at least one data word of an Ultra
DMA data burst has been transferred.
(b) The device shall initiate Ultra DMA data burst termination by negating -DDMARDY.
(c) The host shall stop generating an HSTROBE edges within t
RFS
of the device negating -DDMARDY.
(d) While operating in Ultra DMA modes 2, 1, or 0 the device shall be prepared to receive zero, one or two
additional data words after negating -HDMARDY. While operating in Ultra DMA modes 4 or 3 the
device shall be prepared to receive zero, one, two or three additional data words. The additional data
words are a result of cable round trip delay and t
RFS
timing for the device.
(e) The device shall negate DMARQ no sooner than t
RP
after negating -DDMARDY. The device shall not
assert DMARQ again until after the Ultra DMA data burst is terminated.
(f) The host shall assert STOP within t
LI
after the device has negated DMARQ. The host shall not negate
STOP again until after the Ultra DMA data burst is terminated.
(g) If HSTROBE is negated, the host shall assert HSTROBE within t
LI
after the device has negated
DMARQ. No data shall be transferred during this assertion. The device shall ignore this transition of
HSTROBE. HSTROBE shall remain asserted until the Ultra DMA data burst is terminated.
(h) The host shall place the result of its CRC calculation on D[15:00] (see ATA specification Ultra DMA
CRC Calculation).
(i) The host shall negate -DMACK no sooner than t
MLI
after the host has asserted HSTROBE and STOP
and the device has negated DMARQ and -DDMARDY, and no sooner than t
DVS
after placing the result
of its CRC calculation on D[15:00].
(j) The device shall latch the host’s CRC data from D[15:00] on the negating edge of -DMACK.
(k) The device shall compare the CRC data received from the host with the results of its own CRC
calculation. If a miscompare error occurs during one or more Ultra DMA data bursts for any one
command, the device shall report the first error that occurred (see ATA specification Ultra DMA CRC
Calculation).
(l) While operating in True IDE mode, the device shall release DSTROBE within t
IORDYZ
after the host
negates -DMACK.
(m) The host shall not negate STOP nor assert –HDMARDY until at least t
ACK
after negating -DMACK.
(n) In True IDE mode, the host shall not assert -IOWR, -CS0, -CS1, nor A[02:00] until at least t
ACK
after
negating DMACK.
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ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH.
NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM.
Note: The definitions for the STOP, DDMARDY, and HSTROBE signal lines are no longer in effect after DMARQ
and DMACK are negated. A00-A02, -CS0 & -CS1 are True IDE mode signal definitions.
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Host Terminating an Ultra DMA Data-Out Burst
Termination of an Ultra DMA Data-Out burst by the host is shown in below: Ultra DMA Data-Out
Burst Host Termination Timing while timing parameters are specified in Page 12: Ultra DMA Data Burst
Timing Requirements and timing parameters are described in Page 13: Ultra DMA Data Burst Timing
Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
(a) The host shall initiate termination of an Ultra DMA data burst by not generating HSTROBE edges.
(b) The host shall assert STOP no sooner than t
SS
after it last generated an HSTROBE edge.The host
shall not negate STOP again until after the Ultra DMA data burst is terminated.
(c) The device shall negate DMARQ within t
LI
after the host asserts STOP. The device shall not assert
DMARQ again until after the Ultra DMA data burst is terminated.
(d) The device shall negate -DDMARDY within t
LI
after the host has negated STOP. The device shall not
assert -DDMARDY again until after the Ultra DMA data burst termination is complete.
(e) If HSTROBE is negated, the host shall assert HSTROBE within t
LI
after the device has negated
DMARQ. No data shall be transferred during this assertion. The device shall ignore this transition on
HSTROBE. HSTROBE shall remain asserted until the Ultra DMA data burst is terminated.
(f) The host shall place the result of its CRC calculation on D[15:00] (see ATA specification Ultra DMA
CRC Calculation).
(g) The host shall negate -DMACK no sooner than t
MLI
after the host has asserted HSTROBE and STOP
and the device has negated DMARQ and -DDMARDY, and no sooner than t
DVS
after placing the result
of its CRC calculation on D[15:00].
(h) The device shall latch the host’s CRC data from D[15:00] on the negating edge of -DMACK.
(i) The device shall compare the CRC data received from the host with the results of its own CRC
calculation. If a miscompare error occurs during one or more Ultra DMA data bursts for any one
command, at the end of the command, the device shall report the first error that occurred (see ATA
specification Ultra DMA CRC Calculation).
(j) While operating in True IDE mode, the device shall release -DDMARDY within t
IORDYZ
after the host
has negated -DMACK.
(k) The host shall neither negate STOP nor negate HSTROBE until at least t
ACK
after negating -DMACK.
(l) In True IDE mode, the host shall not assert -IOWR, -CS0, -CS1, nor A[02:00] until at least t
ACK
after
negating DMACK..
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ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH.
NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM.
Notes: The definitions for the STOP, DDMARDY, and HSTROBE signal lines are no longer in effect after DMARQ
and DMACK are negated. A[02:00], -CS0 & -CS1 are True IDE mode signal definitions.
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IDENTIFY DEVICE information
The Identify Device command enables the host to receive parameter information from the device.
This command has the same protocol as the Read Sector(s) command. The parameter words in the
buffer have the arrangement and meanings defined in Table as below. All reserved bits or words are zero.
Hosts should not depend on Obsolete words in Identify Device containing 0. Table below specifies each
field in the data returned by the Identify Device Command. In Table as below, X indicates a numeric
nibble value specific to the card and aaaa indicates an ASCII string specific to the particular drive.
Word
Address
Default
Value
Total
Bytes
Data Field Type Information
0 044Ah
2 General configuration – Bit Significant with ATA-4 definitions.
1 XXXXh
2 Default number of cylinders
2 0000h
2 Reserved
3 00XXh
2 Default number of heads
4 0000h
2 Obsolete
5 0240h
2 Obsolete
6 XXXXh
2 Default number of sectors per track
7-8 XXXXh
4 Number of sectors per card (Word 7 = MSW, Word 8 = LSW)
9 0000h
2 Obsolete
10-19 XXXXh
20 Serial number in ASCII (Right Justified)
20 0002h
2 Obsolete
21 0000h
2 Obsolete
22 0000h
2 Number of ECC bytes passed on Read/Write Long Commands
23-26 XXXXh
8 Firmware revision in ASCII. Big Endian Byte Order in Word
27-46 XXXXh
40 Model number in ASCII (Left Justified) Big Endian Byte Order in
Word
47 8001h
2 Maximum number of sectors on Read/Write Multiple command
48 0000h
2 Reserved
49 0F00h
2 Capabilities
50 0000h
2 Reserved
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~
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~
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Word
Address
Default
Value
Total
Bytes
Data Field Type Information
51 0200h
2 PIO data transfer cycle timing mode
52 0000h
2 Obsolete
53 0007h
2 Field Validity
54 XXXXh
2 Current numbers of cylinders
55 XXXXh
2 Current numbers of heads
56 XXXXh
2 Current sectors per track
57-58 XXXXh
4 Current capacity in sectors (LBAs)(Word 57 = LSW, Word 58 =
MSW)
59 0100h
2 Multiple sector setting
60-61 XXXXh
4 Total number of sectors addressable in LBA Mode
62 0000h
2 Reserved
63 0007h
2 Multiword DMA transfer. In PC Card modes this value shall be 0h
64 0003h
2 Advanced PIO modes supported
65 0078h
2 Minimum Multiword DMA transfer cycle time per word. In PC Card
modes this value shall be 0h
66 0078h
2 Recommended Multiword DMA transfer cycle time. In PC Card
modes
this value shall be 0h
67 0078h
2 Minimum PIO transfer cycle time without flow control
68 0078h
2 Minimum PIO transfer cycle time with IORDY flow control
69-79 0000h
22 Reserved
80 0080h
2 Major version number(ATA/ATAPI-7)
81 0000h
2 Minor version number
82 742Bh
2 Command sets supported
83 5008h
2 Command sets supported
84 4003h
2 Command sets supported
85 0400h
2 Command sets enable
86 0000h
2 Command sets enable
87 0003h
2 Command sets enable
88 001Fh
2 Ultra DMA Mode Supported and Selected
89 0001h
2 Time required for Security erase unit completion
90 0000h
2 Time required for Enhanced security erase unit completion
91 0000h
2 Current Advanced power management value
92 FFFEh
72 Master Password Revision Code
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93
604Fh
6F00h
603Fh
2
• Hardware reset result (Master only)
• Hardware reset result (Slave only)
• Hardware reset result (Master w/ slave present)
94 - 127
0000h
68 Reserved
128 0001h
2 Security status
129-159
0000h
62 Vendor unique bytes
160 0000h
2 Power requirement description
161 0000h
2 Reserved
162 0000h
2 Key management schemes supported
163 0000h
2 CF Advanced True IDE Timing Mode Capability and Setting
164 0000h
2 Reserved
165-175
0000h
22 Reserved
176-255
0000h
140 Reserved
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ATA Command Support
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SMART Command Support
SM2231 supports the SMART command set and devines some vendor-specific data to report
spare/bad block numbers in each memory management units. Users can obtain the data using the “Read
Data” command.
SMART Feature Register Values
If the reserved size is below a threshold, the status can be read from the Cylinder Register using the
Return Status command (DAh)
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SMART Data Structure (Read Data (D0h))
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2G
G
G
~
~
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Specifications:
Transcend P/N Capacity Cylinder (C) Head (H) Sector (S)
TS2GDOM44V-S 2GB 3884 16 63
TS4GDOM44V-S 4GB 7769 16 63
TS8GDOM44V-S 8GB 15538 16 63
Performance
Sequential Read Sequential Write Random 4K Read Random 4K Write
2GB
29.94 11.77 9.287 0.053
4GB
56.29 22.29 13.08 0.058
8GB
50.66 34.98 8.409 0.058
Note : Test by Crystal Disk Mark V3.0.1, 500MB size @25
o
C, P5K-VM(ICH 9), 1GB RAM * 2, IDE
interface support up to UDMA6, Windows® XP SP3.
Power consumption
Capacity 2GB 4GB 8GB
Read
58.1 119.1 112.3
Write
58 80.2 92.9
Idle
0.4 0.4 0.4
Note: Based on JEDEC JESD218A specification, Client Application Class. And based on the following
scenario: Active use : 40
o
C, 8hrs/day
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Ordering Information
Ordering InformationOrdering Information
Ordering Information
The above technical information is based on industry standard data and has been tested to be reliable. However, Transcend
makes no warranty, either expressed or implied, as to its accuracy and assumes no liability in connection with the use of this
product. Transcend reserves the right to make changes to the specifications at any time without prior notice.
USA
Los Angeles:
E-mail: sales@transcendusa.com
Maryland:
E-mail: sales_md@transcendusa.com
www.transcendusa.com
CHINA
E-mail: sales@transcendchina.com
www.transcendchina.com
GERMANY
E-mail: vertrieb@transcend.de
www.transcend.de
HONG KONG
E-mail: sales@transcend.com.hk
www.transcendchina.com
JAPAN
E-mail: sales@transcend.co.jp
www.transcend.jp
THE NETHERLANDS
E-mail: sales@transcend.nl
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TAIWAN
No.70, XingZhong Rd., NeiHu Dist., Taipei, Taiwan, R.O.C
TEL +886-2-2792-8000
Fax +886-2-2793-2222
E-mail: sales@transcend.com.tw
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United Kingdom
E-mail: sales@transcend-uk.com
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Flash Type
Flash TypeFlash Type
Flash Type
(5: SLC)
(5: SLC)(5: SLC)
(5: SLC)
