1
®
FN3116.9
DG406, DG407
Single 16-Channel/Differential 8-Channel,
CMOS Analog Multiplexers
The DG406 and DG407 monolithic CMOS analog
multiplexers are drop-in replacements for the popular
DG506A and DG507A series devices . They each include an
array of sixteen analog switches, a TTL and CMOS
compatible digital decode circuit for channel selection, a
voltage reference f or logic thresholds, and an ENABLE input
for device selection when several multiplexers are present.
These multiplexers feature lower signal ON resistance
(<100Ω) and faster transition time (tTRANS < 300ns)
compared to the DG506A and DG507A. Charge injection
has been reduced, simplifying sample and hol d applications.
The improvements in the DG406 series are made possible
by using a high voltage silicon-gate process. An epitaxial
layer prevents the latch-up associated with older CMOS
technologies. The 44V maximum voltage range permits
controlling 30VP-P signals when operating with ±15V power
supplies.
The sixteen switches are bilateral, equally matched f or AC or
bidirectional signals. The ON resistance variation with
analog signals is quite low over a ±5V analog input range.
Pinouts
Features
• ON-Resistance (Max). . . . . . . . . . . . . . . . . . . . . . . . 100Ω
• Low Power Consumption (PD) . . . . . . . . . . . . . . . <1.2mW
• Fast Transition Time (Max). . . . . . . . . . . . . . . . . . . . 300ns
• Low Charge Injection
• TTL, CMOS Compatible
• Single or Split Supply Operation
•Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Battery Operated Systems
• Data Acquisition
• Medical Instrumentation
• Hi-Rel Systems
• Communication Systems
• Automatic Test Equipment
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
V+
NC
NC
S
16
S
15
S
14
S
13
S
12
S
11
S
10
S
9
GND
NC
A
3
D
S
8
S
7
S
6
S
5
S
3
S
1
EN
A
0
A
1
A
2
V-
S
4
S
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
V+
D
B
NC
S
8B
S
7B
S
6B
S
5B
S
4B
S
3B
S
2B
S
1B
GND
NC
NC
D
A
S
8
A
S
7
A
S
6
A
S
5
A
S
3
A
S
1
A
EN
A
0
A
1
A
2
V-
S
4
A
S
2
A
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DG406 (PDIP, SOIC)
TOP VI EW DG407 (PDIP, SOIC)
TOP VIEW Ordering Information
PART
NUMBER PART
MARKING TEMP.
RANGE (°C) PACKAGE PKG.
DWG. #
DG406DJ DG406DJ -40 to 85 28 Ld PDIP E28.6
DG406DJZ
(See Note) DG406DJZ -40 to 85 28 Ld PDIP*
(Pb-free) E28.6
DG406DY DG406DY -40 to 85 28 Ld SOIC M28.3
DG406DY-T DG406DY 28 Ld SOIC Tape and Reel M28.3
DG406DYZ
(See Note) DG406DYZ -40 to 85 28 Ld SOIC
(Pb-free) M28.3
DG406DYZ-T
(See Note) DG406DYZ 28 Ld SOIC Tape and Reel
(Pb-free) M28.3
DG407DJ DG407DJ -40 to 85 28 Ld PDIP E28.6
DG407DJZ
(Note) DG407DJZ -40 to 85 28 Ld PDIP*
(Pb-free) E28.6
DG407DY DG407DY -40 to 85 28 Ld SOIC M28.3
DG407DYZ
(Note) DG407DYZ -40 to 85 28 Ld SOIC
(Pb-free) M28.3
*Pb-free PDIPs can be used for through hole wave solder processing only. They are
not intended for use in Reflow solder processing applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
Data Sheet March 13, 2006
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2000, 2003, 2004, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2FN3116.9
March 13, 2006
Schematic Dia gram (Typical Chan nel)
V+
GND
A0
AX
EN
V-
VREF
LEVEL
SHIFT DECODE/
DRIVE
V+
V+ V-
D
S1
SN
Functional Diagrams
DG406 DG407
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
D
TO DECODER LOGIC
CONTROLLING BOTH
TIERS OF MUXING
ADDRESS DECODER
1 OF 16 ENABLE
A0A1A2A3EN
S2A
S3A
S4A
S5A
S6A
S7A
S8A
S1B
S2B
S3B
S4B
S5B
S6B
S7B
S8B
DA
TO DECODER LOGIC
CONTROLLING BOTH
TIERS OF MUXING
ADDRESS DECODER
1 OF 8 ENABLE
A0A1A2EN
S1A
DB
DG406, DG407
3FN3116.9
March 13, 2006
DG406 TRUTH TABLE
A3A2A1A0EN ON SWITCH
XXXX0 None
00001 1
00011 2
00101 3
00111 4
01001 5
01011 6
01101 7
01111 8
10001 9
10011 10
10101 11
10111 12
11001 13
11011 14
11101 15
11111 16
DG407 TRUTH TABLE
A2A1A0EN ON SWITCH PAIR
XXX0 None
0001 1
0011 2
0101 3
0111 4
1001 5
1011 6
1101 7
1111 8
Logic “0” = VAL < 0.8V.
Logic “1” = VAH > 2.4V.
X = Don’t Care.
DG406, DG407
4FN3116.9
March 13, 2006
Absolute Maximum Ratings Thermal Info rmation
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44.0V
GND to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V
Digital Inputs, VS, VD (Note 1). . . . . . (V-) -2V to (V+) +2V or 20mA,
Whichever Occurs First
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA
P eak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . . . .100mA
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Resistance (Typical, Note1) θJA (oC/W)
PDIP Package*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(PLCC and SOIC - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditi ons above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. Signals on SX, DX, EN or AX exceeding V+ or V- are clamped by internal diodes. Limit diode current to maximum current ratings.
Electrical Specifications Test Conditions: V+ = +15V, V- = -15V, VAL = 0.8V, VAH = 2.4V Unless Otherwise Specified
PARAMETER TEST CONDITIONS TEMP (oC) (NOTE 3)
MIN (NOTE 4)
TYP (NOTE 3)
MAX UNITS
DYNAMIC CHARACTERISTICS
Transition Time, tTRANS (See Figure 1) 25 - 200 300 ns
Full - - 400 ns
Break-Before-Make Interval, tOPEN (See Figure 3) 25 25 50 - ns
Full 10 - - ns
Enable Turn-ON Time, tON(EN) (See Figure 2) 25 - 150 200 ns
Full - - 400 ns
Enable Turn-OFF Time, tOFF(EN) 25 - 70 150 ns
Full - - 300 ns
Charge Injection, Q CL = 1nF, VS = 0V, RS = 0Ω25 - 40 - pC
OFF Isolation, OIRR VEN = 0V, RL = 1kΩ,
f = 100kHz (Note 7) 25 - -69 - dB
Logic Input Capacitance, CIN f = 1MHz 25 - 7 - pF
Source OFF Capacitance, CS(OFF) VEN = 0V, VS = 0V,
f = 1MHz 25 - 8 - pF
Drain OFF Capacitance, CD(OFF) VEN = 0V, VD = 0V,
f = 1MHz
DG406 25 - 160 - pF
DG407 25 - 80 - pF
Drain ON Capacitance, CD(ON) VEN = 5V, VD = 0V,
f = 1MHz
DG406 25 - 180 - pF
DG407 25 - 90 - pF
DIGITAL INPUT CHARACTERISTICS
Logic High Input Voltage, VINH Full 2.4 - - V
Logic Low Input Voltage, VINL Full - - 0.8 V
Logic High Input Current, IAH VA = 2.4V, 15V Full -1 - 1 µA
Logic Low Input Current, IAL VEN = 0V, 2.4V, VA = 0V Full -1 - 1 µA
ANALOG SWITCH CHARACTERISTICS
Drain-Source ON Resistance, rDS(ON) VD = ±10V, IS = +10m A (Note 5) 25 - 50 100 Ω
Full - - 125 Ω
rDS(ON) Matching Between Channels,
∆rDS(ON) VD = 10V, -10V (Note 6) 25 - 5 - %
DG406, DG407
5FN3116.9
March 13, 2006
Source OFF Leakage Current, IS(OFF) VEN = 0V, VS = ±10V,
VD = +10V 25 -0.5 0.01 0.5 nA
Full -5 - 5 nA
Drain OFF Leakage Current, ID(OFF)
DG406 25 -1 0.04 1 nA
Full -40 - 40 nA
DG407 25 -1 0.04 1 nA
Full -20 - 20 nA
Drain ON Leakage Current, ID(ON) VS = VD = ±10V (Note 5)
DG406 25 -1 0.04 1 nA
Full -40 - 40 nA
DG407 25 -1 0.04 1 nA
Full -20 - 20 nA
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+ VEN = VA = 0V or 5V
(Standby) 25 - 13 30 µA
Full - - 75 µA
Negative Supply Current, I- 25 -1 -0.01 - µA
Full -10 - - µA
Positive Supply Current, I+ VEN = 2.4V, VA = 0V
(Enabled) 25 - 80 100 µA
Full - - 200 µA
Negative Supply Current, I- 25 -1 -0.01 - µA
Full -10 - - µA
Electrical Specifications Single Supply Test Conditions: V+ = 12V, V- = 0V, VAL = 0.8V, VAH = 2.4V,
Unless Otherwise Specified
PARAMETER TEST
CONDITIONS TEMP (oC) (NOTE 3)
MIN (NOTE 4)
TYP (NOTE 3)
MAX UNITS
DYNAMIC CHARACTERISTICS
Switching Time of
Multiplexer, tTRANS VS1 = 8V, VS8 = 0V,
VIN = 2.4V 25 - 300 450 ns
Enable Turn-ON Time, tON(EN) VINH = 2.4V, VINL = 0V,
VS1 = 5V 25 - 250 600 ns
Enable Turn-OFF Time,
tOFF(EN) 25 - 150 300 ns
Charge Injection, Q CL = 1nF, VS = 6V,
RS = 0Ω
25 - 20 - pC
Electrical Specifications Test Conditions: V+ = +15V, V- = -15V, VAL = 0.8V, VAH = 2.4V Unless Otherwise Specified (Continue d)
PARAMETER TEST CONDITIONS TEMP (oC) (NOTE 3)
MIN (NOTE 4)
TYP (NOTE 3)
MAX UNITS
DG406, DG407
6FN3116.9
March 13, 2006
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG Full 0 - 12 V
Drain-Source ON-Resistance,
rDS(ON) VD = 3V, 10V, IS = -1mA
(Note 5) 25 - 90 120 Ω
rDS(ON) Matching Between
Channels (Note 6), ∆rDS(ON) 25 - 5 - %
Source Off Leakage Current, IS(OFF) VEN = 0V, VD = 10V or 0.5V,
VS = 0.5V or 10V 25 - 0.01 - nA
Drain Off Leakage Current, ID(OFF)
DG406 25 - 0.04 - nA
DG407 25 - 0.04 - nA
Drain On Leakage Current, ID(ON) VS = VD = ±10V (Note 5)
DG406 25 - 0.04 - nA
DG407 25 - 0.04 - nA
POWER SUPPLY CHARACTERISTICS
Positive Supply Current (I+)
(Standby) VEN = 0V or 5V,
VA = 0V or 5V 25 - 13 30 µA
Full - 13 75 µA
Negative Supply Current (I-)
(Enabled) 25 -1 -0.01 - µA
Full -5 -0.01 - µA
NOTES:
3. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
4. Typical values are for Design Aid Only, not guaranteed nor production tested.
5. Sequence each switch ON.
6. ∆rDS(ON) = (rDS(ON)(Max) - rDS(ON)(Min)) ÷ rDS(ON) average.
7. Worst case isolation occurs on channel 8B due to proximity to the drain pin.
Test Circuits and W aveforms
FIGURE 1A. DG406 TEST CIRCUIT FIGURE 1B. DG407 TEST CIRCUIT
Electrical Specifications Single Supply Test Conditions: V+ = 12V, V- = 0V, VAL = 0.8V, VAH = 2.4V,
Unless Otherwise Specified (Continued)
PARAMETER TEST
CONDITIONS TEMP (oC) (NOTE 3)
MIN (NOTE 4)
TYP (NOTE 3)
MAX UNITS
EN
A3
DG406
GND
A2
A1
S1
S2 - S15
S16
D
V-
V+
±
±10V
VO
35pF300Ω50Ω
+15V
+2.4V
-15V
A0
10V
LOGIC
INPUT
EN
A0
DG407
GND
A1
A2
S1B
†
S8B
DB
V-
V+ ±10V
VO
35pF300Ω50Ω
+15V
+2.4V
-15V
† = S1A - S8A, S2B - S7B, DA
±
10V
LOGIC
INPUT
DG406, DG407
7FN3116.9
March 13, 2006
FIGURE 1C. MEASUREMENT POINTS
FIGURE 1. TRANSITION TIME
FIGURE 2A. DG406 TEST CIRCUIT FIGURE 2B. DG407 TEST CIRCUIT
FIGURE 2C. MEASUREMENT POINTS
FIGURE 2. ENABLE SWITCHING TIMES
FIGURE 3A. TEST CIRCUIT FIGURE 3B. MEASUREMENT POINTS
FIGURE 3. BREAK-BEFORE-MAKE INTERVAL
Test Circuits and W aveforms (Continued)
LOGIC
INPUT
SWITCH
OUTPUT
VO
3V
VS1B
50%
tr < 20ns
tf < 20ns
tTRANS
50%
0V
0V
VS8B
tTRANS S8 ON
80%
80%
S1 ON
VS8
VS1
EN
A3
DG406
GND
A2
A1
S1
S2 - S16
D
V-
V+ -5V
VO
35pF300Ω50Ω
+15V
-15V
A0
LOGIC
INPUT VIN EN
A0DG407
GND
A1
A2S1B
†
DA AND DB
V-
V+ -5V
VO
35pF300Ω50Ω
+15V
-15V
† = S1A - S8A, S2B - S8B, DA
LOGIC
INPUT VIN
LOGIC
INPUT
SWITCH
OUTPUT
VO
3V
VO
50%
tr < 20ns
tf < 20ns
tON(EN)
0V 50%
tOFF(EN)
90%
0V
VIN
VO
EN
A3 DG406
GND
A2
A1
ALL S
D,
V-
V+ +5V (VS)
VO
35pF300Ω50Ω
+15V
+2.4V
-15V
A0
DG407
AND DA
DB
LOGIC
INPUT
LOGIC
INPUT
SWITCH
OUTPUT
VO
3V
VS
tr < 20ns
tf < 20ns
tOPEN
0V
0V
80%
DG406, DG407
8FN3116.9
March 13, 2006
Typical Performance Curves
FIGURE 4. rDS(ON) vs VD AND SUPPLY FIGURE 5. rDS(ON) vs VD AND TEMPERATURE
FIGURE 6. rDS(ON) vs VD AND SUPPLY FIGURE 7. ID, IS LEAKAGE CURRENTS vs ANALOG VOLTAGE
FIGURE 8. ID, IS LEAKAGE vs TEMPERATURE FIGURE 9. SWITCHING TIMES vs BIPOLAR SUPPLIES
±5V
±8V
±10V
±12V
±15V
±20V
160
140
120
100
80
60
40
20
0
-20 -16 -12 -8 -4 0 4 8 12 16 20
VD, DRAIN VOLTAGE (V)
rDS(ON), ON RESISTANCE (Ω)
125oC
-40oC
-55oC
25oC
85oC
0oC
V+ = 15V
V- = -15V
80
70
60
50
40
30
20
10
0
-15 -10 -5 5 10015
VD, DRAIN VOLTAGE (V)
rDS(ON), ON-RESISTANCE (Ω)
V- = 0V
V+ = 7.5V
10V
12V
15V 20V 22V
240
200
160
120
80
40
0048121620
VD, DRAIN VOLTAGE (V)
rDS(ON), ON-RESISTANCE (Ω)
-10 -5 5 10015
VS, VD, SOURCE DRAIN VOLTAGE (V)
V+ = 15V, V- = -15V
VS = -VD FOR ID(OFF)
VD = VS(OPEN) FOR ID(ON)
IS(OFF)
DG406 ID(ON), ID(OFF)
-15
120
80
40
0
-40
-80
-120
ID, IS, CURRENT (pA)
DG407 ID(ON), ID(OFF)
V+ = 15V, V- = -15V
VS OR VD = ±10V
IS(OFF)
ID(ON), ID(OFF)
100nA
10nA
1nA
100pA
10pA
1pA
0.1pA
ID, IS, CURRENT (A)
-55 -35 -15 5 25 45 65 85 105 125
TEMPERATURE (oC)
350
300
250
200
150
100
50
05101520
VSUPPLY, SUPPLY VOLTAGE (±V)
TIME (ns)
tTRANS
tON(EN)
tOFF(EN)
DG406, DG407
9FN3116.9
March 13, 2006
FIGURE 10. SWITCHING TIMES vs SINGLE SUPPLY FIGURE 11. OFF ISOLATION vs FREQUENCY
FIGURE 12. SUPPLY CURRENTS vs SWITCHING FREQUENCY FIGURE 13. tON/tOFF vs TEMPERATURE
FIGURE 14. SWITCHING THRESHOLD vs SUPPLY VOLTAGE
Typical Performance Curves (Continued)
700
600
500
400
300
200
100
05101520
V+, SUPPLY VOLTAGE (V)
TIME (ns)
tTRANS
tON(EN)
tOFF(EN)
V- = 0V
1K 10K 1M100K 10M
f, FREQUENCY (Hz)
100
-140
-120
-100
-80
-60
-40
-20
ISOL (dB)
0
100 1K 100K 1M10K 10M
f, FREQUENCY (Hz)
EN = 5V, AX = 0V OR 5V
IGND
10
10
8
6
0
-4
-8
-10
I, CURRENT (mA)
I+
I-
4
2
-2
-6
300
280
260
240
220
200
140
120
60
-55 -35 -15 5 25 45 65 85 105 125
TEMPERATURE (oC)
TIME (ns)
180
160
100
80
tTRANS
tON(EN)
tOFF(EN)
V+ = 15V, V- = -15V
5101520
VSUPPLY, SUPPLY VOLTAGE (±V)
0
0
1
2
3
VA,(V)
DG406, DG407
10 FN3116.9
March 13, 2006
Die Characteristics
DIE DIMENSIONS:
2490µm x 4560µm x 485µm
METALLIZATION:
Type: SiAl
Thickness: 12kÅ ±1kÅ
PASSIVATION:
Type: Nitride
Thickness: 8kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
9.1 x 104 A/cm2
Metallization Mask Layout DG406
V-
S16
DNC V+
S5
A0EN
S7
S6
S5
S4
S3
S2
S1
A1
A2
A3
GND
S15
S14
S13
S12
S11
S10
S9
DG406, DG407
11 FN3116.9
March 13, 2006
DG406, DG407
Die Characteristics
DIE DIMENSIONS:
2490µm x 4560µm x 485µm
METALLIZATION:
Type: SiAl
Thickness: 12kÅ ±1kÅ
PASSIVATION:
Type: Nitride
Thickness: 8kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
9.1 x 104 A/cm2
Metallization Mask Layout DG407
A0ENA1
A2
NCGND
S8A
S7A
S6A
S5A
S4A
S3A
S2A
S1A
V-DA
DBV+
S8B
S7B
S6B
S5B
S4B
S3B
S2B
S1B
12 FN3116.9
March 13, 2006
DG406, DG407
Dual-In-Line Plastic Packages (PDIP)
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be perpendic-
ular to datum .
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
eA-C-
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 12 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1 Be
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AMBS
E28.6 (JEDEC MS-011-AB ISSUE B)
28 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.250 - 6.35 4
A1 0.015 - 0.39 - 4
A2 0.125 0.195 3.18 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.030 0.070 0.77 1.77 8
C 0.008 0.015 0.204 0.381 -
D 1.380 1.565 35.1 39.7 5
D1 0.005 - 0.13 - 5
E 0.600 0.625 15.24 15.87 6
E1 0.485 0.580 12.32 14.73 5
e 0.100 BSC 2.54 BSC -
eA0.600 BSC 15.24 BSC 6
eB- 0.700 - 17.78 7
L 0.115 0.200 2.93 5.08 4
N28 289
Rev. 1 12/00
13
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
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FN3116.9
March 13, 2006
DG406, DG407
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45o
C
H
µ
0.25(0.010) BM M
α
M28.3 (JEDEC MS-013-AE ISSUE C)
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.0200 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 -
D 0.6969 0.7125 17.70 18.10 3
E 0.2914 0.2992 7.40 7.60 4
e 0.05 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.01 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N28 287
α0o8o0o8o-
Rev. 0 12/93