C57401 C57401A C57402 C57402A 57401A 57402 57401 Military Standard FIFOs 64x4 64x5 Cascadable & Standalone Memory cl Advanced Micro Devices 57402A DISTINCTIVE CHARACTERISTICS e Choice of 7 or 10 MHz shift-out/shift-in rates * Choice of standalone or cascadable devices e Choice of 4-bit or 5-bit data width e TTL Inputs and outputs Cascadable devices readily expandable in the word and bit dimension Standalone devices expandable In the word dimension o nly Structured pinouts. Output pins directly oppo- site corresponding Inputs pins Asynchronous operation Dose rate (transient upset) junction-Isolated bipolar process 2x10" RADs (SI)/s recovery time of 50 to 70 js from a 1ps pulse Neutron fluence (permanent damage): 1x10" Nicm? GENERAL DESCRIPTION The C/57401/1A and C57402/2A are fall through high- speed First-In First-Out (FIFO) memories organized 64 words by 4 bits and 64 words by 5 bits respectively. FIFO word width and depth are expandable on cas- cadable devices. Standalone devices are expandable in word width only. Ordering Information PACKAGE MIL-M-38510 (CASCADABLE/ PART NUMBER | PINS | PACKAGE TYPE CASE OUTLINE | STANDALONE DESCRIPTION |) gp ote | Ceramic Dip D-2 Standalone | 57401* 16 os 7 MHz 64X4 FIFO CL 020 Leadless Chip Carrier C-2 Standalone CD 016 Ceramic Dip 0-2 Standalone 57401A* 16 |- aa Sena So fe aH 10 MHz 64X4 FIFO | CL 020 Leadless Chip Carrier C-2 Standalone CD018 | CeramicDip D6 | Standaone | | 57402 18 oe 7 MHz 64X5 FIFO CL 020 Leadiess Chip Carrier C-2 Standalone 7 CD018 | Ceramic Dip D-6 Standalone : _ 57402A 18 - - seen | 10MHz 64X5 FIFO CL 020 Leadless Chip Carrier C-2 Standalone CD016 | CeramicDip 0-2 Cascadable a | C57401* 16 -t..-. 7? MHz 64X4 FIFO CL 020 Leadless Chip Carrier C-2 | Cascadable 4 : cD ot Ceramic Dip D-6 Cascadable C57401A* 16 10 MHz 64X4 FIFO cL 020 Leadiess Chip Carrier C-2 Cascadable - CD 018 | Ceramic Dip D-6 Cascadable ee C57402 18 - 7 MHz 64X5 FIFO CL 020 Leadless Chip Carrier C-2 Cascadable | CD 018 Ceramic Dip D-6 Cascadable | | 57402A | 18 | -- =. we ef ..| 10 MHz 64X5 FIFO CL 020 Leadiass Chip Carrier C-2 Cascadabie | * Also available in Ceramic Flatpackage. Contact factory for detail. 505012 2-192 Publication # Rev. Amendment 11816 A 10 Issue Date: January 1989BLOCK DIAGRAMS DIP Pinout 57401 S7401A C57401 C57401A Oo 4 [7g Co pb 4 FIFO 62 X 4 BIT FIFO} 5* 01 +377) Nput | REGISTER output | 124 4, D2 _*] STAGE STAGE PU, Day 1g 3 Araby >| INPUT .| REGISTER output fe Burt SHIFT CONTROL F=N CONTROL CONTROL | 15 OUTPUT s Losic LOGIC Locic fy (N 3 +6 READY Le] l MASTER RESET 57402 57402A C57402 C574024 do 15 0, # FIFO FIFO 14 5 an} 62X5 BIT A [a O INPUT OUTPUT 2 be 8a] STAGE [>] ReEGsteR RK] Ske }2> 03 bi 1" O84 a) p>{ INPUT SHIFT READY 577 _ INPUT REGISTER OUTPUT FS GuT IFT CONTROL J CONTROL *] CONTROL OUTPUT SHI | Loic ] LoGic iN 3 Loic ria READY L ro [ it 506 127 MASTER RESET CONNECTION DIAGRAMS INPUT SHIFT READY OUT w NC Q he] Vcc NC NC VCC INPUT READY [2] 3] SHIFT OUT f|sf2}s jal SHIFTIN] gyggg 9 Fel outPuTReapy = SHIFTIN J 4 | 118 | NC eur ST401A Dols 87401 17 ool] Sitar = f Pt Brac LIT | READY Dis} es74ota = fr} 01 Di} 6 87401 16 } 00 DATA OUTPUTS i es7a01a [J IN} be EE oi 02 D217 15101 03 7 fro] 03 NCI a 14]02 Gnp LB] [e] MASTER RESET 9 [10/11] 2]19[ 7 D3GND MR O39 NC INPUT SHIFT VV READY OUT nc (J fia] vec NG NCVCC INPUT READY [2] fa] SHIFT OUT a [2] 1 [20] 19 SHIFT IN [By fs] OUTPUT READY = SHIFTIN | 4 | [18 | READY co} sz402 3] 00 Do] 5 | 57402 | 17 | 00 57402 87402A OL] Careoa flo DiJ6 | esrac2 =| 16 | 01 DATA J zfs] 87402A FF) op | outputs pel? 57402A slo2 o3 GI fa] os pa} 8 14] 03 oa[e] fi] O4 \ 9 | 10] 11] 12/19 np [] fo] MASTER RESE D4 GND MR O4 NC 505 129 CS7401/A = C57402/A 57401/A 574 02/A 2-193ABSOLUTE MAXIMUM RATINGS Supply voltage, Vag .scscesesessceeseeteseeneeneenenseense O5Vto7V Input Voltage o.oo. cess escnceteteersecerscteseeeees -15Vto7V Off-state OUtpUt VOHAgO 0... ee eeteeteeeee O05 Vto5.5V Storage Temperature... cee renee 65C ta +150C OPERATING CONDITIONS 57401/2 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is 4 stress rating only, and a functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Expo- sure to absolute maximum rating conditions for extended periods of time may affect reliability. Absolute maximum ratings are for system design reference; parameters given are not tested. Military Symbol Parameter Figure Min Typ Max Unit Vee Supply voltage 45 5 5.5 Vv T,* Operating temperature _| 73s 125 C ten Shift in HIGH time 1 45 ns ten Shitt in LOW time 1 45 ns los Input data setup 1 10 ns tow Input data hold time 1 55 ns fin Shift in rate 1 MHz four Shift Out rate 4 7 MHz toon! Shift Out HIGH time 4 45 ns teor Shift Out LOW time 4 45 ns tunw Master Reset pulset 8 30 ns tus. Master Reset to SI 8 ae 45 ns * Instant-On Case Temperature ** tas iS measured on initial characterization lots only and is not directly tested in production. SWITCHING CHARACTERISITCS 57401/2 Over Operating Conditions Military Symbol Parameter Figure Min Max Unit tat Shift In to Input Ready LOW 1 60 ns tant Shift In to input Ready HIGH 1 60 ns toa | Shift Out to Output Ready LOW 4 6 | | , toan! Shift Out to Output Ready HIGH 4 70 ns | toon Output Data Hold (previous word) 4 10 ns tons Output Data Shift (next ward) 4 65 ns tor Data throughput or fall through 3,6 4 ps turort Master Reset to OR LOW 8 65 ns turiRH Master Reset to 1R HIGH 8 65 ns te Input Ready pulse HIGH 3 20 ns top Output Ready pulse HIGH 6 20 | ns t See AC test and high speed application note. 1PH tip, and t,,,, are measured on initial characterization lots only and are not directly tested in production. 2-194 C57401/A C57402/A 57401/A 57402/AABSOLUTE MAXIMUM RATINGS Supplyvoltage, Veg veccccsesssecersssenseesensenrents O5Vto7V Input voltage octet ED V to 7 V Off state output Voltage oo... ees eeeneeereee O05 Vt05.5V Storage temperature we 65C to +150C OPERATING CONDITIONS 57401A/2A Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is 4 stress rating only, and a functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Expo- sure to absolute maximum rating conditions for extended periods of time may affect reliability. Absolute maximum ratings are for system design reference; parameters given are not tasted. + Military Symbol Parameter Figure Min Typ Max Unit Vo Supply voltage 45 5 5.5 Vv T, Operating temperature -55 125 C tou? Shift in HIGH time 1 35 ns | tea. Shift in LOW time 1 35 ns ting Input data setup 1 5 ns ton Input data hold time 1 45 ns Lofty Shift in rate 1 10 MHz fou | Shift Out rate 4 10 MHz | tyont Shift Out HIGH time 4 35 ns teow Shift Out LOW time 4 35 ns twaw Master Reset pulse 8 40 ns = Master Reset to Si 8 45 { ns * Instant-On Case Temperature a tuas ig measured on initial characterization lots only and is not directly tested in production. SWITCHING CHARACTERISTICS 57401A/2A Over Operating Conditions Military Symbol Parameter Figure Min Max Unit tat Shift In to Input Ready LOW 1 50 ns hay Shift In to Input Ready HIGH 1 50 a toa Shift Out to Output Ready LOW 4 65 ns , lors Shift Out to Output Ready HIGH 4 65 ns toon Output Data Hold (previous word) 4 10 ns | tops Output Data Shift (next word) 4 60 ns | ter Data throughput or fall through 3,6 2.2 us tusort Master Reset to OR LOW 8 65 ns turian Master Reset to IR HIGH 8 65 ns teu 1 Input Ready pulse HIGH 3 | 20 ns om , Output Ready pulse HIGH _ 6 20 ns t+ See AC test and high speed application note. * toy and top, are measured on initial characterization lots only and are not directly tested in production. C57401/A C57402/A = S7401/A ss S7A02/A 2-195ABSOLUTE MAXIMUM RATINGS Supply voltage, Vig. -sscsscsssssessesescsssenseeeeesees O5VtI07V Input voltage ............. 1S VIO7V Off state output voltage . 0.5 V to 5.5 V Storage temperature oo... eccsecseersnenees -65C to +150C OPERATING CONDITIONS cs7a01/2 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and a functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Expo- sure to absolute maximum rating conditions for extended periods of time may affect reliability. Absolute maximum ratings are for system design reference; parameters given are not tested. Military Symbol Parameter Figure Min Typ Max Unit Voc Supply voltage 45 5 5.5 v T, Operating temperature 55 125 C ten? Shift in HIGH time 1 45 ns ter Shift in LOW time 1 45 ns tos Input data setup 1 0 ns how Input data hold time 1 55 ns fin Shift in rate 1 7 MHz four Shift Out rate 4 7 MHz teout Shift Out HIGH time 4 45 ns sot Shift Out LOW time 4 45 ns tunw Master Reset pulset 8 30 ns L turns Master Reset to S| 8 45 ns * Instant-On Case Temperature ** tag (8 Measured on initial characterization lots only and is not directly tested in production. SWITCHING CHARACTERISTICS 57401/2 Over Operating Conditions Military Symbol! Parameter Figure Min Max Unit fat Shift In to Input Ready LOW 1 60 ns tru? Shift In to Input Ready HIGH 1 60 ns ton Shift Out to Output Ready LOW 4 65 ns tonu! Shift Out to Output Ready HIGH 4 70 ns toon Output Data Hold (previous word) 4 10 ns tons Output Data Shift (next word) 4 65 ns ty Data throughput or fall through 3, 6 4 ys turort Master Reset to OR LOW 8 65 ns tuninn Master Reset to IR HIGH 8 65 ns tow Input Ready pulse HIGH 3 30 ns topy Output Ready pulse HIGH 6 30 ns +t See AC test and high speed application note. * This parameter characterization plies to FIFOs communicating with each other in a cascaded mode. t,,,, and t,,, are measured on initial its only and are not directly tested in production. 2-196 C57401/A C57402/A S7401/A S7402/AABSOLUTE MAXIMUM RATINGS Supply voltage, Vag csscesesssessesrsessssssseetenesssseense ~O5ViI07V Input voltage ............. -1.5Vto7V Off-state output voltage .0.5Vto5.5V Storage temperature... senses 65C to +150C OPERATING CONDITIONS c57401A4/2A Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and a functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Expo- sure to absolute maximum rating conditions for extended periods of time may affect reliability. Absolute maximum ratings are for system design reference; parameters given are not tested. Military Symbol Parameter Figure Min Typ Max Unit Voc Supply voltage 45 5 5.5 Vv T, Operating temperature -55 125 C ten! Shift in HIGH time 1 35 ns ter Shift in LOW time 1 35 ns tog Input data setup 1 0 ns ton Input data hold time 1 45 ns Fin Shift in rate 1 10 MHz Four Shift Out rate 4 10 MHz teou? Shift Out HIGH time 4 35 ns tear Shift Out LOW time 4 35 ns tarw Master Reset pulse 8 40 ns tars Master Reset to S] 8 45 ns * Instant-On Case Temperatura ** tung iS measured on initial characterization lots only and is not directly tested in production. SWITCHING CHARACTERISTICS 57401A/2A Over Operating Conditions Military Symbol Parameter Figure Min Max Unit ta Shift In to Input Ready LOW 1 50 ns tant Shift In to Input Ready HIGH 1 50 ns ton! Shift Out to Output Ready LOW 4 65 ns torn? Shift Out to Output Ready HIGH 4 65 ns top Output Data Hold (previous word) 4 10 ns - tons Output Data Shift (next word) 4 60 ns toy Data throughput or fall through 3,6 2.2 us twroaL Master Reset to OR LOW 8 65 ns tyrire Master Reset to IR HIGH 8 65 ns tien Input Ready pulse HIGH 3 30 ns tory Output Ready pulse HIGH 6 30 ns +t See AC test and high speed application note. * This parameter applies to FIFOs communicating with each other in a cascaded mode. t,,, andt,,, are measured on initial characterization lots only and are not directly tested in production. CS7401/A C57402/A 2-197 57401/A 57402/ATEST LOAD FOR ALL DEVICES BV Input pulse 0 to 3 V. 560.9 Input Rise and Fall Time (10%-90%). 5 ns minimum. TEST POINT* Measurements made at 1.5 V. 1.4KQ 2290 pF 505 193 * The TEST POINT? is driven by the output under test, and observed by instrumentation. DC CHARACTERISTICS Over Operating Conditions For all Devices | Symbol Parameter Test Conditions Min Typ Max Unit | Vi Low-level input voltage ost | V Vin High-level input voltage at Vv Vic Input clamp voltage Veco = MIN =-18 mA -15 Vv hay D,-0,, MR -0.8 | mA an Low-level input current SISO Veg = MAX V, = 0.45 V 16 | mA ha High-level input current Vog = MAX V,=2.4V 50 | pA i Maximum input current Veg * MAX V,=5.5V 1 | ma | on Low-level output voltage Voc = MIN Ig, 2 8mA 05 on High-level output voltage Voc = MIN low = 0.9 MA 2.4 log Output short-circuit current* Vocg = MAX Vo20V 20 -90 | mA 57401 160 5S7401A 180 leg Supply current Veg * MAX 7402 180 | mA 7402A 200 Inputs low, 57401 160 outputs open. C57401A 180 057402 180 C57402A 200 * Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. 1 V, and V,,, are input conditions of output tests and are not themselves directly tested. V,, and V,,, are absolute voltages with respect to device ground and include all overshoots due to system and/or tester noise. Do not attempt to test these values without suitable equipment. CS7401/A C57402/A S7401/A S7402/AFUNCTIONAL DESCRIPTION Data Input Atter power up the Master Reset is pulsed low (Fig 8) to prepare the FIFO to accept data in the first location. When Input Ready (IR) is HIGH the location is ready to accept data from the D, inputs. Data then present at the data inputs is entered into the first location when the Shift-In (SI) is brought HIGH. A SI HIGH signal causes the IR to go LOW. Data remains at the first location until SI is brought low. When SI is brought LOW and the FIFO is not full, IR will go HIGH, indicating that more room is available. Simultaneously, data will propagate to the second location and continue shifting until it reaches the output stage or a full location. The first word is present at the outputs before a Shift-Out is applied. If the memory is full, IR will remain LOW. Data Transfer Once data is entered into the second cell, the transfer of any full cell to the adjacent (downstream) empty cell is automatic, activated by an on-chip control. Thus data will stack up at the end of the device while empty locations will bubble to the front. t,, defines the time required for the first data to travel from input to the output of a previously empty device. Data Output Data is read from the O, outputs. When data is shifted fo the output stage, Output Ready (OR) goes HIGH, indicating the presence of valid data. When the OR is HIGH, data may be shifted out by bringing the Shift Out (SO) HIGH. A HIGH signal at SO causes the OR to go LOW. Valid data is maintained while the SO is HIGH. When SO is brought LOW the upstream data, provided that stage has valid data, is shifted to the output stage. When new valid data is shifted to the output stage, OR goes HIGH. if the FIFO is emptied, OR stays LOW, and O, remains as before (i.e. data does not change if FIFO is empty). Input Ready and Output Ready may also be used as status signals indicating that the FIFO is completely full (Input Ready stays LOW for at least t,,) or completely empty (Output Ready stays LOW for at least t,,). AC Test and High Speed App. Notes Since the FIFO is a very-high-speed device, care must be exercised in the design of the hardware and the timing utilized within the design. The internal shift rate of the FIFO typically exceeds 20 MHz in operation. Device grounding and decoupling is crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitance and/or poor supply decoupling and grounding. We recom- mend a monolithic ceramic capacitor of 0.1 uF directly between V,,. and GND with very short lead length. In addition, care must be exercised in how the timing is set up and how the parameters are measured. For ex- ample, since an AND gate function is associated with both the Shift-In-Input Ready combination, as well as the Shift-Out-Output Ready combination, timing meas- urements may be misleading, i.e. rising edge of the Shift-In pulse is not recognized until Input-Ready is High. If Input-Ready is not high due to too high a fre- quency or FIFO being full or affected by Master Reset, the Shift-In activity will be ignored. This will affect the device from a functional standpoint, and will also cause the effective timing of Input Data Time (t,,,,) and the next activity of the Input Ready (t,,,) to be extended re- lative to Shift In going High. This same type of problem is also related to tia, tog, ANd tog, aS related to Shift-Out. LIFE TEST/ BURN-IN CIRCUITS Military Burn-in Military burn-in is in accordance with the current revision of MIL-STD-883. Test method 1015, conditions A through E. Test conditions are selected at AMD's option. Dynamic Burn-in Circuitry 57401 57402 5S7401A ST402A 57401 C57402 CS7401A C57402A 3 4 5 6 7 3 SOND AW T snbient = 125C Voce = 5.25 + 0.25 V Square wave pulses on A, to A, are: 50% + 15% duty cycle Logic 0 = -1V to 0.7V Logic 1" = 2.4 VtoV,, Frequency of each address is to be one-half of each preceding input, with A, beginning at 100 kHZ. @.9., A, = 100 KHz A, = 50 kHz + 10% A, = 25 kHz + 10% A, = 1/2 A_, + 10%, etc. On = C57401/A C87402/A 2-199 57401/A 57402/Atit t Win i a INPUT READY PY OS URL INPUT DATA }+ to >) | {~- tips l ! Figure 1. Input Timing SHIFT IN eo LD _ OQ worn IRR sane YX XXX RE RR KKK KARR EKER KKH Input Ready HIGH indicates space is available and a Shift-In pulse may be applied. Input Data is loaded into the first word. Input Ready goes LOW indicating the first word is full. The Data from the first word is released for fall-through to second word. The Data from the first word is transferred to second word. The first word is now empty as indicated by Input Ready HIGH. 5B. If the second word is already full then the Data remains at the first word. Since the FIFO is now full InputReady remains low. Note: Shift in pulses appliad while input Ready is LOW will be ignored (See Figure 3). INPUT READY 605 137 ga Pron = Figure 2. The Mechanism of Shifting Data into the FIFO SHIFT OUT SHIFT IN /f i? INPUT READY _ }+____ r__ 2s, Nes >" weuroxe. XSXXXRKRXXNRKKXKXKKKKN scone UXKXKKKK FIFO is initially full. 508 138 Shift Out pulse is applied. An empty location starts bubbling to the front. Shift in is held HIGH. As soon as Input Ready becomes HIGH the input Data is loaded into the first word. The Data from the first word is released for fall through to second word. OPaons Figure 3. Data Is Shifted In Whenever Shift In and input Ready Are Both HIGH 2-200 C57401/A C57402/A 57401/A 57402/Aout our SHIFT OUT ee r \ Torr OUTPUT READY \ / toa. t [* tops ODH ~y OUTPUT DATA | A-DATA | B-DATA | C-DATA "oO | | 505 139 1. The diagram assumes that at this time words 63, 62, 61 are loaded with A, B, C Data, respectively. 2. Data is shifted out when Shift Out makes a HIGH to LOW transition. Figure 4. Output Timing SHIFT OUT \o OUTPLT READY Na) * By OUTPUT DATA A-DATA 505 140 1. Output Ready HIGH indicates that data is available and a Shift-Out pulse may be applied. 2. Shift-Out goes HIGH causing the next step. 3. Output ready goes LOW. 4. Contents of word 62 (B-DATA) is released for fall-through to word 63. SA. Output ready goes HIGH indicating that new data (B) is now available at the FIFO outputs. 5B. If the FIFO has only one word loaded (A-DATA) then Output Ready stays LOW and the A-DATA remains unchanged at the outputs. Note: Shift Out pulses applied when Output Ready is LOW will be ignored (Figure 7). Figure 5. The Mechanism of Shifting Data Out of the FIFO C57401/A C57402/A S7401/A 57402/A 2-201SHIFT IN SHIFT OUT FI pr OUTPUT READY LP / 1. FIFO initially empty. 806 141 Figure 6. t,, and t,.,, Specification SHIFT OUT \e OUTPUT READY a *O 2 AMAL our oxTA y DATA YYXXXXXXKK 505 142 1. Word 63 is empty. 2. New data (A) arrives at the outputs (word 63). 3. Output Ready goes HIGH indicating arrival of new data. 4. Since Shift Out is hald HIGH. Output Ready goes immediately LOW. 5. As soon as Shift Out goes LOW the Output Data is subject to change as shown by the dashed line on Output Ready. Figure 7. Data is Shifted Out Whenever Shift Out and Output Ready Are Both HIGH ______ p+__tmMaw ___+ MASTER RESET 7 V {MAIR INPUT READY F \ SO Is | tyroAL OUTPUT READY x turns SHIFT IN > 905 143 1. FIFO initially full. Figure 8. Master Reset Timing 2-202 C57401/A -CB7402/A S7401/A 57402/AINPUT READY <1IR so ir SO;f* SHIFT OUT SHIFT IN| * SI oA 7) OR;-* OUTPUT READY Do Qo Do Qo}+-e ~9 Dy Q1 Oy Q1;-e DATA IN De Q2 De Q2 Jou IN aDs _ Qs 03 __ Q3-> MA MR MASTER RESET oj} 505 144 Figure 9. Cascading FIFOs to Form 128X4 FIFO with C57401/A Cascadable FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the FIFOs themselves. IR so IR so IR so SHIFT OUT - Sl On SI OR Sl OR Do Qo Do Qo De Qofr 701 Qs Di Q1 Dt aie 1 D2 Qa De Q2 De Q2;- 03 __ Qs Os __ Q3 Da _. Qs3/- MA MR MR COMPOSITE INPUT IR so 1A so IR sor COMPOSITE READY -| SI OA ey) OR sl OR OUTPUT 00 Qo Do Qo Do Qo - READY 04 Qi D1 Qi D1 Qi - 702 Q2 02 Q2 De Q2-- j03 __ Q3 O03 __ Q3 Oa __ Q3fF- MR MR MR In $o A so iR sore SHIFT IN SI OR $i OA SI OR ~1Do Qo Do Qo Do Qol 701 Qi Di Q1 Dy Qir- Dz Q2 De Q2 Da Q2r- 03 __ a3 Da __ Qs Oa __ Q3aPr MR MA MA I I l MASTER RESET Figure 10. 192X12 FIFO with C57401/A 508 145 Cascadable FIFOs are expandable in depth and width. However, in forming wider words two external gates are required to generate composite Input and Output Ready flags. This need is due to the different fall-thraugh times of the FIFOs. C57401/A - C57402/A 57401V/A S7402/A 2-203