TDA19997HL Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer Rev. 02 -- 22 December 2009 Product data sheet 1. General description The High-Definition Multimedia Interface (HDMI) switch enables connection of multiple DVI/HDMI inputs to a receiver with at least one input. The TDA19997HL is a switch with four HDMI 1.4 compliant DVI/HDMI inputs and one DVI/HDMI output. Each HDMI input has its own dedicated embedded EDID memory. A fifth DDC-bus input is available for VGA or second HDMI input of SoC. The built-in auto-adaptive equalizer improves signal quality, allowing the use of cable lengths up to 30 m. The TDA19997HL supports Deep Color mode in 10-bit and 12-bit per channel up to 1920 x 1080p at 50/60 Hz. The TDA19997HL supports DVI/HDMI streams with or without High-bandwidth Digital Content Protection (HDCP 1.3) and all Data Island packets. The TDA19997HL settings are controllable via the I2C-bus. 2. Features Complies with the HDMI 1.4, DVI 1.0, EIA/CEA-861D and HDCP 1.3 standards Four independent DVI/HDMI inputs, up to 2.25 gigasamples per second Pin compatible with TDA9996/TDA9995 Robust auto-adaptive equalizer (up to 20 m AWG26 at 2.25 Gbit/s) Robust auto-adaptive equalizer (up to 30 m AWG24 at 1.5 Gbit/s) Integrated 50 single-ended termination resistors +5 V signal detection for each HDMI input Supports color depth processing at 24-bit, 30-bit or 36-bit per pixel Supports all Data Island packets Activity detection on each input, manages output activity and power consumption Extended mode: re-generate output TMDS waveform removing jitter and skew Frequency measurement allowing direct reading of format/resolution Automatic mode for main features: Automatic Hot Plug Detect (HPD) generation and termination resistors management Automatic HPD generation with programmable duration Automatic EDID load Display Data Channel (DDC) bus: 5 V tolerant, DDC-bus inputs with bit rates up to 400 kbit/s One DDC-bus output with the same latency as the HDMI stream pipeline delay DDC-bus master switch functionality avoids bus corruption TDA19997HL NXP Semiconductors Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer DDC-bus level-shifting buffer with digital lock-up protection A fifth DDC-bus input available for VGA or second HDMI input of SoC I2C-bus controllable at bit rates up to 400 kbit/s Non-volatile memory for switch management (Hot Plug Detect, Power-down) Non-volatile storage for EDID's allowing easy loading Embedded Extended Display Identification Data (EDID) memory: 253-byte shared and 3-byte of dedicated EDID memory per HDMI input Non-volatile memory for programming default EDID content Supports sources without +5 V 5 embedded EDID memory supplied by +5 V from HDMI source An extra 128-byte blocks for DVI or PC formats EDID update by I2C-bus, example for AVR applications Fail-safe output in Idle mode Mute pin preventing from pop noise/image noise ATC/Rx compliant for 36-bit Deep Color 1080p 60 Hz ATC/Tx eye diagram compliant for 36-bit Deep color 1080p 60 Hz Programmable slave address for easy cascade approach Ready for HDMI Audio return Channel (HDMI 1.4 features refer to AN907) 3.3 V and 1.8 V power supplies Additional ESD protection pin for CEC line ESD protection: HBM: class 2 MM: class B FCDM: class IV IEC 61000-4-2 class 3 for HDMI inputs Power-down mode with dedicated pin CMOS process Lead (Pb) free LQFP100 14 x 14 x 1 mm package, pitch 0.5 mm 3. Applications HDTV (plasma, Rear projection TV and LCD TV) YCbCr or RGB Hi-Speed video digitizer Projector Home theater AVR Switch box TDA19997HL_2 Product data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 02 -- 22 December 2009 2 of 26 TDA19997HL NXP Semiconductors Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer 4. Quick reference data Table 1. Symbol Quick reference data Parameter Conditions Min Typ Max Unit HDMI input pins: RXx_D0+, RXx_D0-, RXx_D1+, RXx_D1-, RXx_D2+, RXx_D2-, RXx_HPD, RXx_5V, RXy_DDC_DAT, RXy_DDC_CLK, CEC[1][2] VESD electrostatic discharge voltage IEC 61000-4-2 class 3 (contact discharge) 7 - - kV HDMI pins: OUT_D0-, OUT_D0+, OUT_D1-, OUT_D1+, OUT_D2-, OUT_D2+, RXx_D0+, RXx_D0-, RXx_D1+, RXx_D1-, RXx_D2+, RXx_D2-[1] fmax maximum frequency 2.25 - - GHz VDDH(3V3) HDMI supply voltage (3.3 V) 3.13 3.3 3.47 V VDDH(1V8) HDMI supply voltage (1.8 V) 1.65 1.8 1.95 V VDDS(3V3) supervisor supply voltage (3.3 V) 3.0 3.3 3.6 V VDDDC(1V8) core digital supply voltage (1.8 V) 1.65 1.8 1.95 V Supplies [1] x = A, B, C, D. [2] y = A, B, C, D, E. 5. Ordering information Table 2. Ordering information Type number TDA19997HL Maximum data rate per channel Package Name Description Version 2.25 gigasamples per second LQFP100 plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1 TDA19997HL_2 Product data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 02 -- 22 December 2009 3 of 26 TDA19997HL NXP Semiconductors Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer 6. Block diagram VDDH(3V3) TDA19997 VDDH(1V8) RXA_C+ RXA_C- RXA_D0+ EQ RXA_D0- RXA_D1+ OUT_C+ OUT_C- EQ RXA_D1- RXA_D2+ EQ RXA_D2- RXB_C+ RXB_C- RXB_D0+ RXB_D0- RXB_D1+ RXB_D1- RXB_D2+ RXB_D2- RT AND EQ RXC_C+ RXC_C- RXC_D0+ RXC_D0- RXC_D1+ RXC_D1- RXC_D2+ RXC_D2- RT AND EQ RXD_C+ RXD_C- RXD_D0+ RXD_D0- RXD_D1+ RXD_D1- RXD_D2+ RXD_D2- RT AND EQ OUT_D0+ OUT_D0- HDMI SWITCH OUT_D1+ OUT_D1- OUT_D2+ OUT_D2- I2C-BUS RXA_5V RXA_HPD RXA_DDC_DAT RXA_DDC_CLK RXB_5V RXB_HPD RXB_DDC_DAT RXB_DDC_CLK RXC_5V RXC_HPD RXC_DDC_DAT RXC_DDC_CLK RXD_5V RXD_HPD RXD_DDC_DAT RXD_DDC_CLK INTERRUPT HP_BIAS I2C_SDA I2C_SCL INT_N/MUTE EDID CONTROL OSCILLATOR HP_BIAS DDC BUFFER MASTER SWITCH HP_BIAS OUT_DDC OUT_DDC_DAT OUT_DDC_CLK HP_BIAS REGULATOR AUX_5V RXE_DDC_DAT RXE_DDC_CLK Fig 1. 001aak370 Block diagram TDA19997HL_2 Product data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 02 -- 22 December 2009 4 of 26 TDA19997HL NXP Semiconductors Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer 7. Pinning information 76 100 7.1 Pinning 1 75 TDA19997 Fig 2. 50 51 26 25 001aak372 Pin configuration 7.2 Pin description Table 3. Pin description Symbol Pin Type[1] Description VSS 1 G ground OUT_C+ 2 O HDMI output positive clock channel OUT_C- 3 O HDMI output negative clock channel VDDO(3V3) 4 P output supply voltage; 3.3 V OUT_DDC_CLK 5 O DDC-bus clock output; open-drain; 5 V tolerant OUT_DDC_DAT 6 I/O DDC-bus data input/output; open-drain; 5 V tolerant VSS 7 G ground VDDDC(1V8) 8 P digital core supply voltage; 1.8 V RXA_HPD 9 O HDMI output A Hot Plug Detect; 5 V tolerant RXA_5V 10 I input A HDMI +5 V RXA_DDC_DAT 11 I/O HDMI input/output A DDC-bus serial data; open-drain; 5 V tolerant RXA_DDC_CLK 12 I HDMI input A DDC-bus serial clock; open-drain; 5 V tolerant RXA_C- 13 I HDMI input A negative clock channel RXA_C+ 14 I HDMI input A positive clock channel VDDH(3V3) 15 P HDMI input A supply voltage; 3.3 V RXA_D0- 16 I HDMI input A negative data channel 0 RXA_D0+ 17 I HDMI input A positive data channel 0 VSS 18 G ground RXA_D1- 19 I HDMI input A negative data channel 1 RXA_D1+ 20 I HDMI input A positive data channel 1 VDDH(3V3) 21 P HDMI input A supply voltage; 3.3 V RXA_D2- 22 I HDMI input A negative data channel 2 TDA19997HL_2 Product data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 02 -- 22 December 2009 5 of 26 TDA19997HL NXP Semiconductors Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer Table 3. Pin description ...continued Symbol Pin Type[1] Description RXA_D2+ 23 I HDMI input A positive data channel 2 VDDH(1V8) 24 P HDMI core supply voltage; 1.8 V AUX_5V 25 I auxiliary input; 5 V VSS 26 G ground TEST1 27 I reserved for test (connect to ground) RXB_HPD 28 O HDMI output B Hot Plug Detect; 5 V tolerant RXB_5V 29 I input B HDMI +5 V RXB_DDC_DAT 30 I/O HDMI input/output B DDC-bus serial data; open-drain; 5 V tolerant RXB_DDC_CLK 31 I HDMI input B DDC-bus serial clock; open-drain; 5 V tolerant RXB_C- 32 I HDMI input B negative clock channel RXB_C+ 33 I HDMI input B positive clock channel VDDH(3V3) 34 P HDMI input B supply voltage; 3.3 V RXB_D0- 35 I HDMI input B negative data channel 0 RXB_D0+ 36 I HDMI input B positive data channel 0 VSS 37 G ground RXB_D1- 38 I HDMI input B negative data channel 1 RXB_D1+ 39 I HDMI input B positive data channel 1 VDDH(3V3) 40 P HDMI input B supply voltage; 3.3 V RXB_D2- 41 I HDMI input B negative data channel 2 RXB_D2+ 42 I HDMI input B positive data channel 2 VSS 43 G ground CDEC_DDC 44 VDDDC(1V8) 45 P digital core supply voltage; 1.8 V VDDDC(3V3) 46 P digital core supply voltage; 3.3 V TEST2 47 I reserved for test (connect to ground) PD 48 I power-down control input; active HIGH I2C_SDA 49 O I2C-bus output serial data I2C_SCL 50 I I2C-bus serial clock RXE_DDC_CLK 51 I Additional input DDC-bus serial clock; open-drain; 5 V tolerant RXE_DDC_DAT 52 I/O Additional input/output DDC-bus serial data; open-drain; 5 V tolerant INT_N/MUTE 53 O interrupt request for I2C-bus mode or 5 V detection CDEC_STBY 54 VDDS(3V3) 55 P supervisor supply voltage; 3.3 V VSS 56 G ground CEC 57 RXC_HPD 58 I HDMI input C Hot Plug Detect; 5 V tolerant RXC_5V 59 I input C HDMI +5 V RXC_DDC_DAT 60 I/O HDMI input/output C DDC-bus serial data; open-drain; 5 V tolerant internal supply voltage regulator decoupling capacitor; 1.8 V MUTE output pin internal supply voltage regulator decoupling capacitor; 1.8 V 8 kV System level ESD protection TDA19997HL_2 Product data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 02 -- 22 December 2009 6 of 26 TDA19997HL NXP Semiconductors Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer Table 3. Pin description ...continued Symbol Pin Type[1] Description RXC_DDC_CLK 61 I HDMI input C DDC-bus serial clock; open-drain; 5 V tolerant RXC_C- 62 I HDMI input C negative clock channel RXC_C+ 63 I HDMI input C positive clock channel VDDH(3V3) 64 P HDMI input C supply voltage; 3.3 V RXC_D0- 65 I HDMI input C negative data channel 0 RXC_D0+ 66 I HDMI input C positive data channel 0 VSS 67 G ground RXC_D1- 68 I HDMI input C negative data channel 1 RXC_D1+ 69 I HDMI input C positive data channel 1 VDDH(3V3) 70 P HDMI input C supply voltage; 3.3 V RXC_D2- 71 I HDMI input C negative data channel 2 RXC_D2+ 72 I HDMI input C positive data channel 2 VSS 73 G ground R12K 74 I termination resistor control VDDH(1V8) 75 P HDMI core supply voltage; 1.8 V RXD_HPD 76 O HDMI output D Hot Plug Detect; 5 V tolerant RXD_5V 77 I input D HDMI +5 V RXD_DDC_DAT 78 I/O HDMI input/output D DDC-bus serial data; open-drain; 5 V tolerant RXD_DDC_CLK 79 I HDMI input D DDC-bus serial clock; open-drain; 5 V tolerant RXD_C- 80 I HDMI input D negative clock channel RXD_C+ 81 I HDMI input D positive clock channel VDDH(3V3) 82 P HDMI input D supply voltage; 3.3 V RXD_D0- 83 I HDMI input D negative data channel 0 RXD_D0+ 84 I HDMI input D positive data channel 0 VSS 85 G ground RXD_D1- 86 I HDMI input D negative data channel 1 RXD_D1+ 87 I HDMI input D positive data channel 1 VDDH(3V3) 88 P HDMI input D supply voltage; 3.3 V RXD_D2- 89 I HDMI input D negative data channel 2 RXD_D2+ 90 I HDMI input D positive data channel 2 VDDDC(1V8) 91 P digital core supply voltage; 1.8 V VSS 92 G ground OUT_D2+ 93 O HDMI output positive data channel 2 OUT_D2- 94 O HDMI output negative data channel 2 VDDO(1V8) 95 P output supply voltage; 1.8 V OUT_D1+ 96 O HDMI output positive data channel 1 OUT_D1- 97 O HDMI output negative data channel 1 VSS 98 G ground OUT_D0+ 99 O HDMI output positive data channel 0 OUT_D0- 100 O HDMI output negative data channel 0 TDA19997HL_2 Product data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 02 -- 22 December 2009 7 of 26 TDA19997HL NXP Semiconductors Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer [1] P = power supply; G = ground; I = input and O = output; I/O = input/output. 8. Functional description The TDA19997HL is a DVI/HDMI switch comprising four DVI/HDMI inputs and one output optimized for Hi-Speed TMDS data. All inputs meet HDMI compliance tests and include a built-in auto-adaptive input equalizer. The TDA19997HL includes an activity detection module and Hot Plug Detect management. In addition, the TDA19997HL stores the Extended Display Identification Data (EDID) for each input in the built-in EDID memory. Full DDC-bus functionality is provided by the TDA19997HL, including level-shifting. 8.1 HDMI input The TDA19997HL supports bit rate inputs up to 2.25 Gbit/s enabling high frame rate formats such as 1080p60, 1080i120 and 720p120 in 36-bit Deep Color mode. The termination resistor control (R12K) needs an external resistor of 12 k 1 %. The termination resistor can be disconnected from the 3.3 V supply to remove the common-mode voltage via the I2C-bus and/or when RXx_HPD is LOW. 8.2 Equalizer The input equalizer is fully auto-adaptive, needing no external control. Signals from short cables with very low TMDS clock frequencies (20 MHz) to long cables (up to 20 m) at high TMDS clock frequencies (225 MHz) are easily managed by the TDA19997HL's equalizer. 8.3 Activity detection When activity is detected, the output is automatically activated. If no input activity is detected, the output is disabled to avoid false detections by the HDMI receiver. The power consumption is reduced accordingly. The detection range is fixed by I2C-bus. An interrupt output can be used to indicate any activity change. * In I2C-bus mode: the TMDS frequency can be read, however, the precision of the value depends on internal oscillator accuracy. 8.4 Embedded EDID memory The size of the EDID memory is 253-byte shared and 3-byte dedicated for each input. The memory can be accessed by each input at the same time. EDID content programming is performed using the non-volatile memory. The EDID memory can be powered by +5 V from the source or directly from the PCB using the dedicated AUX_5V pin. In Power-down mode, the EDID memory remains active and it is possible to modify its content. Access from pins RXx_DDC_DAT and RXx_DDC_CLK is independent of other supplies. Consequently, the source has access to the EDID memory when TDA19997HL is not powered. Content can be modified using the I2C-bus. However, data modified using the I2C-bus must be powered by the 1.8 V supply from pin CDEC_DDC or the AUX_5V auxiliary supply pin. TDA19997HL_2 Product data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 02 -- 22 December 2009 8 of 26 TDA19997HL NXP Semiconductors Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer EDID memory accesses are only acknowledged when EDID-only mode is enabled. Remark: Embedded non-volatile memory content shall be programmed with all termination resistors disconnected to ensure proper programming. 8.5 Display Data Channel (DDC) The DDC-bus is 5 V tolerant and supports all direct connections from the HDMI source. The TDA19997HL provides level-shifting and buffering for both OUT_DDC_DAT and OUT_DDC_CLK pins. It allows level-shifting from 5 V on the source side to 3.3 V on the receiver side. To prevent a lock-up condition, a specific digital protection is implemented on the DDC-bus. Pins RXx_DDC_DAT, RXx_DDC_CLK, OUT_DDC_DAT and OUT_DDC_CLK are compatible with the I2C-bus specification in Fast-mode (400 kHz): * Pins RXx_DDC_DAT and RXx_DDC_CLK at VDD = 4.5 V to 5.5 V * Pins OUT_DDC_DAT and OUT_DDC_CLK at VDD = 3.0 V to 3.6 V When the TDA19997HL is not 1.8 V core supplied, pins OUT_DDC_DAT and OUT_DDC_CLK are high-impedance. In addition, pins RXx_DDC_DAT and RXx_DDC_CLK are high-impedance when the device is not 5 V supplied. TDA19997HL acts as a DDC-bus master switch to prevent bus corruption. When the input selection changes, the upstream DDC-bus communication (using RXx_DDC_DAT and RXx_DDC_CLK) is disconnected and a stop bit is sent on the downstream DDC-bus communication (using OUT_DDC_DAT and OUT_DDC_CLK). The DDC-bus is then connected on the next upstream DDC during a free bus period to avoid bus corruption. 8.6 HDMI features TDA19997HL does not decode Data Island or Deep Color information, it forwards these packets including null packets. 8.7 +5 V signal detection +5 V signal detection from source is used for activity control through I2C-bus by setting a bit and an interrupt. 8.8 AUX_5V pin This pin can be used to supply the built-in EDID memory and DDC-bus enabling access to EDID memory using the DDC-bus without a +5 V signal from any of the input sources. When pin AUX_5V is powered, the TDA19997HL provides support for HDMI cabled sources without a +5 V signal. In addition, the AUX_5V supply ensures EDID data stored in active memory is not lost when a +5 V signal is not available from the input sources. Input signal detection (+5 V) is also available when AUX_5V pin is powered. AUX_5V is necessary when using the fifth DDC-bus input (RXE_DDC_DAT, RXE_DDC_CLK). TDA19997HL_2 Product data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 02 -- 22 December 2009 9 of 26 TDA19997HL NXP Semiconductors Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer 8.9 HDMI output The TDA19997HL HDMI output port is only activated when data is detected on the selected input. HDMI output can be switched off (high-impedance) using an I2C-bus bit or using pin PD. * Idle mode: HDMI output is either fixed at a constant value (fail-safe protection) or high-impedance. Configuration is performed using an I2C-bus bit. When output is fixed at a constant value, it creates a voltage difference in the differential pairs and stabilizes the receiver differential amplifier. The disadvantage of this protection against noise is increased power consumption (current from switch and pull-up on receiver side). If the two differential output pairs are high-impedance, the receiver differential pair is common mode (receiver pull-up). The receiver differential amplifier is not stable and does not need any additional power (no current from switch). 8.10 Power management The following five power modes are available: * * * * * Table 4. Operating mode: the device is fully functional Power-off mode: no supplies are available EDID-only mode: only +5 V from the source available Power-down mode: all supplies are available and pin PD is HIGH. Idle mode: all supplies are available and there is no HDMI input. As a power saving feature, Idle mode is automatically selected when there is no activity on the inputs. When activity is detected, Operating mode wake-up is automatically selected Power management Functions Mode EDID-only Power-down Idle Operating n/a on on on [1] [4] [4] [4] RXx_DDC_DAT; RXx_DDC_CLK (if 5 V)[5][3] on [4] [4] [4] EDID DDC read (if 5 V)[3] [1] [4] [4] [4] EDID I2C-bus write (If 5 V)[3] off on on on [4] +5 V signal detection RXx_HPD (if 5 V)[2][3] OUT_DDC_DAT; OUT_DDC_CLK off off [4] INT_N management off on on on [4] Termination resistors off off [4] Activity detection off off [4] [4] [4] Equalizer (when active) off off [4] TMDS buffer extended mode off off [1] [1] TMDS output (if active) off off [4] [4] Configuration register read/write off on on on Configuration nonvolatile memory download off on on on Configuration nonvolatile memory write off off on on [1] Nonvolatile memory. [2] x = A, B, C or D. TDA19997HL_2 Product data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 02 -- 22 December 2009 10 of 26 TDA19997HL NXP Semiconductors Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer [3] When 5 V is indicated, a +5 V input signal is available on at least one HDMI input and/or pin AUX_5V is powered. [4] Bit state dependent. [5] x = A, B, C, D or E. 8.11 Power supplies The termination supply voltage must be 3.3 V 5 % with a termination resistance of 50 10 % as defined in the HDMI 1.3a specification. A dedicated 3.3 V 10 % supply (powering interrupt pin INT_N/MUTE) is kept for compatibility with TDA9996. This pin shall be connected to the rest of 3.3 V supply line. The 1.8 V supply must also be 10 %. A double Power-On Reset (POR) is implemented to manage different delays between both supply ramp-ups. POR is managed internally without a reset pin. All 1.8 V power supply pins (VDDDC, VDDH, VDDO) could be connected together (i.e. these pins must be shorted out). +5 V from the HDMI connector and AUX_5V pin are used to supply the EDID memory and the corresponding DDC-bus slave module. To maintain the EDID (volatile memory part) contents modified by I2C-bus, it is necessary to have +5 V (from HDMI connector or AUX_5V pin) constantly available. 8.12 I2C-bus The TDA19997HL allows software programming of its internal registers using the I2C-bus. The I2C-bus is a separate bus to the DDC-bus, ensuring that I2C-bus programming of the TDA19997HL's registers does not influence DDC-bus operation. The TDA19997HL supports I2C-bus Fast-mode (400 kHz). 8.12.1 I2C-bus protocol To access registers, the TDA19997HL uses the I2C-bus. The TDA19997HL acts as an I2C-bus slave device. Pin I2C_SCL is used as the input pin. Both Fast-mode (400 kHz) and Standard-mode (100 kHz) are supported by the TDA19997HL. The slave I2C-bus address is shown in Table 5. The I2C-bus slave address is 1100 A2 A1 A0 R/W. Address bit values are stored in the non-volatile configuration memory and enable selection of the slave address. The default slave address value is 1100 000x. The I2C-bus slave address is identical to TDA9996. Table 5. Default slave address Device type TDA19997HL Bit A6 A5 A4 A3 A2 A1 A0 R/W 1 1 0 0 A2 A1 A0 1/0 I2C-bus access is explained in Figure 3. The I2C-bus master writes the TDA19997HL address and the subaddress to access the specific register, then it writes the data. TDA19997HL_2 Product data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 02 -- 22 December 2009 11 of 26 TDA19997HL NXP Semiconductors Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SCL SDA SLAVE ADDRESS SUBADDRESS DATA STOP 001aaf292 Fig 3. I2C-bus access 8.12.2 Memory page management The I2C-bus memory is split into several pages, selected using the common register CURPAGE_ADR. It is only necessary to write in this register once to change the current page. Multiple read or write operations in the same page must start by writing to register CURPAGE_ADR once. * * * * * Page 00h: general control Page 20h: EDID block0 Page 21h: EDID block1 and control Page 22h: second EDID block0 Page 30h: configuration 9. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Min Max Unit VDDx(3V3) supply voltage on all 3.3 V pins Conditions -0.5 +4.6 V VDDx(1V8) supply voltage on all 1.8 V pins -0.5 +2.5 V VDD supply voltage difference -0.5 +0.5 V Tstg storage temperature -55 +150 C Tamb ambient temperature 0 +70 C Tj junction temperature - +125 C HDMI input pins: RXx_D0+, RXx_D0-, RXx_D1+, RXx_D1-, RXx_D2+, RXx_D2-, RXx_HPD, RXx_5V, RXy_DDC_DAT, RXy_DDC_CLK, CEC[1][2] VESD electrostatic discharge voltage IEC 61000-4-2 class 3 (contact discharge) 7 - kV HDMI output pins: OUT_D0-, OUT_D0+, OUT_D1-, OUT_D1+, OUT_D2-, OUT_D2+, OUT_DDC_DAT, OUT_DDC_CLK VESD electrostatic discharge voltage IEC 61000-4-2 class 2 (contact discharge) 5 - kV electrostatic discharge voltage EIA/JESD22-A114-F (human body model) class 2 -2500 +2500 V EIA/JESD22-A115-A (machine model) class B -200 +200 V EIA/JESD22-C101-D (FCDM) class IV 1500 - V All pins VESD [1] x = A, B, C, D. TDA19997HL_2 Product data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 02 -- 22 December 2009 12 of 26 TDA19997HL NXP Semiconductors Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer [2] y = A, B, C, D, E. 10. Thermal characteristics Table 7. Thermal characteristics Symbol Parameter Rth(j-a) Rth(j-c) Conditions Typ Unit thermal resistance from junction to ambient in free air 49.5 K/W thermal resistance from junction to case 18.9 K/W 11. Characteristics Table 8. Characteristics VDDH(3V3) = 3.13 V to 3.47 V; VDDDC(3V3) = 3.0 V to 3.6 V; VDDH(1V8) = 1.65 V to 1.95 V; VDDDC(1V8) = 1.65 V to 1.95 V; Tamb = 0 C to +70 C; typical values measured at VDDH(3V3) and VDDDC(3V3) = 3.3 V; VDDH(1V8) and VDDDC(1V8) = 1.8 V and Tamb = 25 C; fmax = 2.25 GHz; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supplies VDDH(3V3) HDMI supply voltage (3.3 V) 3.13 3.3 3.47 V VDDH(1V8) HDMI supply voltage (1.8 V) 1.65 1.8 1.95 V VDDS(3V3) supervisor supply voltage (3.3 V) 3.0 3.3 3.6 V VDDDC(3V3) core digital supply voltage (3.3 V) 3.0 3.3 3.6 V VDDDC(1V8) core digital supply voltage (1.8 V) 1.65 1.8 1.95 V VDDO(3V3) output supply voltage (3.3 V) 3.0 3.3 3.6 V VDDO(1V8) output supply voltage (1.8 V) 1.65 1.8 1.95 V [1][2] IDDH(3V3) HDMI supply current (3.3 V) - 22 29 mA IDDH(1V8) HDMI supply current (1.8 V) - 13 16 mA IDDS(3V3) supervisor supply current (3.3 V) - 2 3 mA IDDDC(3V3) core digital supply current (3.3 V) - 6 8 mA IDDDC(1V8) core digital supply current (1.8 V) Pin 8 - 51 70 mA Pin 45 - 77 90 mA Pin 91 - 92 105 mA IDDO(3V3) output supply current (3.3 V) - 23 28 mA IDDO(1V8) output supply current (1.8 V) - 15 18 mA IAUX_5V current on pin AUX_5V - 3 5 mA Tj(max) maximum junction temperature - - 124 C Rth(j-a) = 49.5 K/W TDA19997HL_2 Product data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 02 -- 22 December 2009 13 of 26 TDA19997HL NXP Semiconductors Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer Table 8. Characteristics ...continued VDDH(3V3) = 3.13 V to 3.47 V; VDDDC(3V3) = 3.0 V to 3.6 V; VDDH(1V8) = 1.65 V to 1.95 V; VDDDC(1V8) = 1.65 V to 1.95 V; Tamb = 0 C to +70 C; typical values measured at VDDH(3V3) and VDDDC(3V3) = 3.3 V; VDDH(1V8) and VDDDC(1V8) = 1.8 V and Tamb = 25 C; fmax = 2.25 GHz; unless otherwise specified. Symbol Parameter Conditions Pcons Power consumption 0 = Power-down; no 5 V Min Typ Max Unit 3.3 V - - 0 mW 1.8 V - - 0 mW 3.3 V - - 0 mW 1.8 V - - 0 mW - - 28 mW - - 15 mW - - 241 mW - - 583 mW - - 824 mW 1 = EDID read only; using +5 V (20 mW) from source for EDID 2 = Idle mode; EDID + I2C-bus + HDMI, No HDMI activity on selected input, 20 mW from source 3.3 V [3] 1.8 V 3 = Operating mode; all on, with HDMI activity on selected input 3.3 V [3] 1.8 V total power consumption in Operating mode TDA19997HL_2 Product data sheet [3] (c) NXP B.V. 2009. All rights reserved. Rev. 02 -- 22 December 2009 14 of 26 TDA19997HL NXP Semiconductors Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer Table 8. Characteristics ...continued VDDH(3V3) = 3.13 V to 3.47 V; VDDDC(3V3) = 3.0 V to 3.6 V; VDDH(1V8) = 1.65 V to 1.95 V; VDDDC(1V8) = 1.65 V to 1.95 V; Tamb = 0 C to +70 C; typical values measured at VDDH(3V3) and VDDDC(3V3) = 3.3 V; VDDH(1V8) and VDDDC(1V8) = 1.8 V and Tamb = 25 C; fmax = 2.25 GHz; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit HDMI inputs: pins RXx_C+, RXx_C-, RXx_D0+, RXx_D0-, RXx_D1+, RXx_D1-, RXx_D2+ and RXx_D2-[4] R12K = 12 k 1 % Vi(dif) differential input voltage VI(cm) common-mode input voltage 150 - 1200 mV 2.735 - 3.475 V 400 525 600 mV 3.125 3.3 3.475 V 2.535 2.8 3.065 V 225 - - MHz HDMI output pins: OUT_D0-, OUT_D0+, OUT_D1-, OUT_D1+, OUT_D2- and OUT_D2+ Vo(p-p) peak-to-peak output voltage VOH HIGH-level output voltage VOL LOW-level output voltage HDMI pins: RXx_C+ and fclk(max) with test load and operating conditions as described in the HDMI 1.3a specification RXx_C-[4] maximum clock frequency HDMI pins: OUT_D0-, OUT_D0+, OUT_D1-, OUT_D1+, OUT_D2-, OUT_D2+, RXx_D0-, RXx_D0+, RXx_D1-, RXx_D1+, RXx_D2- and RXx_D2+[4] fmax maximum frequency 2.25 - - GHz LOW-level input voltage - - 0.8 V HIGH-level input voltage 2.0 - - V Digital inputs[5]: pins PD VIL VIH Digital inputs[5]: pin RXx_HPD[4] VIL LOW-level input voltage - - 0.8 V VIH HIGH-level input voltage 2.0 - - V Ci input capacitance - - 2.8 pF Digital outputs: pin INT_N/MUTE VOH HIGH-level output voltage CL = 10 pF; lOH = 2 mA 2.4 - - V VOL LOW-level output voltage CL = 10 pF; lOL = 2 mA - - 0.4 V I2C-bus: pins I2C_SCL and I2C_SDA (Fast-mode)[5] fSCL SCL clock frequency - - 400 kHz Cb capacitive load for each bus line - - 400 pF input capacitance - - 10 pF Standard-mode - - 100 kHz Fast-mode - - 400 kHz - - 10 pF - - 100 kHz 400 kHz Ci DDC I2C-bus: fSCL pins RXx_DDC_DAT and SCL clock frequency Ci RXx_DDC_CLK[6][5] input capacitance DDC I2C-bus[5]: fSCL master bus; pins OUT_DDC_DAT and OUT_DDC_CLK SCL clock frequency Standard-mode Fast-mode MTP endurance Nendu(W) write endurance number of cycles at Tj = 125 C 1000 [1] Typical values: add 40 mA by connected link for regulator dimensioning. [2] Maximum values: add 48 mA by connected link for regulator dimensioning. [3] Maximum values: add 167 mW by connected link for regulator dimensioning (12 mA x 3.47 V = 167 mW). TDA19997HL_2 Product data sheet - - (c) NXP B.V. 2009. All rights reserved. Rev. 02 -- 22 December 2009 15 of 26 TDA19997HL NXP Semiconductors Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer [4] x = A, B, C, D. [5] 5 V tolerant. [6] x = A, B, C, D, E. 12. Typical operating characteristics 001aak378 300 current consumption (mA) VDDx(1V8) 200 100 VDDx(3V3) 0 0 50 100 150 200 250 fTMDS (MHz) (1) VDDx(1V8) = sum of current from all VDD(1V8) supply pins. (2) VDDx(3V3) = sum of current from all VDD(3V3) supply pins, excluding current from HDMI source. Fig 4. Typical current consumption TDA19997HL_2 Product data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 02 -- 22 December 2009 16 of 26 TDA19997HL NXP Semiconductors Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer SOURCE CABLE TDA19997 TP1 (source output) TP2 (cable output) TP3 (switch output) 001aak373 a. Jitter measurement test bench 001aak366 40 001aak367 40 Jitter (% Tbit) Jitter (% Tbit) 30 30 20 20 TP2 TP1 TP2 TP3 10 10 TP3 TP1 0 0 1m 5m 10 m cable length 15 m AWG26 b. Typical jitter measurement in 480p60 24-bit deep color video format 001aak368 40 Jitter (% Tbit) 1m 20 m AWG24 30 TP2 TP3 TP1 20 TP1 TP3 10 10 0 0 1m 5m 10 m cable length 15 m AWG26 20 m AWG24 d. Typical jitter measurement in 1080p60 24-bit deep color video format Fig 5. 20 m AWG24 001aak371 40 30 20 15 m AWG26 c. Typical jitter measurement in 720p60 24-bit deep color video format Jitter (% Tbit) TP2 5m 10 m cable length 1m 5m 10 m cable length 15 m AWG26 20 m AWG24 e. Typical jitter measurement in 1080p60 36-bit deep color video format Typical jitter measurement TDA19997HL_2 Product data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 02 -- 22 December 2009 17 of 26 TDA19997HL NXP Semiconductors Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer 001aak374 875 (mV) (mV) 525 525 175 175 -175 -175 -525 -525 -875 001aak375 875 0 1.48 2.96 4.44 5.92 7.40 -875 0 0.538 1.076 1.614 t (ns) a. Typical eye diagram in 480p60 24-bit deep color video format 001aak376 875 (mV) b. Typical eye diagram in 720p60 24-bit deep color video format 001aak377 875 (mV) 525 525 175 175 -175 -175 -525 -525 -875 0 270 540 810 1080 1350 -875 0 t (ps) c. Typical eye diagram in 1080p60 24-bit deep color video format Fig 6. 2.152 2.690 t (ns) 179.6 359.2 538.8 718.4 898.0 t (ps) d. Typical eye diagram in 1080p60 36-bit deep color video format Typical eye diagram measurement with Tx compliancy mask TDA19997HL_2 Product data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 02 -- 22 December 2009 18 of 26 TDA19997HL NXP Semiconductors Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer 13. Application information 47 k (1) 76 RXD_HPD RXD_DDC_DAT RXD_DDC_CLK RXD_5V 77 78 79 RXD_C- 81 80 VDDH(3V3) RXD_C+ 82 RXD_D0+ RXD_D0- 83 84 VSS 86 85 RXD_D1+ VDDH(3V3) RXD_D1- 87 89 88 RXD_D2+ VDDDC(1V8) RXD-D2- 90 91 OUT_D2+ VSS 92 94 93 VDDO(1V8) OUT_D1+ OUT_D2- 95 96 OUT_D1- 97 OUT_D0+ VSS 98 99 61 16 60 17 59 18 58 19 57 20 56 21 55 22 54 VDDH(1V8) 12 k 1% R12K VDD(3V3) VSS RXC_D2+ RXC_D2- VDDH(3V3) RXC_D1+ RXC_D1- VSS RXC_D0+ RXC_D0- VDDH(3V3) 100 nF RXC_C+ RXC_C- RXC_DDC_CLK RXC_DDC_DAT 47 k(1) RXC_5V RXC_HPD CEC 47 k(2) 100 nF VSS VDDS(3V3) 100 nF 100 nF CDEC_STBY INT_N/MUTE 22 k VDD(3V3) RXE_DDC_DAT 50 RXE_DDC_CLK I2C_SCL 49 I2C_SDA 47 48 PD TEST2 46 45 VDDDC(3V3) 44 VDDDC(1V8) CDEC_DDC 42 VSS RXB_D2+ RXB_D2- VDDH(3V3) VSS 100 nF 43 51 41 25 40 52 39 53 38 23 24 37 AUX_5V V5V_AUX 62 RXB_D1- VDDH(1V8) 14 RXB_D1+ 100 nF 63 15 VSS RXA_D2+ TDA19997 13 36 RXA_D2- 64 35 VDDH(3V3) 65 12 RXB_D0- RXA_D1+ 11 RXB_D0+ VSS RXA_D1- 66 34 RXA_D0- RXA_D0+ 67 10 33 VDDH(3V) 9 32 RXA_C+ 100 nF 68 RXB_C+ RXA_C- 69 8 VDDH(3V3) RXA_DDC_CLK 7 RXB_C- RXA_DDC_DAT 47 k(1) 70 31 RXA_5V 6 30 RXA_HPD 71 RXB_DDC_CLK VDDDC(1V8) 47 k(2) 72 5 29 100 nF 4 RXB_5V VSS 73 RXB_DDC_DAT OUT_DDC_DAT 74 27 22 k VDD(3V3) 2 28 OUT_DDC_CLK 47 k(2) 100 nF 75 RXB_HPD VDDO(3V3) 22 k VDD(3V3) 100 nF 3 26 OUT_C- 100 nF 1 TEST1 VSS OUT_C+ 100 OUT_D0- 100 nF 100 nF I2C-bus 100 nF 100 nF 47 k(2) 100 nF 47 k (1) 100 nF 100 nF 001aak369 (1) Mandatory. (2) Recommended. Fig 7. Application diagram TDA19997HL_2 Product data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 02 -- 22 December 2009 19 of 26 TDA19997HL NXP Semiconductors Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer 14. Package outline LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1 c y X A 51 75 50 76 ZE e E HE A A2 (A 3) A1 w M bp Lp pin 1 index L 100 detail X 26 25 1 ZD e v M A w M bp D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 14.1 13.9 0.5 HD HE 16.25 16.25 15.75 15.75 L Lp v w y 1 0.75 0.45 0.2 0.08 0.08 Z D (1) Z E (1) 1.15 0.85 1.15 0.85 7o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. Fig 8. REFERENCES OUTLINE VERSION IEC JEDEC SOT407-1 136E20 MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-02-01 03-02-20 Package outline SOT407-1 (LQFP100) TDA19997HL_2 Product data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 02 -- 22 December 2009 20 of 26 TDA19997HL NXP Semiconductors Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer 15. Abbreviations Table 9. Abbreviations Acronym Description ATC Authorized Test Center AVR Audio/Video Receiver AWG American Wire Gauge CDM Charged Device Model DDC Display Data Channel DVI Digital Video Input EDID Extended Display Identification Data ESD ElectroStatic Discharge EQ EQualizer HBM Human Body Model HDCP High-bandwidth Digital Content Protection HDMI High-Definition Multimedia Interface HDTV High-Definition TeleVision HPD Hot Plug Detect I2 C Inter-Integrated Circuit LCD Liquid Crystal Display MM Machine Model MTP Multi-Time Programmable POR Power-On Reset RGB Red/Green/Blue RT Resistor Termination SoC System on a Chip TMDS Transition Minimized Differential Signaling VGA Video Graphic Array YCbCr Y = Luminance, Cb = Chroma blue, Cr = Chroma red 16. References [1] HDMI 1.4 -- High-Definition Multimedia Interface; Specification Version 1.4; 5 June 2009. [2] CEA-861D -- A DTV profile for Uncompressed High-Speed Digital Interfaces; CEA-861rDv18; 5 August 2006. [3] IEC-60958 -- Digital audio interface - Part 1: General; Second edition; March 2004. Digital audio interface - Part 3: Consumer applications; Second edition; January 2003. [4] IEC-61937 -- Digital audio interface - Interface for non-linear PCM encode audio bit stream applying IEC-60958 - Part 1: General; First edition; May 2003. [5] HDCP 1.3 -- High-bandwidth Digital Content Protection; Revision 1.3; 21 December 2006. TDA19997HL_2 Product data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 02 -- 22 December 2009 21 of 26 TDA19997HL NXP Semiconductors Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer [6] E-DDC 1.1 -- VESA Enhanced Display Data Channel Standard; Version 1.1; 24 March 2004. [7] DVI 1.0 -- DVI Digital Video Interface; Revision 1.0; 2 April 1999. 17. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes TDA19997HL_2 20091222 Product data sheet - TDA19997_1 Modifications: TDA19997_1 * * * Section 2 "Features": updated ESD part Table 1 "Quick reference data": updated ESD part Table 6 "Limiting values": updated ESD part 20090819 Objective data sheet TDA19997HL_2 Product data sheet - - (c) NXP B.V. 2009. All rights reserved. Rev. 02 -- 22 December 2009 22 of 26 TDA19997HL NXP Semiconductors Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term `short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 18.3 Disclaimers General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 18.4 Licenses Purchase of NXP ICs with HDMI technology Use of an NXP IC with HDMI technology in equipment that complies with the HDMI standard requires a license from HDMI Licensing LLC, 1060 E. Arques Avenue Suite 100, Sunnyvale CA 94085, USA, e-mail: admin@hdmi.org. 18.5 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com TDA19997HL_2 Product data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 02 -- 22 December 2009 23 of 26 TDA19997HL NXP Semiconductors Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer 20. Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Quick reference data . . . . . . . . . . . . . . . . . . . . .3 Ordering information . . . . . . . . . . . . . . . . . . . . .3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 Power management . . . . . . . . . . . . . . . . . . . .10 Default slave address . . . . . . . . . . . . . . . . . . . 11 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .12 Thermal characteristics . . . . . . . . . . . . . . . . . .13 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .21 Revision history . . . . . . . . . . . . . . . . . . . . . . . .22 TDA19997HL_2 Product data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 02 -- 22 December 2009 24 of 26 TDA19997HL NXP Semiconductors Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer 21. Figures Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . .5 I2C-bus access. . . . . . . . . . . . . . . . . . . . . . . . . . .12 Typical current consumption . . . . . . . . . . . . . . . .16 Typical jitter measurement . . . . . . . . . . . . . . . . . .17 Typical eye diagram measurement with Tx compliancy mask . . . . . . . . . . . . . . . . . . . . . .18 Application diagram . . . . . . . . . . . . . . . . . . . . . . .19 Package outline SOT407-1 (LQFP100) . . . . . . . .20 TDA19997HL_2 Product data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 02 -- 22 December 2009 25 of 26 TDA19997HL NXP Semiconductors Smart HDMI 1.4 (4 : 1) switch with auto-adaptive equalizer 22. Contents 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.12.1 8.12.2 9 10 11 12 13 14 15 16 17 18 18.1 18.2 18.3 18.4 18.5 19 20 21 22 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Quick reference data . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 8 HDMI input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Equalizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Activity detection. . . . . . . . . . . . . . . . . . . . . . . . 8 Embedded EDID memory. . . . . . . . . . . . . . . . . 8 Display Data Channel (DDC) . . . . . . . . . . . . . . 9 HDMI features . . . . . . . . . . . . . . . . . . . . . . . . . 9 +5 V signal detection . . . . . . . . . . . . . . . . . . . . 9 AUX_5V pin . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 HDMI output . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power management . . . . . . . . . . . . . . . . . . . . 10 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . 11 I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 11 Memory page management . . . . . . . . . . . . . . 12 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 12 Thermal characteristics . . . . . . . . . . . . . . . . . 13 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 13 Typical operating characteristics . . . . . . . . . . 16 Application information. . . . . . . . . . . . . . . . . . 19 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 20 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 21 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 22 Legal information. . . . . . . . . . . . . . . . . . . . . . . 23 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Contact information. . . . . . . . . . . . . . . . . . . . . 23 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 22 December 2009 Document identifier: TDA19997HL_2