Supertex inc.
Supertex inc.
www.supertex.com
HV219
Doc.# DSFP-HV219
C070713
Features
►HVCMOS® technology for high performance
►Very low quiescent power dissipation (-10µA)
►Output on-resistance typically 11Ω
►Low parasitic capacitance
►DC to 50MHz small signal frequency response
►-60dB typical off-isolation at 5.0MHz
►CMOS logic circuitry for low power
►Excellent noise immunity
►Serial shift register logic control with latches
►Flexible operating supply voltages
►Surface mount packages
Applications
►Medical ultrasound imaging
►Non-destructive evaluation
Block Diagram
200V Low Charge Injection
8-Channel High Voltage Analog Switch
General Description
The Supertex HV219 is a low switch resistance, low charge
injection, 8-channel, 200V, analog switch integrated circuit (IC)
intended primarily for medical ultrasound imaging. The device can
also be used for NDE (non-destructive evaluation) applications. The
HV219 is a lower switch resistance, 11Ω versus 22Ω, version of the
Supertex HV20220 device. The lower switch resistance will help
reduce insertion loss. It has the same pin conguration as that of the
Supertex HV20220PJ and the HV20220FG.
The device is manufactured using Supertex’s HVCMOS® (high
voltage CMOS) technology with high voltage bilateral DMOS
structures for the outputs and low voltage CMOS logic for the input
control. The outputs are congured as eight independent single
pole single throw 11Ω analog switches. The input logic is an 8-bit
serial to parallel shift register followed by an 8-bit parallel latch. The
switch states are determined by the data in the latch. Logic high will
correspond to a closed switch and logic low as an opened switch.
The HV219 is designed to operate on various combinations of high
voltage supplies. For example the VPP and VNN supplies can be:
+40V/-160V, +100V/-100V, or +160V/-40V. This allows the user to
maximize the signal voltage for uni-polar negative, bi-polar, or uni-
polar positive.
SW0
SW1
SW2
SW3
SW4
SW5
SW6
SW7
Latches
Level
Shifters
Output
Switches
VDD LE CL
DIN
CLK
DOUT
8-Bit
Shift
Register
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
VNN VPP
GND
2
HV219
Supertex inc.
www.supertex.com
Doc.# DSFP-HV219
C070713
Absolute Maximum Ratings
Parameter Value
VDD logic power supply voltage -0.5V to +15V
VPP - VNN supply voltage 220V
VPP positive high voltage supply -0.5V to VNN +200V
VNN negative high voltage supply +0.5V to -200V
Logic input voltages -0.5V to VDD +0.3V
Analog signal range VNN to VPP
Peak analog signal current/channel 3.0A
Storage temperature -65OC to +150OC
Power dissipation:
28-Lead PLCC
48-Lead LQFP
1.2W
1.0W
Operating Conditions
Sym Parameter Value
VDD Logic power supply voltage 4.5V to 13.2V
VPP Positive high voltage supply 40V to VNN +200V
VNN Negative high voltage supply -40V to -160V
VIH High level input logic voltage VDD -1.5V to VDD
VIL Low-level input logic voltage 0V to 1.5V
VSIG
Analog signal voltage
peak-to-peak VNN +10V to VPP -10V
TAOperating free air temperature 0OC to 70OC
Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied. Continuous operation of the device
at the absolute rating level may affect device reliability. All voltages are referenced to device
ground.
Pin Conguration
Product Marking
YY = Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
Top Marking
Bottom Marking
YYWW
HV219PJ
LLLLLLLLLL
CCCCCCCCCCC
AAA
YY = Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
Top Marking
Bottom Marking
YYWW
HV219FG
LLLLLLLLL
CCCCCCCC
AAA
28-Lead PLCC
48-Lead LQFP
28-Lead PLCC
(top view)
48-Lead LQFP
(top view)
1
48
1 28
4 26
Package may or may not include the following marks: Si or
Package may or may not include the following marks: Si or
Ordering Information
Part Number Package Option Packing
HV219FG-G 48-Lead LQFP 250/Tray
HV219FG-G M931 1000/Reel
HV219PJ-G 28-Lead PLCC 38/Tube
HV219PJ-G M904 500/Reel
Typical Thermal Resistance
Package θja
48-Lead LQFP 52OC/W
28-Lead PLCC 48OC/W
Power Up/Down Sequence
1. Power up/down sequence is arbitrary except GND must be powered up rst and powered down last. This applies for
applications powering GND of the IC with different voltages.
2. VSIG must always be at or in between VPP and VNN or oating during power up/down transition.
3. Rise and fall times of the power supplies VDD, VPP
, and VNN should not be less than 1.0ms.
-G denotes a lead (Pb)-free / RoHS compliant package
3
HV219
Supertex inc.
www.supertex.com
Doc.# DSFP-HV219
C070713
DC Electrical Characteristics (over recommended operating conditions unless otherwise noted)
Sym Parameter 0OC +25OC +70OCUnits Conditions
Min Max Min Typ Max Min Max
RONS
Small signal switch
on-resistance
- 15 - 13 19 - 24
Ω
ISIG = 5.0mA VPP = +40V
VNN = -160V
- 13 - 11 14 - 16 ISIG = 200mA
- 13 - 11 14 - 15 ISIG = 5.0mA VPP = +100V
VNN = -100V
- 9.0 - 9.0 12 - 14 ISIG = 200mA
- 12 - 10 13 - 15 ISIG = 5.0mA VPP= +160V
VNN = -40V
-11 - 8 13 - 14 ISIG = 200mA
ΔRONS
Small signal switch
on-resistance matching - 20 - 5.0 20 - 20 % ISIG = 5.0mA, VPP = +100V,
VNN = -100V
RONL
Large signal switch
on-resistance - - - 8.0 - - - ΩVSIG = VPP -10V, ISIG = 1.0A
ISOL Switch off leakage per switch - 5.0 - 1.0 10 - 15 µA VSIG = VPP -10V & VNN +10V
VOS
DC offset switch off - 300 - 100 300 - 300 mV RLOAD = 100kΩ
DC offset switch on - 500 - 100 500 - 500 mV RLOAD = 100kΩ
IPPQ Quiescent VPP supply current - - - 10 50 - - µA All switches off
INNQ Quiescent VNN supply current - - - -10 -50 - - µA All switches off
IPPQ Quiescent VPP supply current - - - 10 50 - - µA All switches on,
ISW = 5.0mA
INNQ Quiescent VNN supply current - - - -10 -50 - - µA All switches on,
ISW = 5.0mA
ISW Switch output peak current - 3.0 - 3.0 2.0 - 2.0 A VSIG duty cycle < 0.1%
fSW Output switch frequency - - - - 50 - - kHz Duty cycle = 50%
IPP Average VPP supply current
- 6.5 - - 7.0 - 8.0
mA
VPP = +40V
VNN = -160V All output
switches
are turning
on and off
at 50kHz
with no load
- 4.0 - - 5.0 - 5.5 VPP = +100V
VNN = -100V
- 4.0 - - 5.0 - 5.5 VPP = +160V
VNN = -40V
INN Average VNN supply current
- 6.5 - - 7.0 - 8.0
mA
VPP = +40V
VNN = -160V All output
switches
are turning
on and off
at 50kHz
with no load
- 4.0 - - 5.0 - 5.5 VPP = +100V
VNN = -100V
- 4.0 - - 5.0 - 5.5 VPP = +160V
VNN = -40V
IDD Average VDD supply current - 4.0 - - 4.0 - 4.0 mA fCLK = 5.0MHz, VDD = 5.0V
IDDQ Quiescent VDD supply current - 10 - - 10 - 10 µA All logic inputs are static
ISOR Data out source current 0.45 - 0.45 0.70 - 0.40 - mA VOUT = VDD -0.7V
ISINK Data out sink current 0.45 - 0.45 0.70 - 0.40 - mA VOUT = 0.7V
CIN Large input capacitance - 10 - - 10 - 10 pF ---
4
HV219
Supertex inc.
www.supertex.com
Doc.# DSFP-HV219
C070713
AC Electrical Characteristics (over recommended operating conditions, VDD = 5.0V, unless otherwise noted)
Sym Parameter 0OC +25OC +70OCUnits Conditions
Min Max Min Typ Max Min Max
tSD Set-up time before LE rises 150 - 150 - - 150 - ns ---
tWLE Time width of LE 150 - 150 - - 150 - ns ---
tDO Clock delay time to data out - 150 - - 150 - 150 ns ---
tWCL Time width of CL 150 - 150 - - 150 - ns ---
tSU Set-up time data to clock 15 - 15 8.0 - 20 - ns ---
tHHold time data from clock 35 - 35 - - 35 - ns ---
fCLK Clock frequency - 5.0 - - 5.0 - 5.0 MHz 50% duty cycle,
fDATA = fCLK/2
tr, tf Clock rise and fall times - 50 - - 50 - 50 ns ---
TON Turn-on time - 5.0 - - 5.0 - 5.0 µs VSIG = VPP -10V,
RLOAD = 10kΩ
TOFF Turn-off time - 5.0 - - 5.0 - 5.0 µs
dv/dt Maximum VSIG slew rate
- 20 - - 20 - 20
V/ns
VPP = +40V, VNN = -160V
- 20 - - 20 - 20 VPP = +100V, VNN = -100V
- 20 - - 20 - 20 VPP = +160V, VNN = -40V
KOOff isolation -30 - -30 -33 - - - dB
f = 5.0MHz,
1.0KΩ//15pF load
-58 - -58 - - - - f = 5.0MHz, 50Ω load
KCR Switch crosstalk - - -60 - - - - dB f = 5.0MHz, 50Ω load
IID
Output switch isolation diode
current - 300 - - 300 - 300 mA 300ns pulse width,
2% duty cycle
CSG(OFF) Off capacitance SW to GND 14 25 14 20 25 14 25 pF 0V, f = 1.0MHz
CSG(ON) On capacitance SW to GND 40 60 40 50 60 40 60 pF 0V, f = 1.0MHz
+VSPK
Output voltage spike
- - - - 150 - -
mV
VPP = +40V,
VNN = -160V, RLOAD = 50Ω
-VSPK - - - - 200 - -
+VSPK - - - - 150 - - VPP = +100V,
VNN = -100V, RLOAD = 50Ω
-VSPK - - - - 200 - -
+VSPK - - - - 150 - - VPP = +160V,
VNN = -40V, RLOAD = 50Ω
-VSPK - - - - 200 - -
QC Charge injection
- - - 1450 - - -
pC
VPP = +40V,
VNN = -160V, VSIG = 0V
- - - 1050 - - - VPP = +100V,
VNN = -100V, VSIG = 0V
- - - 550 - - - VPP = +160V,
VNN = -40V, VSIG = 0V
5
HV219
Supertex inc.
www.supertex.com
Doc.# DSFP-HV219
C070713
DATA
IN
LE
CLOCK
DATA
OUT
OFF
ON
VOUT
(typ)
50% 50%
50%50%
tWLE
tSD
tSU th
50%
50%
tOFF
50%
tDO
tON
tWCL
CLR
DN+1 DNDN-1
50%50%
90%
10%
Logic Timing Waveforms
Truth Table
Data in 8-Bit Shift Register LE CL Output Switch State
D0 D1 D2 D3 D4 D5 D6 D7 SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7
L L L OFF
H L L ON
L L L OFF
H L L ON
L L L OFF
H L L ON
L L L OFF
H L L ON
L L L OFF
H L L ON
L L L OFF
H L L ON
L L L OFF
H L L ON
L L L OFF
H L L ON
X X X X X X X X H L Hold Previous State
X X X X X X X X X H OFF OFF OFF OFF OFF OFF OFF OFF
Notes:
1. The eight switches operate independently.
2. Serial data is clocked in on the L to H transition clock.
3. The switches go to a state retaining their present condition at the rising edge of the LE.
4. When LE is low, the shift register data ows through the latch.
5. Shift register clocking has no effect on the switch states if LE is high.
6. The clear input overrides all other inputs.
6
HV219
Supertex inc.
www.supertex.com
Doc.# DSFP-HV219
C070713
Test Circuits
Charge Injection
VSIG
VOUT 1000pF
Q = 1000pF x VOUT
VOUT
Switch OFF Leakage
ISOL
VPP 5V
VNN
VPP - 10V
DC Offset ON/OFF
VOUT
TON/TOFF Test Circuit
VPP -10V
VOUT
Isolation Diode Current
IID
VNN
VSIG
NC
50Ω
50Ω
Output Voltage Spike
VOUT
1.0KΩ
+VSPK
-VSPK
VIN = 10VP-P
@5.0MHz
VOUT
RLOAD
50Ω
RLOAD
100kΩ
VNN + 10V
VPP 5V
VNN
VPP
VNN
VDD
GND
VPP 5V
VNN
VPP 5V
VNN
VPP 5V
VNN
VPP 5V
VNN
RLOAD
10kΩ
VIN = 10VP-P
@5.0MHz
KO = 20 Log VOUT
VIN
OFF Isolation
KCR = 20Log VOUT
VIN
Crosstalk
VPP 5V
VNN
VPP
VNN
VDD
GND
VPP
VNN
VDD
GND
VPP
VNN
VDD
GND
VPP
VNN
VDD
GND
VPP
VNN
VDD
GND
VPP
VNN
VDD
GND
RLOAD
VPP 5V
VNN
VPP
VNN
VDD
GND
7
HV219
Supertex inc.
www.supertex.com
Doc.# DSFP-HV219
C070713
Pin Description
48-Lead LQFP
Pin Name
1 SW5
2 NC
3 SW4
4 NC
5 SW4
6 NC
7 NC
8 SW3
9 NC
10 SW3
11 NC
12 SW2
Pin Name
13 NC
14 SW2
15 NC
16 SW1
17 NC
18 SW1
19 NC
20 SW0
21 NC
22 SW0
23 NC
24 VPP
Pin Name
25 VNN
26 NC
27 NC
28 GND
29 VDD
30 NC
31 NC
32 NC
33 DIN
34 CLK
35 LE
36 CLR
Pin Name
37 DOUT
38 NC
39 SW7
40 NC
41 SW7
42 NC
43 SW6
44 NC
45 SW6
46 NC
47 SW5
48 NC
Pin Description
28-Lead PLCC
Pin Name
1 SW3
2 SW3
3 SW2
4 SW2
5 SW1
6 SW1
7 SW0
Pin Name
8 SW0
9 NC
10 VPP
11 NC
12 VNN
13 GND
14 VDD
Pin Name
15 NC
16 DIN
17 CLK
18 LE
19 CL
20 DOUT
21 SW7
Pin Name
22 SW7
23 SW6
24 SW6
25 SW5
26 SW5
27 SW4
28 SW4
8
HV219
Supertex inc.
www.supertex.com
Doc.# DSFP-HV219
C070713
48-Lead LQFP Package Outline (FG)
7.00x7.00mm body, 1.60mm height (max), 0.50mm pitch
Symbol A A1 A2 b D D1 E E1 e L L1 L2 θ
Dimension
(mm)
MIN 1.40* 0.05 1.35 0.17 8.80* 6.80* 8.80* 6.80*
0.50
BSC
0.45
1.00
REF
0.25
BSC
0O
NOM - - 1.40 0.22 9.00 7.00 9.00 7.00 0.60 3.5O
MAX 1.60 0.15 1.45 0.27 9.20* 7.20* 9.20* 7.20* 0.75 7O
JEDEC Registration MS-026, Variation BBC, Issue D, Jan. 2001.
* This dimension is not specied in the JEDEC drawing.
Drawings are not to scale.
Supertex Doc. #: DSPD-48LQFPFG Version, D041309.
1
Seating
Plane
Gauge
Plane
θ
L
L1
L2
View B
View B
Seating
Plane
Top View
Side View
Note 1
(Index Area
D1/4 x E1/4)
48
A2A
A1
b
D
D1
E
E1
e
Note:
1. A Pin 1 identier must be located in the index area indicated. The Pin 1 identier can be: a molded mark/identier; an embedded metal marker; or
a printed indicator.
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
9
HV219
(The package drawing(s) in this data sheet may not reect the most current specications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-HV219
C070713
28-Lead PLCC Package Outline (PJ)
.453x.453in. body, .180in. height (max), .050in. pitch
Symbol A A1 A2 b b1 D D1 E E1 e R
Dimension
(inches)
MIN .165 .090 .062 .013 .026 .485 .450 .485 .450
.050
BSC
.025
NOM .172 .105 - - - .490 .453 .490 .453 .035
MAX .180 .120 .083 .021 .032 .495 .456 .495 .456 .045
JEDEC Registration MS-018, Variation AB, Issue A, June, 1993.
Drawings not to scale.
Supertex Doc. #: DSPD-28PLCCPJ, Version B031111.
.150max
.048/.042
x 45O
.075max
D
D1
E1
E
Top View
View
B
AA2
A1
Seating
Plane
Note 1
(Index Area)
.056/.042
x 45O
Base
Plane
.020min
b
View B
b1
Horizontal Side View
Vertical Side View
Note 2
.020max
(3 Places)
R
e
426
28
1
Notes:
1. A Pin 1 identier must be located in the index area indicated. The Pin 1 identier can be: a molded mark/identier; an embedded metal marker; or
a printed indicator.
2. Actual shape of this feature may vary.
