REV. 0
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a
AD7376*
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1997
*Patent Number: 5495245
615 V Operation
Digital Potentiometer
FUNCTIONAL BLOCK DIAGRAM
GND
V
DD
SDO
AD7376
7-BIT
SERIAL
REGISTER
Q
DCK
77-BIT
LATCH
R
7
SDI
CLK
A
W
B
V
SS
SHDN
CS
RS
SHDN
FEATURES
128 Position
Potentiometer Replacement
10 kV, 50 kV, 100 kV, 1 MV
Power Shutdown: Less than 1 mA
3-Wire SPI Compatible Serial Data Input
+5 V to +30 V Single Supply Operation
65 V to 615 V Dual Supply Operation
Midscale Preset
APPLICATIONS
Mechanical Potentiometer Replacement
Instrumentation: Gain, Offset Adjustment
Programmable Voltage-to-Current Conversion
Programmable Filters, Delays, Time Constants
Line Impedance Matching
Power Supply Adjustment
GENERAL DESCRIPTION
The AD7376 provides a single channel, 128-position digitally-
controlled variable resistor (VR) device. This device performs the
same electronic adjustment function as a potentiometer or vari-
able resistor. These products were optimized for instrument and
test equipment applications where a combination of high voltage
with a choice between bandwidth or power dissipation are avail-
able as a result of the wide selection of end-to-end terminal resis-
tance values. The AD7376 contains a fixed resistor with a wiper
contact that taps the fixed resistor value at a point determined by
a digital code loaded into the SPI-compatible serial-input regis-
ter. The resistance between the wiper and either endpoint of the
fixed resistor varies linearly with respect to the digital code trans-
ferred into the VR latch. The variable resistor offers a completely
programmable value of resistance between the A terminal and the
wiper or the B terminal and the wiper. The fixed A to B terminal
resistance of 10 kΩ, 50 kΩ, 100 kΩ or 1 MΩ has a nominal tem-
perature coefficient of –300 ppm/°C.
The VR has its own VR latch which holds its programmed resis-
tance value. The VR latch is updated from an internal serial-to-
parallel shift register which is loaded from a standard 3-wire
serial-input digital interface. Seven data bits make up the data
word clocked into the serial data input register (SDI). Only the
last seven bits of the data word loaded are transferred into the
7-bit VR latch when the CS strobe is returned to logic high. A
serial data output pin (SDO) at the opposite end of the serial
register allows simple daisy-chaining in multiple VR applications
without additional external decoding logic.
The reset (RS) pin forces the wiper to the midscale position by
loading 40
H
into the VR latch. The SHDN pin forces the resistor
to an end-to-end open circuit condition on the A terminal and
shorts the wiper to the B terminal, achieving a microwatt power
shutdown state. When shutdown is returned to logic high, the
previous latch settings put the wiper in the same resistance
setting prior to shutdown as long as power to V
DD
is not re-
moved. The digital interface is still active in shutdown so that
code changes can be made that will produce a new wiper posi-
tion when the device is taken out of shutdown.
The AD7376 is available in both surface mount (SOL-16) and
the 14-lead plastic DIP package. For ultracompact solutions
selected models are available in the thin TSSOP package. All
parts are guaranteed to operate over the extended industrial
temperature range of –40°C to +85°C. For operation at lower
supply voltages (+3 V to +5 V), see the AD8400/AD8402/
AD8403 products.
61 LSB ERROR BAND
61 LSB
SDI
(DATA IN)
SDO
(DATA OUT)
CLK
CS
VDD
VOUT 0V
0
1
0
1
0
1
0
1DXDX
tPD_MAX
D'XD'X
tDS tDH
tCH
tCSH0
tCSS
tCL
tCS1
tCSW
tS
tCSH
Figure 1. Detail Timing Diagram
The last seven data bits clocked into the serial input register will
be transferred to the VR 7-bit latch when CS returns to logic
high. Extra data bits are ignored.
–2– REV. 0
AD7376–SPECIFICATIONS
(VDD/VSS = 615 V 6 10% or 6 5 V 6 10%, VA = +VDD, VB = VSS/0 V, –408C < TA < +858C
unless otherwise noted.)
ELECTRICAL CHARACTERISTICS
Parameter Symbol Conditions Min Typ
1
Max Units
DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs)
Resistor Differential NL
2
R-DNL R
WB
, V
A
= NC –1 ±0.25 +1 LSB
Resistor Nonlinearity
2
R-INL R
WB
, V
A
= NC –1 ±0.5 +1 LSB
Nominal Resistor Tolerance ∆RT
A
= +25°C –30 30 %
Resistance Temperature Coefficient R
AB
/∆TV
AB
= V
DD
, Wiper = No Connect –300 ppm/°C
Wiper Resistance R
W
I
W
= ±15 V/R
NOMINAL
120 200 Ω
Wiper Resistance R
W
I
W
= ±5 V/R
NOMINAL
200 Ω
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs)
Resolution N 7 Bits
Integral Nonlinearity
3
INL –1 ±0.5 +1 LSB
Differential Nonlinearity
3
DNL –1 ±0.1 +1 LSB
Voltage Divider Temperature Coefficient ∆V
W
/∆T Code = 40
H
5 ppm/°C
Full-Scale Error V
WFSE
Code = 7F
H
–2 –0.5 +0 LSB
Zero-Scale Error V
WZSE
Code = 00
H
0 +0.5 +1 LSB
RESISTOR TERMINALS
Voltage Range
4
V
A, B, W
V
SS
V
DD
V
Capacitance
5
A, B C
A, B
f = 1 MHz, Measured to GND, Code = 40
H
45 pF
Capacitance
5
WC
W
f = 1 MHz, Measured to GND, Code = 40
H
60 pF
Shutdown Supply Current
6
I
A_SD
V
A
= V
DD
, V
B
= 0 V, SHDN = 0 0.01 1 µA
Shutdown Wiper Resistance R
W_SD
V
A
= V
DD
, V
B
= 0 V, SHDN = 0, V
DD
= +15 V 170 400 Ω
Common-Mode Leakage I
CM
V
A
= V
B
= V
W
1nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High V
IH
V
DD
= +5 V or +15 V 2.4 V
Input Logic Low V
IL
V
DD
= +5 V or +15 V 0.8 V
Output Logic High V
OH
R
L
= 2.2 kΩ to +5 V 4.9 V
Output Logic Low
7
V
OL
I
OL
= 1.6 mA, V
LOGIC
= +5 V, V
DD
= +15 V 0.4 V
Input Current I
IL
V
IN
= 0 V or +15 V ±1µA
Input Capacitance
5
C
IL
5pF
POWER SUPPLIES
Power Supply Range V
DD
/V
SS
Dual Supply Range ±4.5 ±16.5 V
Power Supply Range V
DD
Single Supply Range, V
SS
= 0 4.5 28 V
Supply Current I
DD
V
IH
= +5 V or V
IL
= 0 V, V
DD
= +5 V 0.0001 0.01 mA
Supply Current I
DD
V
IH
= +5 V or V
IL
= 0 V, V
DD
= +15 V 0.75 2 mA
Supply Current I
SS
V
IH
= +5 V or V
IL
= 0 V, V
SS
= –5 V or –15 V 0.02 0.1 mA
Power Dissipation
8
P
DISS
V
IH
= +5 V or V
IL
= 0 V, V
DD
= +15 V, V
SS
= –15 V 11 30 mW
Power Supply Sensitivity PSS ∆V
DD
= +5 V ± 10%, or ∆V
SS
= –5 V ± 10% 0.05 0.15 %/%
PSS ∆V
DD
= +15 V ± 10% or ∆V
SS
= –15 V ± 10% 0.01 0.02 %/%
DYNAMIC CHARACTERISTICS
5, 9, 10
Bandwidth –3 dB BW_10K R
AB
= 10 kΩ, Code = 40
H
520 kHz
Bandwidth –3 dB BW_50K R
AB
= 50 kΩ, Code = 40
H
125 kHz
Bandwidth –3 dB BW_100K R
AB
= 100 kΩ, Code = 40
H
60 kHz
Total Harmonic Distortion THD
W
V
A
= 1 V rms, V
B
= 0 V, f = 1 kHz 0.005 %
V
W
Settling Time t
S
V
A
= 10 V, V
B
= 0 V, ±1 LSB Error Band 4 µs
Resistor Noise Voltage e
N_WB
R
WB
= 25 kΩ, f = 1 kHz, RS = 0 14 nV√Hz
INTERFACE TIMING CHARACTERISTICS (Applies to All Parts [Notes 5, 11])
Input Clock Pulsewidth t
CH
, t
CL
Clock Level High or Low 120 ns
Data Setup Time t
DS
30 ns
Data Hold Time t
DH
20 ns
CLK to SDO Propagation Delay
12
t
PD
R
L
= 2.2 kΩ, C
L
< 20 pF 10 100 ns
CS Setup Time t
CSS
120 ns
CS High Pulsewidth t
CSW
150 ns
Reset Pulsewidth t
RS
120 ns
CLK Rise to CS Rise Hold Time t
CSH
120 ns
CS Rise to Clock Rise Setup t
CS1
120 ns
–3–REV. 0
AD7376
ORDERING GUIDE
Temperature Package Package
Model kVRange Description Options
AD7376AN10 10 –40°C to +85°C PDIP-14 N-14
AD7376AR10 10 –40°C to +85°C SOL-16 R-16
AD7376ARU10 10 –40°C to +85°C TSSOP-14 RU-14
AD7376AN50 50 –40°C to +85°C PDIP-14 N-14
AD7376AR50 50 –40°C to +85°C SOL-16 R-16
AD7376ARU50 50 –40°C to +85°C TSSOP-14 RU-14
AD7376AN100 100 –40°C to +85°C PDIP-14 N-14
AD7376AR100 100 –40°C to +85°C SOL-16 R-16
AD7376ARU100 100 –40°C to +85°C TSSOP-14 RU-14
AD7376AN1M 1,000 –40°C to +85°C PDIP-14 N-14
AD7376AR1M 1,000 –40°C to +85°C SOL-16 R-16
AD7376ARU1M 1,000 –40°C to +85°C TSSOP-14 RU-14
Die Size: 101.6 mil × 127.6 mil, 2.58 mm × 3.24 mm
Number Transistors: 840
NOTES
11
Typicals represent average readings at +25°C, V
DD
= +15 V, and V
SS
= –15 V.
12
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi-
tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 27. Test Circuit.
13
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V. DNL
specification limits of ±1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 26. Test Circuit.
14
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
15
Guaranteed by design and not subject to production test.
16
Measured at the A terminal. A terminal is open circuit in shutdown mode.
17
I
OL
= 200 µA for the 50 k Ω version operating at V
DD
= +5 V.
18
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
19
Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest band-
width. The highest R value results in the minimum overall power consumption.
10
All dynamic characteristics use V
DD
= +15 V and V
SS
= –15 V.
11
See timing diagram for location of measured values. All input control voltages are specified with t
R
= t
F
= 1 ns (10% to 90% of V
DD
) and timed from a voltage level
of 1.6 V. Switching characteristics are measured using both V
DD
= +5 V or +15 V.
12
Propagation delay depends on value of V
DD
, R
L
and C
L
see Applications section.
Specifications subject to change without notice.
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7376 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS
(T
A
= +25°C, unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +30 V
V
SS
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –16.5 V
V
DD
to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +44 V
V
A
, V
B
, V
W
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . V
SS
, V
DD
A
X
– B
X
, A
X
– W
X
, B
X
– W
X
. . . . . . . . . . . . . . . . . . . ±20 mA
Digital Input Voltages to GND . . . . . . . . . . 0 V, V
DD
+ 0.3 V
Digital Output Voltage to GND . . . . . . . . . . . . . . 0 V, +30 V
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature (T
J
MAX) . . . . . . .+150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C
Package Power Dissipation . . . . . . . . . . . . (T
J
MAX – T
A
)/θ
JA
Thermal Resistance θ
JA
P-DIP (N-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W
SOIC (SOL-16) . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
TSSOP-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C/W
PIN CONFIGURATIONS
PDIP & TSSOP-14 SOL-16
14
13
12
11
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
NC = NO CONNECT
AD7376
W
NC
V
DD
SDO
SHDN
SDI
NC
A
B
V
SS
GND
CS
RS
CLK
14
13
12
11
16
15
10
9
8
1
2
3
4
7
6
5TOP VIEW
(Not to Scale)
AD7376
NC = NO CONNECT
W
NC
V
DD
SDO
SDI
NC
NC
A
B
V
SS
GND
CLK
NC
SHDN
CS
RS
AD7376
–4– REV. 0
PERCENT OF NOMINAL
END-TO-END RESISTANCE – % R
AB
100
75
0032 128
64 96
50
25
R
WB
R
WA
CODE – Decimal
Figure 2. Wiper To End Terminal
Percent Resistance vs. Code
TEMPERATURE – 8C
NOMINAL END-TO-END RESISTANCE – kV
50
–55 –35 105
–15 5 25 45 65 85
49
47
46
45
48
V
DD
= +15V
V
SS
= –15V
R
AB
= 50kV NOMINAL
125
Figure 5. Nominal Resistance vs.
Temperature
SUPPLY VOLTAGE (V
DD
- V
SS
) – Volts
INL – LSB
1.0
51015202530
0.8
0.2
0
0.6
0.4
V
A
= 2.5V
V
B
= 0V
CODE = 40
H
R
AB
= 50kV
Figure 8. Potentiometer Divider
Nonlinearity Error vs. Supply
Voltage
–Typical Performance Characteristics
CODE – Decimal
R-INL ERROR – LSB
0.5
–0.5 0 16 128
32 48 64 80 96 112
0.4
0.1
0
–0.2
–0.4
0.3
0.2
–0.1
–0.3
T
A
= –558C
T
A
= +258C
T
A
= +858C
V
DD
= +15V
V
SS
= –15V
V
A
= 2.5V
V
B
= 0V
R
AB
= 50kV
Figure 3. Resistance Step Position
Nonlinearity Error vs. Code
I
WA
– mA
V
WA
– V
10
0 0.25 20.5 0.75 1 1.25 1.5 1.75
8
4
2
0
6T
A
= +258C
V
DD
= +15V
V
SS
= –15V
R
AB
= 50kV
12
14
20
H
01
H
10
H
40
H
7F
H
CODE = 70
H
Figure 6. Resistance Linearity vs.
Conduction Current
CODE – Decimal
DVWB/DT POTENTIOMETER
MODE TEMPCO – ppm/8C
20
0 16 128
32 48 64 80 96 112
10
0
–5
5
VDD = +15V
VSS = –15V
VA = +2.5V
VB = 0V
–558C < TA < +858C
RAB = 50kV
15
–10
–15
–20
–25
–30
Figure 9.
∆
V
WB
/
∆
T Potentiometer
Mode Tempco
CODE – Decimal
R-DNL ERROR – LSB
0.25
–0.25 0 16 12832 48 64 80 96 112
0.20
0.05
0
–0.10
–0.20
0.15
0.10
–0.05
–0.15
T
A
= –558C
T
A
= +258C
V
DD
= +15V
V
SS
= –15V
R
AB
= 50kV
T
A
= +858C
Figure 4. Relative Resistance Step
Change from Ideal vs. Code
SUPPLY VOLTAGE (V
DD
- V
SS
) – Volts
R_INL – LSB
1.5
51015202530
1.2
0.3
0
0.9
0.6
I
w
= 100mA, T
A
= +258C
DATA = 40
H
Figure 7. Resistance Nonlinearity
Error vs. Supply Voltage
TEMPERATURE – 8C
WIPER CONTACT RESISTANCE – V
1000
0
–55 –35 125
–15 5 25 45 65 105
900
600
500
300
100
800
700
400
200
V
DD
= +5V
V
SS
= 0V
85
V
DD
= +5V
V
SS
= –5V
R
AB
= 50kV
V
DD
= +15V
V
SS
= –15V
Figure 10. Wiper Contact
Resistance vs. Temperature
AD7376
–5–REV. 0
CODE – Decimal
INL NONLINEARITY ERROR – LSB
0.25
–0.25 0 16 12832 48 64 80 96 112
0.20
0.05
0
–0.10
–0.20
0.15
0.10
–0.05
–0.15
T
A
= –558C
T
A
= +258C
V
DD
= +15V
V
SS
= –15V
V
A
= +2.5V
V
B
= 0V
R
AB
= 50kV
T
A
= +858C
Figure 11. Potentiometer Divider
Nonlinearity Error vs. Code
FREQUENCY – Hz
GAIN – dB
1k
–18
–24
–36
–48
–6
–12
–30
–42
AWOP275
BV
SS
= –15V
V
AMPL
= 50mVrms
V
DD
= +15V
CODE = 7F
H
CODE = 40
H
CODE = 20
H
CODE = 10
H
CODE = 08
H
CODE = 04
H
CODE = 02
H
CODE = 01
H
CODE = 00
H
0
10k 100k 1M
R
AB
= 10kV
Figure 14. 10 k
Ω
Gain vs. Frequency
vs. Code
FREQUENCY – Hz
GAIN – dB
1k 10k 1M100k
0
–54
–6
–12
–18
–24
–30
–36
–42
–48 B
A
OP275
01
H
02
H
04
H
08
H
10
H
20
H
CODE = 40
H
CODE = 7F
H
128kHz
AMP = 50mV
V
DD
= +15V
V
SS
= –15V
R
L
= 1MV
R
AB
= 50kV
Figure 17. 50 k
Ω
Gain vs. Frequency
vs. Code
CODE – Decimal
DNL – LSB
0.25
–0.25 0 16 12832 48 64 80 96 112
0.20
0.05
0
–0.10
–0.20
0.15
0.10
–0.05
–0.15
V
DD
= +15V
V
SS
= –15V
V
A
= +2.5V
V
B
= 0V
R
AB
= 50kV
Figure 12. Potentiometer Divider
Differential Nonlinearity Error
vs. Code
FREQUENCY – Hz
GAIN – dB
100
–18
–24
–36
–48
–6
–12
–30
–42
A
B
W
OP275
V
SS
= –15V
V
AMPL
= 50mVrms
V
DD
= +15V
CODE = 7F
H
CODE = 40
H
CODE = 20
H
CODE = 10
H
CODE = 08
H
CODE = 04
H
CODE = 02
H
CODE = 01
H
0
1k 10k
R
AB
= 1MV
100k
R
AB
= 1MV
Figure 15. 1 M
Ω
Gain vs. Frequency
vs. Code
0
5
12
0
27.08
ms
A2 1.6 V DLY
5V 5V H
O
2ms
B
L
w
V
DD
= +15V
V
SS
= –15V
2mS/DIV
CODE = 3F
H
V
A
= 12V
V
B
= 0V
f = 1 MHz
Figure 18. Large Signal Settling Time
CODE – Decimal
RHEOSTAT MODE TEMPCO – ppm/8C
40
–10 0 16 12832 48 64 80 96 112
35
20
15
5
–5
30
25
10
0
V
DD
= +15V
V
SS
= –15V
R
AB
= 50kV
Figure 13.
∆
R
WB
/
∆
T Rheostat Mode
Tempco
259.8ms
50m H
O
5ms
B
Lw
V
DD
= +15V
V
SS
= —15V
5mS/DIV
CODE = 3F
H
40
H
3F
H
V
A
= 2.5V
V
B
= 0V
f = 100 kHz
Figure 16. Midscale Transition Glitch
FREQUENCY – Hz
10
1.0
100 1k 10k 200k
0.001
0.010
0.0005
0.1
V
DD
= +15V
V
SS
= –15V
V
A
= 610V p–p
CODE = 40
H
R
AB
= 50kV
THD – %
NON-INVERTING
MODE TEST
CKT FIG 35
NON-INVERTING
MODE TEST
CKT FIG 36
Figure 19. Total Harmonic Distortion
Plus Noise vs. Frequency
AD7376
–6– REV. 0
FREQUENCY – Hz
GAIN – dB
–18
–24
–36
–48
–6
–12
–30
–42
A
B
W
OP275
V
SS
= –15V
V
AMPL
= 50mVrms
V
DD
= +15V
0
1k 100k
R
AB
= 100kV
1M10k
CODE = 7F
H
40H
20H
10H
08H
04H
02H
01H
Figure 20. 100 k
Ω
Gain vs. Frequency
vs. Code
V
DD
= +15V
V
SS
= –15V
V
AMPL
= 50mVrms
CODE = 40
H
FREQUENCY – Hz
GAIN – dB
0
–0.4
–0.8
–0.2
–0.6
10 100k 1M10k
50kV
100kV
1MV
A
B
W
OP275
–0.1
–0.7
–0.5
–0.3
0.1
–0.9 100 1k
R
AB
= 10kV
Figure 23. Gain Flatness vs Fre-
quency vs. Nominal Resistance R
AB
TEMPERATURE – 8C
–55
1.0
–35 –15 5 25
0.001
0.010
0.1
45 65 85 105 125
SUPPLY CURRENT – mA
I
SS
@V
SS
= –15V, V
LOGIC
= +15V
I
DD
@V
DD
= +5V, V
LOGIC
= +0.8V
I
DD
@V
DD
= +5V, V
LOGIC
= +5V
I
DD
@V
DD
= +15V, V
LOGIC
= 0V
I
DD
@V
DD
= +15V, V
LOGIC
= +5V
R
AB
= 50kV
10
Figure 26. Supply Current (I
DD
, I
SS
)
vs. Temperature
V
DD
= +15V
V
SS
= –15V
V
AMPL
= 50mVrms
CODE = 40
H
FREQUENCY – Hz
GAIN – dB
–18
–24
–36
–48
–6
–12
–30
–42
0
1k 100k 1M10k
50kV
100kV
R
AB
= 1MV
–54
10kV
A
B
W
OP275
Figure 21. –3 dB Bandwidth vs.
Nominal Resistance
+PSRR
V
DD
= +15V610%
V
SS
= –15V
–PSRR
V
DD
= +15V
V
SS
= –15V610%
+PSRR
V
DD
= +5V610%
V
SS
= –5V
–PSRR
V
DD
= +5V
V
SS
= –5V610%
FREQUENCY – Hz
PSRR – dB
10 100 1k 10k 100k
90
80
10
70
60
50
40
30
20
Figure 24. Power Supply Rejection
vs. Frequency
TEMPERATURE – 8C
–55
1.0
–35 –15 5 25
0.001
0.010
0.1
V
DD
= +15V
V
SS
= –15V
45 65 85 105 125
SHUTDOWN CURRENT – mA
Figure 27. I
A_SD
Shutdown Current vs.
Temperature
235.2 s
20m HO2 s
B
Lw
VDD = +15V
VSS = –15V
A2 2.9 V DLY
Figure 22. Clock Feedthrough
VB – Volts
RON– V
250
–15 –10 –5 0 5
200
50
0
150
100
VDD = +5V
VSS = –5V
300
350
400 TA = +258C
SEE FIGURE 38 TEST CIRCUIT
VDD = +15V
VSS = –15V
10 15
Figure 25. Incremental Wiper
Contact Resistance vs.
Common-Mode Voltage
CLOCK FREQUENCY – Hz
SUPPLY CURRENT – mA
1k 10k 100k 1M 10M
4.0
3.5
0.0
3.0
2.5
2.0
1.5
1.0
0.5
DATA = 55
H
DATA = 3F
H
V
DD
= +15V,
V
SS
= –15V
V
A
= +2.5V
V
B
= 0
T
A
= +258C
Figure 28. I
DD
Supply Current vs.
Input Clock Frequency
AD7376
–7–REV. 0
PARAMETRIC TEST CIRCUITS
AW
BV
MS
DUT V+ = V
DD
1LSB = V+/128
V+
Figure 31. Potentiometer Divider Nonlinearity Error Test
Circuit (INL, DNL)
NO CONNECT
IW
AW
BVMS
DUT
Figure 32. Resistor Position Nonlinearity Error (Rheostat
Operation; R-INL, R-DNL)
R
W
=
V+
V
DD
V
W2
- (V
W1
+ I
W
[R
AW
||
R
BW
])
AND V
W2
= V
MS
WHEN I
W
= 1/R
I
W
WHERE V
W1
= V
MS
WHEN I
W
= 0
I
MS
V
W
I
W
= 1V/R
NOMINAL
AW
B
DUT
V+
V
MS
Figure 33. Wiper Resistance Test Circuit
PSS (%/%) =
D
V
MS
%
D
V+%
PSRR (dB) = 20LOG
D
V
MS
D
V+
(
(
V+ = V
DD
610% OR V
SS
610%
V
DD
AW
BV
MS
V+
V
A
Figure 34. Power Supply Sensitivity Test Circuit
(PSS, PSRR)
DUT
A
W
B
V
IN
+18V
V
OUT
–18V
OP275
Figure 35. Inverting Programmable Gain Test Circuit
AB
–18V
DUT
W
V
IN
+18V
V
OUT
OP275
Figure 36. Noninverting Programmable Gain Test Circuit
A
B
–18V
DUT W
V
IN
+18V
V
OUT
OP275
Figure 37. Gain vs. Frequency Test Circuit
SUPPLY VOLTAGE (V
DD
) – Volts
INPUT LOGIC THRESHOLD
VOLTAGE – Volts
3.5
51015202530
3.0
1.0
0
2.5
2.0
V
A
= +5V
V
B
= 0V
V
SS
= 0V
0.5
1.5
Figure 29. Input Logic Threshold Voltage vs.
V
DD
Supply Voltage
V
DD
= +15V
V
SS
= –15V
V
DD
= +5V
V
SS
= 0V OR –5V
V
LOGIC
I
DD
– mA
51015
800
0
1600
400
1200
0
Figure 30. Supply Current (I
DD
) vs. Logic Voltage
AD7376
–8– REV. 0
0.1V
CODE = OO
H
I
SW
V
SS
TO V
DD
W
B
DUT
0.1V
I
SW
R
SW
=
Figure 38. Incremental ON Resistance Test Circuit
ICM
VCM
W
B
DUT
VDD
VSS
NC
A
NC
GND
Figure 39. Common-Mode Leakage Current Test Circuit
OPERATION
The AD7376 provides a 128-position digitally-controlled vari-
able resistor (VR) device. Changing the programmed VR set-
tings is accomplished by clocking in a 7-bit serial data word into
the SDI (Serial Data Input) pin, while CS is active low. When
CS returns high the last seven bits are transferred into the RDAC
latch setting the new wiper position. The exact timing require-
ments are shown in Figure 1.
The AD7376 resets to a midscale by asserting the RS pin, sim-
plifying initial conditions at power-up. Both parts have a power
shutdown SHDN pin which places the RDAC in a zero power
consumption state where terminal A is open circuited and the
wiper W is connected to B, resulting in only leakage currents
being consumed in the VR structure. In shutdown mode the
VR latch settings are maintained so that, returning to opera-
tional mode from power shutdown, the VR settings return to
their previous resistance values.
D6
D5
D4
D3
D2
D1
D0
RDAC
LATCH
&
DECODER
RS
RS
RS
RS
SHDN
A
W
B
RS = RNOMINAL/128
Figure 40. AD7376 Equivalent RDAC Circuit
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance of the RDAC between terminals A and
B are available with values of 10 kΩ, 50 kΩ, 100 kΩ and 1 MΩ.
The final three characters of the part number determine the
nominal resistance value, e.g., 10 kΩ = 10; 50 kΩ = 50; 100 kΩ
= 100; 1 MΩ = 1M. The nominal resistance (R
AB
) of the VR
has 128 contact points accessed by the wiper terminal, plus the
B terminal contact. The 7-bit data word in the RDAC latch is
decoded to select one of the 128 possible settings. The wiper’s first
connection starts at the B terminal for data 00
H
. This B–termi-
nal connection has a wiper contact resistance of 120 Ω. The
second connection (10 kΩ part) is the first tap point located
at 198 Ω (= R
BA
[nominal resistance]/128 + R
W
= 78 Ω + 120 Ω)
for data 01
H
. The third connection is the next tap point repre-
senting 156 + 120 = 276 Ω for data 02
H
. Each LSB data value
increase moves the wiper up the resistor ladder until the last tap
point is reached at 10041 Ω. The wiper does not directly con-
nect to the B terminal. See Figure 40 for a simplified diagram of
the equivalent RDAC circuit.
The general transfer equation that determines the digitally pro-
grammed output resistance between W and B is:
R
WB
(D) = (D)/128
×
R
BA
+ R
W
(1)
where D is the data contained in the 7-bit VR latch, and R
BA
is
the nominal end-to-end resistance.
For example, when V
B
= 0 V and A–terminal is open circuit, the
following output resistance values will be set for the following
VR latch codes (applies to the 10 kΩ potentiometer).
Table I.
DR
WB
(DEC) (V) Output State
127 10041 Full-Scale
64 5120 Midscale (RS = 0 Condition)
1 276 1 LSB
0 198 Zero-Scale (Wiper Contact Resistance)
Note that in the zero-scale condition a finite wiper resistance of
120 Ω is present. Care should be taken to limit the current flow
between W and B in this state to a maximum value of 5 mA to
avoid degradation or possible destruction of the internal switch
contact.
Like the mechanical potentiometer the RDAC replaces, it is
totally symmetrical. The resistance between the wiper W and
terminal A also produces a digitally controlled resistance R
WA
.
When these terminals are used the B–terminal should be tied to
the wiper. Setting the resistance value for R
WA
starts at a maxi-
mum value of resistance and decreases as the data loaded in the
latch is increased in value. The general transfer equation for this
operation is:
R
WA
(D) = (128-D)/128 × R
BA
+ R
W
(2)
where D is the data contained in the 7-bit RDAC latch, and R
BA
is the nominal end-to-end resistance. For example, when V
A
= 0 V
and B–terminal is tied to the wiper W the following output
resistance values will be set for the following RDAC latch codes.
AD7376
–9–REV. 0
Table II.
DR
WA
(DEC) (V) Output State
127 74 Full-Scale
64 5035 Midscale (RS = 0 Condition)
1 9996 1 LSB
0 10035 Zero-Scale
The typical distribution of R
BA
from device to device matching
is process lot dependent having a ±30% variation. The change
in RBA with temperature has a –300 ppm/°C temperature
coefficient.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates an output voltage
proportional to the input voltage applied to a given terminal.
For example connecting A–terminal to +5 V and B–terminal to
ground produces an output voltage at the wiper which can be
any value starting at zero volts up to 1 LSB less than +5 V. Each
LSB of voltage is equal to the voltage applied across terminal
AB divided by the 128-position resolution of the potentiometer
divider. The general equation defining the output voltage with
respect to ground for any given input voltage applied to termi-
nals AB is: V
W
(D) = D/128 × V
AB
+ V
B
Operation of the digital potentiometer in the divider mode
results in more accurate operation over temperature. Here the
output voltage is dependent on the ratio of the internal resis-
tors, not the absolute value; therefore, the drift improves to
5 ppm/°C.
GND
VDD
SDO
AD7376
7-BIT
SERIAL
REGISTER
Q
DCK
7
R
7
SDI
CLK
A
W
B
VSS
SHDN
CS
RS
SHDN
7-BIT
RDAC
LATCH
Figure 41. Block Diagram
DIGITAL INTERFACING
The AD7376 contains a standard three-wire serial input control
interface. The three inputs are clock (CLK), CS and serial data
input (SDI). The positive-edge sensitive CLK input requires
clean transitions to avoid clocking incorrect data into the serial
input register. Standard logic families work well. If mechanical
switches are used for product evaluation they should be de-
bounced by a flip-flop or other suitable means. When CS is
taken active low the clock loads data into the serial register on
each positive clock edge, see Table III. The last seven bits
clocked into the serial register will be transferred to the 7-bit
RDAC latch, see Figure 41. Extra data bits are ignored. The
serial-data-output (SDO) pin contains an open drain n-channel
FET. This output requires a pull-up resistor in order to transfer
data to the next package’s SDI pin. This allows for daisy chain-
ing several RDACs from a single processor serial data line.
Clock period needs to be increased when using a pull-up resistor
to the SDI pin of the following device in the series. Capacitive
loading at the daisy chain node SDO-SDI between devices must
be accounted for to successfully transfer data. When daisy
chaining is used, the CS should be kept low until all the bits of
every package are clocked into their respective serial registers
insuring that the data bits are in the proper decoding location.
This would require 14 bits of data when two AD7376 RDACs
are daisy chained. During shutdown (SHDN) the SDO output
pin is forced to the off (logic high state) to disable power dissi-
pation in the pull up resistor. See Figure 42 for equivalent SDO
output circuit schematic.
Table III. Input Logic Control Truth Table
CLK CS RS SHDN Register Activity
L L H H Enables SR, enables SDO pin.
P L H H Shifts one bit in from the SDI
pin. The seventh previously
entered bit is shifted out of the
SDO pin.
X P H H Loads SR data into 7-bit RDAC
latch.
X H H H No Operation.
X X L H Sets 7-bit RDAC latch to mid-
scale, wiper centered, and SDO
latch cleared.
X H P H Latches 7-bit RDAC latch to
40
H
.
X H H L Opens circuits resistor A–terminal,
connects W to B, turns off SDO
output transistor.
NOTE
P = positive edge, X = don’t care, SR = shift register.
AD7376
–10– REV. 0
The data setup and data hold times in the specification table
determine the data valid time requirements. The last seven bits
of the data word entered into the serial register are held when
CS returns high. At the same time CS goes high it transfers the
7-bit data to the VR latch.
SHDN
SDI
CLK
CK
DQ
RS
CS
SERIAL
REGISTER
RS
SDO
Figure 42. Detail SDO Output Schematic of the AD7376
All digital inputs are protected with a series input resistor and
parallel Zener ESD structure shown in Figure 43. Applies to
digital input pins CS, SDI, SDO, RS, SHDN, CLK
100V
V
DD
LOGIC
Figure 43. Equivalent ESD Protection Circuit
V
SS
A,B,W
V
DD
Figure 44. Equivalent ESD Protection Analog Pins
AD7376
–11–REV. 0
14-Lead Plastic DIP
(N-14)
14
17
8
0.795 (20.19)
0.725 (18.42)
0.280 (7.11)
0.240 (6.10)
PIN 1
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.060 (1.52)
0.015 (0.38)
0.210 (5.33)
MAX 0.130
(3.30)
MIN
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
0.160 (4.06)
0.115 (2.93)
14-Lead TSSOP
(RU-14)
14 8
7
1
0.201 (5.10)
0.193 (4.90)
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
PIN 1
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.0118 (0.30)
0.0075 (0.19)
0.0256
(0.65)
BSC
0.0433
(1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
8°
0°
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Wide Body SOIC
(R-16)
16 9
81
0.4133 (10.50)
0.3977 (10.00)
0.4193 (10.65)
0.3937 (10.00)
0.2992 (7.60)
0.2914 (7.40)
PIN 1
SEATING
PLANE
0.0118 (0.30)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.1043 (2.65)
0.0926 (2.35)
0.0500
(1.27)
BSC 0.0125 (0.32)
0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0291 (0.74)
0.0098 (0.25) x 45°
–12–
C3163–8–10/97
PRINTED IN U.S.A.