iy Integrated Circuit Systems, Inc. ICS9176 Low Skew Output Buffer General Description The 1CS9176 is designed specifically to support the tight timing requirements of high-performance microprocessors and chip sets. Because the jitter of the device is limited to +250ps. the ICS9176 is ideal for clocking Pentium systems. The 10 high drive (40mA), low-skew (+250ps} outputs make the 1CS9176 a perfect fit for PCI clocking requirements. The ICS9176 has 10 outputs synchronized in phase and fre- quency to an input clock. The internal phase locked loop (PLL) acts either as a 1X clock multiplier or a 1/2X clock multiplier depending on the state of the input control pins TO and TL. With metal mask options, any type of ratio between the input clock and output clock can be achieved, including 2X. The PLL maintains the phase and frequency relationship be- tween the input clock and the outputs by externally feeding back FBOUT to FBIN. Any change in the input will be tracked by all 10 outputs. However, the change at the outputs will happen smoothly so no glitches will be present on any driven input. The PLL circuitry matches rising edges of the input clock and the output clock. Since the input to FBIN skew is guaran- teed to +500ps, the part acts as a zero delay buffer. The ICS9176 has a total of eleven outputs. Of these, FROUT is dedicated as the feedback into the PLL and another, Q/2. has an output frequency half that of the remaining nine. These nine outputs can either be running at the same speed as the input, or at half the frequency of the input. With Q/2 as the feedback to FBIN, the nine Q outputs will be running at twice the input frequency in the normal divide-by-1 mode. In this case, the output can go to 120 MHz with a 60 MHz input clock. The maximum rise and fall time of an output is l4ns and each is TTL-compatible with a 40mA symmetric drive. The ICS9176 is fabricated using CMOS technology which results in much lower power consumption and cost compared with the gallium arsenide based 1086E. The typical operating current for the ICS9176 is 60mA versus 115mA for the GAI1086E. Features 189176-01 is pin compatible with Triquint GA1086 e +500ps skew (max) between input and outputs +250ps skew (max) between outputs 10 symmetric. TLL-compatible outputs 28-pin PLCC surface mount package High drive, 4OmA outputs Power-down option Output frequency range 20 MHz to 120 MHz Input frequency range 20 MHz to 100 MHz Ideal for PCI bus applications Selection Table T! To DESCRIPTION 0 Power-down l Test Mode (PLL Off CLK=outputs) l oO Normal (PLL On) I |__| Divide by 2 Mode Block Diagram FBOUT Qi Q2 CLK Q3 DIVIDE LOGIC Q5 6 Q7 Q8 Q@ Q/2 TO CONTROL 1 LOGIC Pentium is a trademark of intel Corporatian. 1C$9176RevBO92794 D-57ICS9176 Pin Configuration FBIN 1 CLK VDD NC NC ICS9176 Pin Descriptions GND VDO Qg Q8 Q7 Q6 VDD GND (pin 1) L PIN NUMBER PIN NAME TYPE DESCRIPTION 1 GND - GROUND. 2 [Q8 _| Output Output clock 8. | 3 1Q9 Output | Output clock 9. 4 [VDD - Power supply (+5V). | 5 GND GROUND. | 6 NC No Connect. | 7 NC - No Connect. | 8 VDD - Power supply (+5V). 9 CLK Input Input for reference clock. | 10 TI Input T1 selects normal operation, power-down, or test mode. 11 FBIN Input FEEDBACK INPUT from output FBOUT. 7 12 TO | Inputs TO selects normal operation, power-down, or test mode. 13 VDD - Power Supply (+5V). 14 Q/2 Output Half-clock output. a 15 GND - GROUND. B 16 FBOUT Output FEEDBACK OUTPUT to Input FBIN. 17 Ql Output Output clock 1. - 18 VDD - Power Supply (+5V). a 19 GND - GROUND. , 20 Q2 Output Output clock 2. z 21 Q3 Output | Output clock 3. E 22 VDD - 'Power supply (+5V). , 23 Q4 Output Output clock 4. Ez 24 Q5 Output Output clock 5. a 25 GND - GROUND. | 26 VDD - Power Supply (+5V). | 27 Q6 Output Output clock 6. 28 Q7 Output Output clock 7. D-58ICS9176 Timing Diagrams INPUT CLOCK pe Qt - a9 7 TF Of Timing in Divide by 1 Mode /D INPUT CLOCK __| LS LJ L__| LJ oo t Li J LJ e_| Ovi_tf- Timing in Divide by 2 Mode INPUT CLOCK Q1-Q9 _ PLL Q/2 Timing in Eliminate by Test Mode Note: In test mode, the VCOs are bypassed. The test clock input is simply buffered, then output. The part is transparent. Damage to the device may occur if an output is shorted or forced to ground or VDD. INPUT CLOCK _ Q1 -Q9 Q/2 Timing in Power-down Mode D-59iCS9176 Absolute Maximum Ratings VDD referenced toGND ..................00., 1Vv Operating Temperature under bias............... OC to +70C Storage Temperature...........00...20...02000, -65C to +150C Voltage on V/O pins referenced to GND........... GND -0.5V to VDD +0.5V Power Dissipation...........0.. 0.00000 eee eee 0.5 Watts Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics DC Characteristics Vpp = +5V+5%, Ta=0C to 70C unless otherwise stated) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX ._ UNITS Input Low Voltage Vit Vpp=5V - - 0.8 Vv Input High Voltage Vin Vpp=5V 2.0 - - | Vv Input Current ij Vin=0V, 5V -5 : 5 BA Output Low Voltage Vou @IoL=l4mA - 0.25 0.4 Vv Output Low Current lot @VoL=0.8V , 33 42 - mA Output High Voltage Vou @lou=-38mA 2.4 : - Vv Output High Current lou @VonH=2.0V ! - -59 -41 mA D-60ICS9176 AC Characteristics PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS (Input Clock Pulse Width* CLKw | Vdd=4.5V. fcLK=100 MHz 2.5 - 75 . ns Output Rise time, 0.8 to tr 15 pf load - 0.7 1 | ns 2.0V* Rise time. 20% to 80% | t :15pfload - L5 2 ns Vpp* Output Fall time, 2.0V to tf 15 pf load - 0.7 I ns 0.8V* Fall time, 80% to 20% tr 15 pf load | - 1.2 2 ns Vpp* Output Duty cycle* dt 15 pf load 45 49/51 55 % Jitter, 1 sigma* Tis 60 ps Jitter, absolute* Tabs -250 +100 250 ps Input Frequency fi 20 100 MHz Output Frequency fo 20 120 MHz (Q outputs) FBIN to IN skew tskew| Note 1, 3. Input rise time -500 250 0 ps <3ns Li Skew between any 2 tskew2 Note 1, 3. -250 50 250 ps outputs at same frequency Skew between any | 3 ns output and Q/2 NOTES: 1. All skew specifications are measured with a 50Q transmission line, load terminated with 502 to 1.4V. 2. Duty cycle measured at 1.4V. 3. Skew measured at [.4V on rising edges. Loading must be equal on outputs. * Guaranteed by design and characterization. Not subject to 100% test. D-61ICS9176 Applications FBOUT is normally connected to FBIN to facilitate input to output skew control. However. there is no requirement that the external feedback connection be a direct hardwire from an output pin to the FBIN pin. As long as the signal at FBIN is derived directly from the FBOUT pin and maintains its fre- quency. additional delays can be accommodated. The clock phase of the outputs (rising edge) will be adjusted so that the phase of FBIN and the input clock will be the same. See Figure 1 for an example. FBIN ICS9176 66 MHz 33 MHz! +2 66 MHz Figure 1 In Figure |, the propagation delay through the divide by 2 circuit is eliminated. The internal phase-locked loop will adjust the output clock on the ICS9176 to ensure zero phase delay between the FBIN and CLK signals, as a result, the nsing edge at the output of the divide by two circuit will be aligned with the rising edge of the 66 MHz input clock. This type of configuration can be used to eliminate propagation delay as long as the signal at FBIN is continuous and is not gated or conditional. Ordering Information ICS9176-01CQ28 Example: ICS XXXX-PPP M X#W Lead Count=1. 2 or 3 digits Package Type Q=PLCC Prefix The ICS9176 is also ideal for clocking multi-processor sys- tems. The 10 outputs can be used to synchronize the operation of CPU cache and memory banks operating at different speeds. Figure 2 depicts a 2-CPU system in which processors and associated peripherals are operating at 66 MHz. Each of the nine outputs operating at 66 MHz are fully utilized to drive the appropriate CPU, cache and memory control logic. The 33 MHz output is used to synchronize the operation of the slower memory bank to the restart of the system. FBOUT SYSTEM CLOCK Qi Q2 Q3 Q4 MEMORY CONTROL Q5 Q6 Q7 GND vDD a8 ag Figure 2 Lead Count & Package Width W=.3 SOIC or .6 DIP; None=Standard Width Pattern Number (2 or 3 digit number for parts with ROM code patterns) Device Type (consists of 3 or 4 digit numbers) ICS, AV=Standard Device: GSP=Genlock Device D-62