ESMT
F25L04UA
Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009
Revision: 1.2 7/25
Instructions
Instructions are used to Read, Write (Erase and Program), and
configure the F25L04UA. The instruction bus cycles are 8 bits
each for commands (Op Code), data, and addresses. Prior to
executing any Byte-Program, Auto Address Increment (AAI)
programming, Sector-Erase, Block-Erase, or Chip-Erase
instructions, the Write-Enable (WREN) instruction must be
executed first. The complete list of the instructions is provided in
Table 5. All instructions are synchronized off a high to low
transition of CE . Inputs will be accepted on the rising edge of
SCK starting with the most significant bit. CE must be driven
low before an instruction is entered and must be driven high after
the last bit of the instruction has been shifted in (except for Read,
Read-ID and Read-Status-Register instructions). Any low to high
transition on CE , before receiving the last bit of an instruction
bus cycle, will terminate the instruction in progress and return the
device to the standby mode.
Instruction commands (Op Code), addresses, and data are all
input from the most significant bit (MSB) first.
TABLE 5: DEVICE OPERATION INSTRUCTIONS
Bus Cycle4
1 2 3 4 5 6
Cycle Type/
Operation1,2
Max
Freq
MHz SIN S
OUT SIN SOUT SIN S
OUT SIN S
OUT S
IN S
OUT SIN SOUT
Read 33 03H Hi-Z A23-A16 Hi-Z A15-A8Hi-Z A7-A0Hi-Z X DOUT
High-Speed-Read 0BH Hi-Z A23-A16 Hi-Z A15-A8Hi-Z A7-A0Hi-Z X X X DOUT
Sector-Erase4,5 20H Hi-Z A23-A16 Hi-Z A15-A8Hi-Z A7-A0Hi-Z - -
Chip-Erase5 60H Hi-Z - - - - - - - -
Byte-Program5 02H Hi-Z A23-A16 Hi-Z A15-A8Hi-Z A7-A0Hi-Z DIN Hi-Z
Auto Address Increment -
word programming (AAI)6 AFH Hi-Z A23-A16 Hi-Z A15-A8Hi-Z A7-A0Hi-Z DIN Hi-Z
Read-Status-Register
(RDSR) 05H Hi-Z X DOUT - Note7- Note7 - Note7
Enable-Write-Status-Register
(EWSR)8 50H Hi-Z - - - - - - - -
Write-Status-Register
(WRSR)8 01H Hi-Z Data Hi-Z - - -. - - -
Write-Enable (WREN) 11 06H Hi-Z - - - - - - - -
Write-Disable (WRDI) 04H Hi-Z -
Jedec-Read-ID (JEDEC-ID) 10
50
and
75
and
100
9FH Hi-Z X 8CH X 8CH X 8CH - -
1. Operation: SIN = Serial In, SOUT = Serial Out
2. X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary)
3. One bus cycle is eight clock periods.
4. Sector addresses: use AMS-A12, remaining addresses can be VIL or VIH
5. Prior to any Byte-Program, AAI-Program, Sector-Erase ,or Chip-Erase operation, the Write-Enable (WREN) instruction must be
executed.
6. To continue programming to the next sequential address location, enter the 8-bit command, AFH, followed by the data to be
programmed.
7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE .
8. The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction
of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR instruction to make both
instructions effective.
9. The Jedec-Read-ID is continuous with on going clock cycles until terminated by a low to high transition on CE .
10. The Jedec-Read-ID is output first byte 8CH as manufacture ID; second byte 8CH as top memory type; third byte 8CH as memory
capacity.
11. The Write-Enable (WREN) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each other.
The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both instructions
effective. Both EWSR and WREN can enable WRSR, user just need to execute one of it. A successful WRSR can reset WREN.