TDA8766G_C1_S1 - Philips Semiconductors / NXP Semiconductors

DATA SH EET

Product speciﬁcation

Supersedes data of 1995 Mar 22

File under Integrated Circuits, IC02

1996 Mar 20

INTEGRATED CIRCUITS

TDA8766

10-bit high-speed 2.7 to 5.25 V

analog-to-digital converter

1996 Mar 20 2

Philips Semiconductors Product speciﬁcation

10-bit high-speed 2.7 to 5.25 V

analog-to-digital converter TDA8766

FEATURES

•10-bit resolution

•2.7 to 5.25 V operation

•Sampling rate up to 20 MHz

•DC sampling allowed

•High signal-to-noise ratio over a large analog input

frequency range (9.3 effective bits at 1.0 MHz full-scale

input at fclk = 20 MHz)

•In range (IR) CMOS output

•CMOS/TTL compatible digital inputs and outputs

•External reference voltage regulator

•Power dissipation only 53 mW (typical)

•Low analog input capacitance, no buffer amplifier

required

•Standby mode

•No sample-and-hold circuit required.

APPLICATIONS

High-speed analog-to-digital conversion for:

•Video data digitizing

•Camera

•Camcorder

•Radio communication.

GENERAL DESCRIPTION

The TDA8766 is a 10-bit high-speed analog-to-digital

converter (ADC) for professional video and other

applications. It converts with 2.7 to 5.25 V operation the

analog input signal into 10-bit binary-coded digital words at

a maximum sampling rate of 20 MHz. All digital inputs and

outputs are CMOS compatible. A standby mode allows

reduction of the device power consumption down to 4 mW.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

VDDA analog supply voltage 2.7 3.3 5.25 V

VDDD1 digital supply voltage 1 2.7 3.3 5.25 V

VDDD2 digital supply voltage 2 2.7 3.3 5.25 V

VDDO output stages supply voltage 2.5 3.3 5.25 V

IDDA analog supply current −7.5 10 mA

IDDD digital supply current −7.5 10 mA

IDDO output stages supply current fclk = 20 MHz; CL= 20 pF;

ramp input −12mA

INL integral non-linearity fclk = 20 MHz; ramp input −±1±2 LSB

DNL differential non-linearity fclk = 20 MHz; ramp input −±0.25 ±0.7 LSB

fclk(max) maximum clock frequency 20 −−MHz

Ptot total power dissipation VDDA =V

DDD =V

DDO = 3.3 V −53 73 mW

TYPE

NUMBER PACKAGE

NAME DESCRIPTION VERSION

TDA8766G LQFP32 plastic low profile quad flat package; 32 leads; body 5 ×5×1.4 mm SOT401-1

1996 Mar 20 3

Philips Semiconductors Product speciﬁcation

10-bit high-speed 2.7 to 5.25 V

analog-to-digital converter TDA8766

BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

RLAD

VRB

VSSA VSSD2 VSSO VSSD1

VRM

VRT

VDDD2

VDDA

27 D4

23 D1

22 D0

IN RANGE LATCH

CMOS

OUTPUTS

LATCHES

ANALOG -TO - DIGITAL

CONVERTER

CLOCK DRIVER

MLC853

CMOS

OUTPUT

CLK

STDBY

TDA8766

20 VDDO

analog

ground digital

ground 2

321

output

ground digital

ground 1

analog

voltage input data outputs

LSB

MSB

4VDDD1

output

1996 Mar 20 4

Philips Semiconductors Product speciﬁcation

10-bit high-speed 2.7 to 5.25 V

analog-to-digital converter TDA8766

PINNING

SYMBOL PIN DESCRIPTION

D9 1 data output; bit 9 (MSB)

IR 2 in range data output

VSSD1 3 digital ground 1

VDDD1 4 digital supply voltage 1 (2.7 to 5.25 V)

CLK 5 clock input

STDBY 6 standby mode input

VDDA 7 analog supply voltage (2.7 to 5.25 V)

n.c. 8 not connected

VSSA 9 analog ground

VRB 10 reference voltage BOTTOM input

VRM 11 reference voltage MIDDLE

n.c. 12 not connected

n.c. 13 not connected

VI14 analog input voltage

VRT 15 reference voltage TOP input

OE 16 output enable input

n.c. 17 not connected

VDDD2 18 digital supply voltage 2 (2.7 to 5.25 V)

VSSD2 19 digital ground 2

VDDO 20 positive supply voltage for output

stage (2.5 to 5.25 V)

VSSO 21 digital output ground

D0 22 data output; bit 0 (LSB)

D1 23 data output; bit 1

n.c. 24 not connected

D2 25 data output; bit 2

D3 26 data output; bit 3

D4 27 data output; bit 4

D5 28 data output; bit 5

D6 29 data output; bit 6

D7 30 data output; bit 7

D8 31 data output; bit 8

n.c. 32 not connected

SYMBOL PIN DESCRIPTION

Fig.2 Pin configuration.

handbook, full pagewidth

TDA8766

MLC854

index

corner

VDDD1

VSSD1

CLK

STDBY

DDA VDDD2

VSSD2

VDDO

VSSO

n.c.

SSA

n.c.

1996 Mar 20 5

Philips Semiconductors Product speciﬁcation

10-bit high-speed 2.7 to 5.25 V

analog-to-digital converter TDA8766

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Note

1. The supply voltages VDDA, VDDD and VDDO may have any value between −0.3 V and +7.0 V provided that the supply

voltage differences ∆VDD are respected.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is

desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VDDA analog supply voltage note 1 −0.3 +7.0 V

VDDD1, VDDD2 digital supply voltages note 1 −0.3 +7.0 V

VDDO output stages supply voltage note 1 −0.3 +7.0 V

∆VDD supply voltage difference

VDDA −VDDD −1.0 +4.0 V

VDDD −VDDO −1.0 +4.0 V

VDDA −VDDO −1.0 +4.0 V

VIinput voltage referenced to VSSA −0.3 +7.0 V

Vclk(p-p) AC input voltage for switching

(peak-to-peak value) referenced to VSSD −VDDD V

IOoutput current −10 mA

Tstg storage temperature −55 +150 °C

Tamb operating ambient temperature −20 +75 °C

Tjjunction temperature −+150 °C

SYMBOL PARAMETER VALUE UNIT

Rth j-a thermal resistance from junction to ambient in free air 90 K/W

1996 Mar 20 6

Philips Semiconductors Product speciﬁcation

10-bit high-speed 2.7 to 5.25 V

analog-to-digital converter TDA8766

CHARACTERISTICS

VDDA =V

7to V9= 3.3 V; VDDD =V

4to V3=V

18 to V19 = 3.3 V; VDDO =V

20 to V21 = 3.3 V; VSSA,V

SSD and VSSO

short-circuited together; Vi(p-p) = 1.83 V; CL= 20 pF; Tamb =0to+70°C; typical values measured at Tamb =25°C;

unless otherwise speciﬁed.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

VDDA analog supply voltage 2.7 3.3 5.25 V

VDDD1 digital supply voltage 1 2.7 3.3 5.25 V

VDDD2 digital supply voltage 2 2.7 3.3 5.25 V

VDDO output stages supply voltage 2.5 3.3 5.25 V

∆VDD voltage difference

VDDA −VDDD −0.2 −+0.2 V

VDDA −VDDO −0.2 −+3.0 V

VDDD −VDDO −0.2 −+3.0 V

IDDA analog supply current −7.5 10 mA

IDDD digital supply current −7.5 10 mA

IDDO output stages supply current fclk = 20 MHz;

ramp input; CL=20pF −12 mA

Inputs

CLOCK INPUT CLK (REFERENCED TO VSSD); see note 1

VIL LOW level input voltage 0 −0.3VDDD V

VIH HIGH level input voltage 0.7VDDD −VDDD V

VDDD ≤3.6 V 0.6VDDD −VDDD V

IIL LOW level input current Vclk = 0.3VDDD −10+1µA

IH HIGH level input current Vclk = 0.7VDDD −−5µA

Iinput impedance fclk = 20 MHz −4−kΩ

CIinput capacitance fclk = 20 MHz −3−pF

INPUTS OE AND STDBY (REFERENCED TO VSSD); see Table 3

VIL LOW level input voltage 0 −0.3VDDD V

VIH HIGH level input voltage 0.7VDDD −VDDD V

VDDD ≤3.6 V 0.6VDDD −VDDD V

IIL LOW level input current VIL = 0.3VDDD −1−− µA

IH HIGH level input current VIH = 0.7VDDD −−+1 µA

VI(ANALOG INPUT VOLTAGE REFERENCED TO VSSA)

IIL LOW level input current VI=V

RB −0−µA

IH HIGH level input current VI=V

RT −35 −µA

Iinput impedance fi= 1 MHz −5−kΩ

CIinput capacitance fi= 1 MHz −8−pF

1996 Mar 20 7

Philips Semiconductors Product speciﬁcation

10-bit high-speed 2.7 to 5.25 V

analog-to-digital converter TDA8766

Reference voltages for the resistor ladder; see Table 1

VRB reference voltage BOTTOM 1.1 1.2 −V

VRT reference voltage TOP VTOP ≤VDDA 2.7 3.3 VDDA V

Vdiff differential reference voltage

VRT −VRB

1.5 2.1 2.7 V

Iref reference current −7.2 −mA

RLAD resistor ladder −290 −Ω

TCRLAD temperature coefﬁcient of the resistor

ladder −1860 −ppm

−539 −mΩ/K

VosB offset voltage BOTTOM note 2 −135 −mV

VosT offset voltage TOP note 2 −135 −mV

Vi(p-p) analog input voltage

(peak-to-peak value) note 3 1.4 1.83 2.4 V

Outputs

DIGITAL OUTPUTS D9 TO D0 AND IR (REFERENCED TO VSSD)

VOL LOW level output voltage IO=1mA 0 −0.5 V

VOH HIGH level output voltage IO=−1mA V

DDO −0.5 −VDDO V

IOZ output current in 3-state mode 0.5V<V

O<V

DDO −20 −+20 µA

Switching characteristics

CLOCK INPUT CLK; see Fig.4; note 1

fclk(max) maximum clock frequency 20 −− MHz

tCPH clock pulse width HIGH 15 −− ns

tCPL clock pulse width LOW 15 −− ns

Analog signal processing

LINEARITY

INL integral non-linearity fclk = 20 MHz;

ramp input; (see Fig.6) −±1±2 LSB

DNL differential non-linearity fclk = 20 MHz;

ramp input; (see Fig.7) −±0.25 ±0.7 LSB

INPUT SET RESPONSE (fclk = 20 MHz; see Fig.8; note 4)

tSTLH analog input settling time

LOW-to-HIGH full-scale square wave −46 ns

STHL analog input settling time

HIGH-to-LOW full-scale square wave −46 ns

HARMONICS;(f

clk =20MHZ; see Fig.9; note 5)

THD total harmonic distortion fi= 1 MHz −−63 −dB

SIGNAL-TO-NOISE RATIO; see Fig.9; note 5

S/N signal-to-noise ratio (full scale) without harmonics;

fclk = 20 MHz;

fi= 1 MHz

−60 −dB

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1996 Mar 20 8

Philips Semiconductors Product speciﬁcation

10-bit high-speed 2.7 to 5.25 V

analog-to-digital converter TDA8766

Notes

1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock

must not be less than 1 ns.

2. Analog input voltages producing code 0 up to and including 1023:

a) VosB (voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and

the reference voltage BOTTOM (VRB) at Tamb =25°C.

b) VosT (voltage offset TOP) is the difference between VRT (reference voltage TOP) and the analog input which

produces data outputs equal to 1023 at Tamb =25°C.

3. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities

of the converter reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to

pins VRB and VRT via offset resistors ROB and ROT as shown in Fig.3.

a) The current flowing into the resistor ladder is IL= and the full-scale input range at the converter,

to cover code 0 to code 1023, is

b) Since RL, ROB and ROT have similar behaviour with respect to process and temperature variation, the ratio

will be kept reasonably constant from part to part. Consequently variation of the output codes

at a given input voltage depends mainly on the difference VRT −VRB and its variation with temperature and supply

voltage. When several ADCs are connected in parallel and fed with the same reference source, the matching

between each of them is then optimized.

EFFECTIVE BITS; see Fig.9; note 5

EB effective bits fclk = 20 MHz

fi= 300 kHz −9.5 −bits

fi= 1 MHz −9.3 −bits

fi= 3.58 MHz −8.0 −bits

Timing (fclk = 20 MHz; CL= 20 pF); see Fig.4; note 6

tds sampling delay time −−5ns

houtput hold time 5 −− ns

tdoutput delay time VDDO = 4.75 V 8 12 15 ns

VDDO = 3.15 V 8 17 20 ns

VDDO = 2.7 V 8 21 24 ns

3-state output delay times; see Fig.5

tdZH enable HIGH −14 18 ns

tdZL enable LOW −16 20 ns

tdHZ disable HIGH −16 20 ns

tdLZ disable LOW −14 18 ns

Standby mode output delay times

tdSTBLH standby (LOW-to-HIGH transition) −−200 ns

tdSTBHL start-up (HIGH-to-LOW transition) −−500 ns

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

VRT VRB

–

ROB RLROT

------------------------------------------

VIRLIL

×RL

ROB RLROT

------------------------------------------ VRT VRB

–()0.871 VRT VRB

–()×=×==

OB RLROT

-----------------------------------------

1996 Mar 20 9

Philips Semiconductors Product speciﬁcation

10-bit high-speed 2.7 to 5.25 V

analog-to-digital converter TDA8766

4. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale

input (square-wave signal) in order to sample the signal and obtain correct output data.

5. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent

fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency

(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB ×6.02 + 1.76 dB.

6. Output data acquisition: the output data is available after the maximum delay time of td.

Fig.3 Explanation of note 3.

handbook, halfpage

RLAD

ROT

VRT

VRM

VRB

ROB

code 1023

code 0

MGD281

1996 Mar 20 10

Philips Semiconductors Product speciﬁcation

10-bit high-speed 2.7 to 5.25 V

analog-to-digital converter TDA8766

Table 1 Output coding and input voltage (typical values; referenced to VSSA)

Table 2 Mode selection

Table 3 Standby selection

STEP VI(p-p)

(V) IR BINARY OUTPUT BITS

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Underﬂow <1.335 00000000000

0 1.335 10000000000

1 . 10000000001

. . ...........

1022 . 11111111110

1023 3.165 11111111111

Overﬂow >3.165 01111111111

OE D9 TO D0 IR

1 high impedance high impedance

0 active; binary active

STDBY D9 TO D0 IDDA +I

DDD (typ.)

1 last logic state 1.2 mA

0 active 15 mA

Fig.4 Timing diagram.

handbook, full pagewidth

sample N + 1

sample N

CLK

MGD346

sample N + 2

50%

DATA

D0 to D9

CPH

tCPL

VDDO

0 V

50%

DATA

N + 1

DATA

N - 1

DATA

N - 2

1996 Mar 20 11

Philips Semiconductors Product speciﬁcation

10-bit high-speed 2.7 to 5.25 V

analog-to-digital converter TDA8766

Fig.5 Timing diagram and test conditions of 3-state output delay time.

fOE = 100 kHz.

handbook, full pagewidth

MLC855

50 %

HIGH

LOW

dZH

dHZ

50 %

HIGH

LOW

dZL

dLZ

10 %

90 %

output

data

VDDD

output

data

3.3 kΩ

20 pF

VDDD

TDA8766

TEST

dLZ

dZL

dHZ

dZH

DDD

GND

1996 Mar 20 12

Philips Semiconductors Product speciﬁcation

10-bit high-speed 2.7 to 5.25 V

analog-to-digital converter TDA8766

Fig.6 Typical integral non-linearity (INL) performance.

handbook, full pagewidth

1023

−0.6 0 400 600 800 1000 1100200

MLD115

0.4

−0.2

−0.4

0.2

0.6

(LSB)

f (codes)

Fig.7 Typical differential non-linearity (DNL) performance.

handbook, full pagewidth

1023

−0.25 0 400 600 800 1000 1100200

MLD116

0.25

−0.05

−0.15

0.15

0.05

(LSB)

f (codes)

1996 Mar 20 13

Philips Semiconductors Product speciﬁcation

10-bit high-speed 2.7 to 5.25 V

analog-to-digital converter TDA8766

Fig.8 Analog input settling-time diagram.

handbook, full pagewidth

MBD875

50 %

STLH

5 ns

code 0

code 1023

50 %

2 ns

50 %

5 ns

STHL

50 %

2 ns

CLK

Fig.9 Typical Fast Fourier Transform (fclk = 20 MHz; fi= 1 MHz).

Effective bits: 9.59; THD = −76.60 dB.

Harmonic levels (dB): 2nd = −81.85; 3rd = −87.56; 4th = −88.81; 5th = −88.96; 6th = −79.58.

handbook, full pagewidth

120 0 2.5 3.76 5.01 7.51 8.761.25 6.26

MLD117

100

(dB)

f (MHz)

1996 Mar 20 14

Philips Semiconductors Product speciﬁcation

10-bit high-speed 2.7 to 5.25 V

analog-to-digital converter TDA8766

INTERNAL PIN CONFIGURATIONS

Fig.10 CMOS data and In Range (IR) outputs.

handbook, halfpage

MLC856

VDDO

D9 to D0

SSO

Fig.11 Analog inputs.

handbook, halfpage

MLC857

VDDA

VSSA

Fig.12 OE (STDBY) input.

handbook, halfpage

MLC858

VDDO

VSSO

(STDBY)

Fig.13 VRB, VRM and VRT.

handbook, halfpage

MLC859

VRB

VRM

VDDA

VSSA

VRT

LAD

1996 Mar 20 15

Philips Semiconductors Product speciﬁcation

10-bit high-speed 2.7 to 5.25 V

analog-to-digital converter TDA8766

Fig.14 CLK input.

handbook, halfpage

VDDD

VSSD

CLK

MLC860

1/2VDDD

1996 Mar 20 16

Philips Semiconductors Product speciﬁcation

10-bit high-speed 2.7 to 5.25 V

analog-to-digital converter TDA8766

APPLICATION INFORMATION

Additional application information will be supplied upon request (please quote number

“AN96012”

Fig.15 Application diagram.

The analog and digital supplies should be separated and decoupled.

The external voltage reference generator must be built such that a good supply voltage ripple rejection is achieved with respect to the LSB value.

Eventually, the reference ladder voltages can be derived from a well regulated VDDA supply through a resistor bridge and a decoupled capacitor.

(1) VRB, VRM and VRT are decoupled to VSSA.

(2) Pins 8, 12, 13, 17, 24 and 32 should be connected to the closest ground pin in order to prevent noise influence.

(3) When VRM is not used, pin 11 can be left open, avoiding the decoupling capacitor. In any case, pin 11 must not be grounded.

(4) When analog input signal is AC coupled, an input bias or a clamping level must be applied to VI input (pin 14).

handbook, full pagewidth

TDA8766

MLC861

VDDD1

VSSD1

CLK

STDBY

DDA

VSSA

VDDD2

VSSD2

VDDO

VSSO

n.c.

VRB

VRM

12 13 14

VRT

(2)

n.c.(2) n.c.(2)

(1)

(3)

(4)

(1) (1)

(2)

n.c.(2)

100

VSSA

100

VSSA

100

32 31 30 29 28 27 26 25

D5 D4 D3n.c.(2) D2D8 D7 D6

1996 Mar 20 17

Philips Semiconductors Product speciﬁcation

10-bit high-speed 2.7 to 5.25 V

analog-to-digital converter TDA8766

PACKAGE OUTLINE

0.2

UNIT A

max. A1A2A3bpcE

(1) eH

pZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC EIAJ

mm 1.60 0.15

0.05 1.5

1.3 0.25 0.27

0.17 0.18

0.12 5.1

4.9 0.5 7.15

6.85 1.0 0.95

0.55 7

0.12 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75

0.45

SOT401-1 95-12-19

97-08-04

D(1) (1)(1)

5.1

4.9

7.15

6.85

0.95

0.55

vMB

vMA

24 17

detail X

(A )

0 2.5 5 mm

scale

LQFP32: plastic low profile quad flat package; 32 leads; body 5 x 5 x 1.4 mm SOT401-1

pin 1 index

1996 Mar 20 18

Philips Semiconductors Product speciﬁcation

10-bit high-speed 2.7 to 5.25 V

analog-to-digital converter TDA8766

SOLDERING

Introduction

There is no soldering method that is ideal for all IC

packages. Wave soldering is often preferred when

through-hole and surface mounted components are mixed

on one printed-circuit board. However, wave soldering is

not always suitable for surface mounted ICs, or for

printed-circuits with high population densities. In these

situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.

A more in-depth account of soldering ICs can be found in

our

“IC Package Databook”

(order code 9398 652 90011).

Reﬂow soldering

Reflow soldering techniques are suitable for all LQFP

packages.

Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied

to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,

thermal conduction by heated belt. Dwell times vary

between 50 and 300 seconds depending on heating

method. Typical reflow temperatures range from

215 to 250 °C.

Preheating is necessary to dry the paste and evaporate

the binding agent. Preheating duration: 45 minutes at

45 °C.

Wave soldering

Wave soldering is not recommended for LQFP packages.

This is because of the likelihood of solder bridging due to

closely-spaced leads and the possibility of incomplete

solder penetration in multi-lead devices.

If wave soldering cannot be avoided, the following

conditions must be observed:

•A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)

soldering technique should be used.

•The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves

downstream and at the side corners.

Even with these conditions, do not consider wave

soldering LQFP packages LQFP48 (SOT313-2),

LQFP64 (SOT314-2) or LQFP80 (SOT315-1).

During placement and before soldering, the package must

be fixed with a droplet of adhesive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured.

Maximum permissible solder temperature is 260 °C, and

maximum duration of package immersion in solder is

10 seconds, if cooled to less than 150 °C within

6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally-

opposite end leads. Use only a low voltage soldering iron

(less than 24 V) applied to the flat part of the lead. Contact

time must be limited to 10 seconds at up to 300 °C. When

using a dedicated tool, all other leads can be soldered in

one operation within 2 to 5 seconds between

270 and 320 °C.

1996 Mar 20 19

Philips Semiconductors Product speciﬁcation

10-bit high-speed 2.7 to 5.25 V

analog-to-digital converter TDA8766

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these

products can reasonably be expected to result in personal injury. Philips customers using or selling these products for

use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such

improper use or sale.

Data sheet status

Objective speciﬁcation This data sheet contains target or goal speciﬁcations for product development.

Preliminary speciﬁcation This data sheet contains preliminary data; supplementary data may be published later.

Product speciﬁcation This data sheet contains ﬁnal product speciﬁcations.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or

more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation

of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation

is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

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Denmark: Prags Boulevard 80, PB 1919, DK-2300

COPENHAGEN S, Tel. (032) 88 2636, Fax. (031) 57 1949

Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. (358) 0-615 800, Fax. (358) 0-61580 920

France: 4 Rue du Port-aux-Vins, BP317,

92156 SURESNES Cedex,

Tel. (01) 4099 6161, Fax. (01) 4099 6427

Germany: P.O. Box 10 51 40, 20035 HAMBURG,

Tel. (040) 23 53 60, Fax. (040) 23 53 63 00

Greece: No. 15, 25th March Street, GR 17778 TAVROS,

Tel. (01) 4894 339/4894 911, Fax. (01) 4814 240

Hungary: see Austria

India: Philips INDIA Ltd, Shivsagar Estate, A Block,

Dr. Annie Besant Rd. Worli, BOMBAY 400 018

Tel. (022) 4938 541, Fax. (022) 4938 722

Indonesia: see Singapore

Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. (01) 7640 000, Fax. (01) 7640 200

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180,

Tel. (03) 645 04 44, Fax. (03) 648 10 07

Italy: PHILIPS SEMICONDUCTORS,

Piazza IV Novembre 3, 20124 MILANO,

Tel. (0039) 2 6752 2531, Fax. (0039) 2 6752 2557

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,

TOKYO 108, Tel. (03) 3740 5130, Fax. (03) 3740 5077

Korea: Philips House, 260-199 Itaewon-dong,

Yongsan-ku, SEOUL, Tel. (02) 709-1412, Fax. (02) 709-1415

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA,

SELANGOR, Tel. (03) 750 5214, Fax. (03) 757 4880

Mexico: 5900 Gateway East, Suite 200, EL PASO,

TEXAS 79905, Tel. 9-5(800) 234-7831, Fax. (708) 296-8556

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. (040) 2783749, Fax. (040) 2788399

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. (09) 849-4160, Fax. (09) 849-7811

Norway: Box 1, Manglerud 0612, OSLO,

Tel. (022) 74 8000, Fax. (022) 74 8341

Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC,

MAKATI, Metro MANILA,

Tel. (63) 2 816 6380, Fax. (63) 2 817 3474

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,

Tel. (022) 612 2831, Fax. (022) 612 2327

Portugal: see Spain

Romania: see Italy

Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. (65) 350 2000, Fax. (65) 251 6500

Slovakia: see Austria

Slovenia: see Italy

South Africa: S.A. PHILIPS Pty Ltd.,

195-215 Main Road Martindale, 2092 JOHANNESBURG,

P.O. Box 7430 Johannesburg 2000,

Tel. (011) 470-5911, Fax. (011) 470-5494

South America: Rua do Rocio 220 - 5th floor, Suite 51,

CEP: 04552-903-SÃO PAULO-SP, Brazil,

P.O. Box 7383 (01064-970),

Tel. (011) 821-2333, Fax. (011) 829-1849

Spain: Balmes 22, 08007 BARCELONA,

Tel. (03) 301 6312, Fax. (03) 301 4107

Sweden: Kottbygatan 7, Akalla. S-16485 STOCKHOLM,

Tel. (0) 8-632 2000, Fax. (0) 8-632 2745

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,

Tel. (01) 488 2211, Fax. (01) 481 77 30

Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66,

Chung Hsiao West Road, Sec. 1, P.O. Box 22978,

TAIPEI 100, Tel. (886) 2 382 4443, Fax. (886) 2 382 4444

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,

209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,

Tel. (66) 2 745-4090, Fax. (66) 2 398-0793

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,

Tel. (0212) 279 2770, Fax. (0212) 282 6707

Ukraine: PHILIPS UKRAINE,

2A Akademika Koroleva str., Office 165, 252148 KIEV,

Tel.380-44-4760297, Fax. 380-44-4766991

United Kingdom: Philips Semiconductors LTD.,

276 Bath Road, Hayes, MIDDLESEX UB3 5BX,

Tel. (0181) 730-5000, Fax. (0181) 754-8421

United States: 811 East Arques Avenue, SUNNYVALE,

CA 94088-3409, Tel. (800) 234-7381, Fax. (708) 296-8556

Uruguay: see South America

Vietnam: see Singapore

Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. (381) 11 825 344, Fax. (359) 211 635 777

Internet: http://www.semiconductors.philips.com/ps/

For all other countries apply to: Philips Semiconductors,

Marketing & Sales Communications, Building BE-p,

P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands,

Fax. +31-40-2724825

All rights are reserved. Reproduction in whole or in part is prohibited without the

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The information presented in this document does not form part of any quotation

or contract, is believed to be accurate and reliable and may be changed without

notice. No liability will be accepted by the publisher for any consequence of its

use. Publication thereof does not convey nor imply any license under patent- or

other industrial or intellectual property rights.

Printed in The Netherlands

537021/1100/02/pp20 Date of release: 1996 Mar 20

Document order number: 9397 750 00746