MICRON TECHNOLOGY INC (met = Ta) MT5C2568 883C MILITARY SRAM AVAILABLE AS MILITARY SPECIFICATIONS SMD 5962-88662 JAN M38510/293 * MIL-STD-883, Class B Radiation tolerant (consult factory) FEATURES High speed: 20, 25, 35 and 45ns Battery backup: 2V data retention Low power standby Power down (gated inputs) High-performance, low-power, CMOS double-metal process Single +5V (+10%) power supply * Easy memory expansion with CE All inputs and outputs are TTL compatible OPTIONS MARKING Timing 20ns access -20 25ns access -25 35ns access 35 | 45ns access -45 55ns access -55* ' 70Ons access -70* Packages Ceramic DIP (300 mil) c Ceramic DIP (600 mil) CW Ceramic LCC (28 leads) EC Ceramic LCC (32 leads) ECW Ceramic Flat Pack F 2V data retention, low power standby L Power down (gated inputs) *Electrical characteristics identical to those provided for the 45ns access devices. GENERAL DESCRIPTION The Micron SRAM family employs high-speed, low- power CMOS designs using a four-transistor memory cell. Micron SRAMs are fabricated using double-layer metal, double-layer polysilicon technology. Micron SRAMs are manufactured and quality controlled in the USA at our modern Boise, Idaho, facility. For Seay in bige Sees memory applications,Micron -. | offers chip enable (CE) and output enable (OF) capability. 32K x SRAM TH623-13 PIN ASSIGNMENT (Top View) 28-Pin DIP 32-Pin LCC (D-15/D-10) (C-12) A14d1e 280 Vec Al2q2 270 WE eis ATU3 260 A13 tate ABY4 250 a8 oe A505 240 49 aa nngcct? Ad 0 6 23 D Ali 141898 17 181920 ast? 20) OE Nae9 593 A218 211 At 28-Pin LCC A119 200 CE (C-11) A0 410 191 Das DOI 411. 181 Dav poz 412 17) 006 92138 pQ3 413 16) DOs ws Bae Vss 414 15} Da4 iE te ty a2388 28-Pin Fiat Pack (F-12) at 28 Vee a2 ar WE 73 25 AIS mw 4 Bw aS OS 4 AD ME BAN 37 2 0 8 21 A10 ag mc 10 19 DOs Dat it 18 907 baz 12 17 006 Daa 13 16 005 Vex 14 15 004 These enhancements can place the outputs in High-Z for additional flexibility in system design. Writing to these devices is accomplished when write enable (WE) and CE inputs are both LOW. Reading is accomplished when WE remains HIGH and CE and OE go LOW. The device offers a reduced power standby mode | when disabled. This allows system designs to achieve low standby power requirements. MTSC2668 REV. 7792 Micron Semiconductor, Inc., reserves the right to change products of specifications without notice. 1982, Micron Semiconductor, Inc. SSE D MM 6131549 0005653 947 MRN WVUS LSVSMICRON TECHNOLOGY INC 55E D MM 611315459 OO05b654 443 BEMRN fom Co DN MT5C2568 883C oe 32K x 8 SRAM 1-46-2 3-13 - The L version provides an approximate 50 percent battery backed systems where the designer needs to protect reduction in CMOS standby current (Isecz) over the stan- against inadvertent battery current drain during power- dard version. The P version provides an approximate 80 down, when inputs may be at undefined levels. wl percent reduction in TTL standby current (Issti). This is All devices operate from a single +5V power supply ahd p> achieved by including gated inputs on the WE, OE and all inputs and outputs are fully TTL compatible. DO address lines, The gated inputs also facilitate the design of Ww FUNCTIONAL BLOCK DIAGRAM = Voc GND All > Aa > Das A10 >| iT = : Qa oO : AO > oO o : oO 262,144-BIT 5 ' WW MEMORY ARRAY 5 AS = o q-_ 001 5 Q t c AA > pbe CE Ay L{ | (LSB) __ Al2 > LE OE ptt WE COLUMN DECODER (LSB) POWER rr? tt tp Al A2 A3 A4 A14 A13 A8 TRUTH TABLE MODE DE] CE WE ba POWER STANDBY x H X HIGH-Z STANDBY READ L L H Q ACTIVE READ H L H HIGH-Z ACTIVE WRITE x L L D ACTIVE MTS5C2568 BB3C 1-74 Micron Semiconductor, inc., reserves the right to change products or specifications without notice. REV. 7/92 1992, Micron Semiconductor, Inc.MICRON TECHNOLOGY INC Naat == [eel 55E D MB 6113549 0005655 ?LT GMRN MT5C2568 883C CPL T- 46-2 3-13 ABSOLUTE MAXIMUM RATINGS* *Stresses greater than those listed under Absolute Maxi- Voltage on Any Input or DQ Relative to V5s ....-2V to +7V mum Ratings may cause permanent damage to the device. Voltage on Vcc Supply Relative to Vss .............. This is a stress rating only and functional operation of the "Tl Storage Temperature .........scsccoseseccseecesseee device at these or any other conditions above those indi- Power Dissipation cated in the operational sections of this specification is not > Short Circuit Output Current ..ccssccsssossseuecsssecsonsee implied. Exposure to absolute maximum rating conditions (f) Lead Temperature (soldering 10 seconds) for extended periods may affect reliability. on] Junction Temperature .........scscssssssecccsessceeeseeens ~ ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS e (55C < Tg < 125C; Vec = 5V + 10%) = DESCRIPTION CONDITIONS SYMBOL | MIN MAX UNITS | NOTES Input High (Logic 1) Voltage Vin 2.2 Vec+1.0 Vv 1 Input Low (Logic 0) Voltage Vit -0.5 0.8 Vv 1,2 Input Leakage Current OV < Vins Voc Iki 5 5 pA Output Leakage Current Outputs Disabled ILo 5 pA OV < VouT < Vcc Output High Voltage lou = -4.0mA Vou 2.4 Vv 1 Output Low Voltage lo. = 8.0mA VoL 0.4 Vv 1 MAX DESCRIPTION CONDITIONS SYMBOL -20 | -25 | -35 | -45 |unrrs| notes Power Supply CE < Vit, Voc = MAX Current: Operating f = MAX = 1/*RC (MIN) Icc 130 |120}110/100| mA} 3 Outputs Open : CE 2 Vin, Vec = MAX f-_! __pz Isers 35 | 30 | 27 | 25 | ma RC (MIN) P Version Only Iset1 5;5)}5 |] 5 |mA Power Supply CE 2 Vin, All Other Inputs Current: Standby < Vit or 2 Vin, Voc = MAX Iset2 20 | 20 | 20 | 20 |mA f=0Hz P Version Only Isat2 ;5|5 15 |mA CE = (Vcc - 0.2), Voc = MAX All Other Inputs < 0.2V Isaca 15/,5 ]5 |mA or 2 (Vcc - 0.2V), f= 0 Hz | L Version Only Isec2 3/3 ]3 1/3 |ma CAPACITANCE DESCRIPTION CONDITIONS SYMBOL | MIN MAX UNITS NOTES input Capacitance Ta, = 25C, f = 1MHz Ci 8 pF 4 Output Capacitance Voc = 5V Go 8 pF 4 Rceeee 1-75 Micron Semiconductor, Inc., reserves the right to change products or specifications without notice. (1992, Micron Semiconductor, inc,MICRON TECHNOLOGY INC 55E D MM 6122545 OO05b5b b5b MMRN MT5C2568 883C le ee 32K x 8 SRAM T~46-2 3-13 ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Note 5) (-55C < Tp s 126C; Vcc = 5V + 10%) Tl z DESCRIPTION 20 = 6 ~ =| SYM MIN | MAX | MIN | MAX] MIN | MAX] MIN | MAX | UNITS! NOTES ~ READ Cycle a READ cycle time 'RG 20 25 35 45 ns = Address access time AA 20 25 35 45 | ns Chip Enable access time tACE 20 25 35 45 ns Output hold from address change OH 3 3 3 3 ns Chip Enable to output in Low-Z ZCE|] 5 5 5 5 ns 7 Chip disable to output in High-Z tHZCE 9 10 14 15 ns 6,7 Chip Enable to power-up time PU 0 0 0 0 ns Chip disable to power-down time 'PD 20 25 35 45 ns Output Enable access time tAOE - 9 10 14 15 ns Output Enable to output in Low-Z LZOE|] 0 0 0 0 ns Output disable to output in High-Z tHZOE 8 10 14 15 ns 6 WRITE Cycle WRITE cycle time two 20 25 35 45 ns Chip Enable to end of write tcw 15 18 20 25 |: ns Address valid to end of write TAW 15 18 20 25 ns Address setup time aS 0 0 0 ft) ns Address hold from end of write AH 0 0 0 0 ns WRITE pulse width twp 15 17 20 25 ns Data setup time Ds 10 12 15 20 ns Data hold time DH 0 0 0 0 ns Write disable to output in Low-Z LZWE| 3 3 3 3 ns 7 Write Enable to output in High-Z 'HZWE| 0 10 | O 11 0 14 0 16 ns | 6,7 MT6C2568 683C Micron Semiconductor, inc., reserves tha right te change products or specifications without notice. REV. 7/92 1 -76 1992, Micron Semiconductor, Inc.MICRON TECHNOLOGY INC MT5C2568 883C 55E D MM 6111549 OO0S657? S92 SBNRN MICRON AC TEST CONDITIONS Input pulse level ........c.cccscssssssceseeesseeeees Vss to 3V Input rise and fall tiM@S ........ccccc ss esecesessesesseeees 5ns Input timing reference level ............cccccccceceseee 1.5V Output reference level 0... csssssssssessssesesees 1.5V Output load ...........scsscscssssessssssees See figures 1 and 2 NOTES 1. All voltages referenced to Vss (GND). 2. -3V for pulse width < 20ns. 3. Icc is dependent on output loading and cycle rates. The specified value applies with the outputs unloaded, and f = 1 Hz 'RC (MIN) 4. This parameter is sampled. 5. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. 6. HZCE, 'HZOE and HZWE are specified with CL = 5 pF as in Fig. 2. Transition is measured + 500mV typical from steady state voltage, allowing for actual tester RC time constant. 32K x 8 SRAM +5V . : +5V 480 | $ 420 Q Q 255 : T 30 RF 255 ; 7 SPF V V Fig. 1 OUTPUT LOAD Fig. 2 OUTPUT LOAD EQUIVALENT EQUIVALENT 7. At any given temperature and voltage condition, HZCE is less than LZCE and HZWE is less than LZWE 8. WEis HIGH for READ cycle. 9. Device is continuously selected. Chip enable and output enable are held in their active state. 10. Address valid prior to or coincident with latest occurring chip enable. 11. *RC = READ cycle time. 12. Chip enable (CE) and write enable (WE) can initiate and terminate a WRITE cycle. DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only) DESCRIPTION CONDITIONS SYMBOL | MIN MAX UNITS | NOTES Vcc for Retention Data Vpr 2 _ Vv Data Retention Current CE 2 (Vcc - 0.2V) (Voc = 2V} Iccpr 500 pA Vin 2 (Vcc - 0.2V) or <0.2V Voc = 3V 800 pA Chip Deselect to Data CDR 0 - ns 4 Retention Time Operation Recovery Time 'R tRC ns 4,11 LOW Vcc DATA RETENTION WAVEFORM DATA RETENTION MODE Vee A 8B vy tcor tr S/n YL. DON'T CARE BR] UNDEFINED MTSC2568: REV. 792 Micron Semiconductor, Inc., reserves the right to change products or apscifications without notice. 1992, Micron Semiconductor, inc. IVS LSV4MICRON TECHNOLOGY INC SSE D MM 6121549 0005658 424 @ENRN MICRON MT5C2568 883C 32K x 8 SRAM T=46-2 3-13 READ CYCLE NO. 1 > n * - ~t ADDR Be VALID \ 3 zm > toH = Qa PREVIOUS DATA VALID DATA VALID READ CYCLE NO. 27:8 1 tro a CE x J ___AOE 'LZ0E | tHZOE _ | OE K ace tLZCE tHZCE pa HIGH-Z DATA VALID +__ tpu tpp lec | DON'T CARE RRR) UNDEFINED rscres 1 -78 Micron Semiconductor, tne. resarvee th right to change products or spactioanons wih Actos,MICRON TECHNOLOGY INC 55E D MM 6131549 0005659 365 MNRN MT5C2568 883C Meiied 32K x 8 SRAM WRITE CYCLE NO. 1 12 T- 46-2 3-13 (Chip Enable Controlled) two z ADDR \ n : = taw as | tow taH Y ce oF? 2 twe = we LLL WLLL bs tou ~paTAVAD e HIGH-Z WRITE CYCLE NO. 27.12 (Write Enable Controlled) two ADDR x BD taw | tow tan e WY TLD WLLL, |. tas we - Tn yo WE K A tos tH D DATA VALID Qa HIGH-Z DON'T CARE RR3] UNDEFINED NOTE: Output enable (OE) is inactive (HIGH). ey 2aee Be9C : 1-79 Noon Semiconductor, In. reserve the igi 0 change pdt of epgctioagons without noticeMICRON TECHNOLOGY INC 55E D @@ 61121549 OOOS6EED 047 HEMRN ICRON MT5C 2568 883C M 32K x 8 SRAM ELECTRICAL TEST REQUIREMENTS J-46-23- 13- wl SUBGROUPS > MIL-STD-883 TEST REQUIREMENTS (per Method 5005, Table I) Q) [INTERIM ELECTRICAL (PRE-BURN-IN) TEST PARAMETERS 2, BA, 10 = (Method 5004) FINAL ELECTRICAL TEST PARAMETERS 1, 2,3, 7,8,9, 10, 11 y (Method 5004) > GROUP A TEST REQUIREMENTS 1,2, 3,4", 7,8,9, 10, 11 = (Method 5005) GROUP C AND D END-POINT ELECTRICAL PARAMETERS 1,2,3,7,8,9, 10,11 (Method 5005) * PDA applies to subgroups 1 and 7. ** Subgroup 4 shall be measured only for initial qualification and after process or design changes, which may affect input or output capacitance. * MTSC2588 8836 Micron Semiconductor, inc., reserves the right ta change products or specifications without notice. REV. 702 1 -80 1992, Micron Semiconductor, Inc.