Zvi National Semiconductor DS78LS120/DS88LS$120 Dual Differential Line Receiver (Noise Filtering and Fail-Safe) General Description The DS78LS120 and DS88LS120 are high performance, dual differential, TTL compatible line receivers for both bal- anced and unbalanced digital data transmission. The inputs are compatible with EIA, Federal and MIL standards. The line receiver will discriminate a +200 mV input signal over a common-mode range of +10V and a 300 mV sig- nal over a range of + 15V. Circuit features include hysteresis and response control for applications where controlled rise and fall times and/or high frequency noise rejection are desirable. Threshold offset control is provided for fail-safe detection, should the input be open or short. Each receiver includes an optional 1800 terminating resistor and the output gate contains a logic strobe for time discrimination. The DS78LS120 is specified over a 55C to +125C temperature range and the DS88LS120 from 0C to + 70C. Input specifications meet or exceed those of the popular DS7820/DS8820 line receiver. Features m Meets EIA standards RS232-C, RS422 and RS423, Federal Standards 1020, 1030 and MIL-188-114 Input voltage range of +15V (differential or common- mode) Separate strobe input for each receiver 5k typical input impedance Optional 1802 termination resistor 50 mV input hysteresis 200 mV input threshold Separate fail-safe mode Connection Diagram Dual-In-Line Package FAIL-SAFE TERMI- RESPONSE Voc OFFSET -INPUT NATION +INPUT STROBE TIME OUTPUT ls 15 14 |. |. 1" 10 3 * TI y oO 1 2 3 5 6 7 [: FAIL-SAFE -INPUT TERMI +INPUT STROBE RESPONSEOUTPUT GND OFFSET NATION TIME TL/F/7499-1 Top View Order Number DS88LS120N or 0S8&LS120M See NS Package Number M16A or N16A For Complete Military 883 Specifications, see RETS Data Sheet. Order Number DS78LS120J/883 or DS78LS120W/883 See NS Package Number J16A or W16A 2-75 021S188S0/021S18ZSd |yer 4 . = a ~ | Absolute Maximum Ratings (Note 1) Operating Conditions =a if Military/Aerospace specified devices are required, Min Max Units a please contact the National Semiconductor Sales Supply Voltage (Vcc) 4.5 5.5 v Office/Distributors for availability and specifications. Temperature (Ta) Oo o Supply Voltage 7V DS78LS120 55 +125 C = Input Voltage +25V DS88LS120 0 +70 "C H Strobe Voltage 7 Common-Mode Voltage (Vc) 15 +15 Vv 2 Output Sink Current 50 mA cS Storage Temperature Range 65C to + 150C Maximum Power Dissipation at 25C Cavity Package 1433 mV Molded Package 1362 mW Lead Temperature (Soldering, 4 sec) 260C Derate cavity package 9.6 mW/C above 25C; derate molded package 10.9 mW/C above 25C. Electrical Characteristics (Notes 2 and 3) Symbol Parameter Conditions Min | Typ | Max | Ur VTH Differential Threshold Voltage lout = 400 pA, Vout 2 2.5V | -7V < Vou = 7V 0.06 | 0.2 ' 15 < Voy <15V 0.06 | 0.3 \ VIL Differential Threshold Voltage lout = 4 MA, Vout s 0.5V ~-7V < Vom s7V 0.08/ -O.2| ' 7 15V < Voy < 15V 0.08] 0.3 VTH Differential Threshold Voltage lout = 400 BA, Vout 2 2.5V | -7V < Vom < 7V 0.47 0.7 VTL with Fail-Safe Offset = 5V _ _ _ lout = 4MA, Vout < 0.5V -7V 3 Vom s 7V 0.2| 0.42 Rin Input Resistance 15V < Vou < 15V,0V <$ Voc s 7V 4 5 k Rr Line Termination Resistance Ta = 25C 100 | 180 | 300 ! Ro Offset Control Resistance Ta = 25C 42 56 70 k IInD Data Input Current (Unterminated) | Voy = 10V 2 3.1 tT Vom = OV OV< Veco <7V 0 0.5] nm Vom = 10V -2 | -3.1] on VTHB Input Balance lout = 400 pA, Vout 2 2.5V, | -7V < Voy 7V 04 0.4 (Note 5) Rs = 5000 , lout = 4MA, Vout s 0.5V, 7V 3 Vom Ss 7V ~o1| -0.4 Rs = 5000 . . VOH Logical 1 Output Voltage lout = 400 BA, VoirF = 1V, Voc = 4.5V 2.5 3 VoL Logical 0 Output Voltage louT = 4MA, VoiFE = 1V, Veco = 4.5V 0.35 | 0.5 lec Power Supply Current Voc = 5.5V Vom = 15V 10 16 r Voirr = 0.5V, (Both Receivers) Vom = 15V 40 16 r Hn (1) Logical 1 Strobe Input Current | VstRoge = 5.5V, Voice = 3V 1 100 | 1 Tin (0) Logical 0 Strobe Input Current | VstRoge = OV, Voire = 3V 290} 400| ; Vin Logical 1 Strobe Input Voltage | VoL S 0.5, lout = 4mA 2.0 | 1.12 Vit Logical 0 Strobe Input Voltage | Vox 2 2.5V, lout, = 400 pA 1.12 0.8 los Output Short-Circuit Current Vout = OV, Voc = 5.5V, Vstroge = OV, (Note 4) ~30; 100{-170] +r Note 1: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. Except for Operating Temperature Range they are nat meant to imply that the devices should be operated at these limits. The table of Electrical Characteristics provides conditions for actual devic operation. Note 2: Unless otherwise specified min/max limits apply across the 55C to + 125C temperature range for the OS78LS120 and across the 0C to + 70C for tr O0S88LS120. All typical values are for Ta = 25C, Voc = 5V and Voy = OV. Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shov as max or min on absolute value basis. Note 4: Only one output at a time should be shorted. Note 5: Refer to EIA-RS422 for exact canditions. 2-76ee Switching Characteristics vcc = 5vV, Ta = 25C Symbol Parameter Conditions Min Typ Max Units tpdo(D) Differential Input to 0 Output 38 60 ns tod4 (D) Differential Input to 1 Output Response Pin Open, CL = 15pF, Ry = 2k 38 60 ns tpdo(s) Strobe Input to 0 Output . 16 25 ns tod1(S) Strobe Input to 1 Output 12 25 ns AC Test Circuit and Switching Time Waveforms Differential and Strobe Input Signal OUTPUT InpuT O- OPEN O- O STAOBE OPEN INPUT = . = TL/F/7499~3 Includes probe and test fixture capacitance 254, DIFF / \ INPUT ov 500 ns -25V Vec STROBE / \ INPUT 50% 500 ov _ OUTPUT 1.5 1.5 te ete 10ns 4 40(0) 7 d1(D) 405 a(S) PRA =1 MHz *d0(0) "py 'pdo(s) + edt (S) i Note: Optimum switching response is obtained by minimizing stray capacitance on Response Control pin (no external connection). TL/F/7499-4 Application Hints Balanced Data Transmission 0$1691A/0S3691 UNE DRIVER _ 1/2 OS78LS120 T LINE RECEIVER TWISTED PAIR STROBE TL/F/7499-5 021S188S0/021S18ZSG0 2-77DS78LS120/DS88LS 120 Application Hints (Continued) Unbalanced Data Transmission 1/4 031483 OR 1/40818914/0S3891 1/2 OS78LS129 LINE RECEIVER 2OVLIOA 1NdLNO Vou Vou Vin YT Vin . INPUT VOLTAGE TL/F/7499-7 The DS78LS120/DS88LS120 may be used as a level trans- lator to interface between +12V MOS, ECL, TTL and CMOS. To configure, bias either input to a voltage equal to Vv the voltage of the input signal, and the other input to the driving gate. LINE DRIVERS Line drivers which will interface with the DS78LS120/ DS88LS120 are listed below. Balanced Drivers DS26LS31 Quad RS-422 Line Driver Dual CMOS DS7830, DSss30 Dual TTL DS7831, DS8831 Dual TRI-STATE TTL DS7832, DS8832 Dual TRI-STATE TTL 0S1691A, DS3691 Quad RS-423/Dual RS-422 TTL 0S1692, DS3692 Quad RS-423/Dual TRI-STATE RS-422 TTL DS3487 Quad TRI-STATE RS-422 Unbalanced Drivers 0S1488 Quad RS-232 DS75150 Dual RS-232 RESPONSE CONTROL AND HYSTERESIS In unbalanced (RS-232/RS-423) applications it is recom- mended that the rise time and fall time of the line driver be controlled to reduce cross-talk. Elimination of switching noise is accomplished in the DS78LS120/DS88LS120 by the 50 mV of hysteresis incorporated in the output gate. This eliminates the oscillations which may appear in a line receiver due ta the input signal slowly varying about the threshold level for extended periods of time. High frequency noise which is superimposed on the input signal which may exceed 50 mV can be reduced in ampli- tude by filtering the device input. On the DS78LS120/ DS88LS120, a high impedance response control pin in the input amplifier is available to filter the input signal without TL/F/7499~-6 Logic Level Transiator ECL GATE ECt THAESHOLD O=+4 o-| 1/2 OS7B8L$120 LINE RECEIVER TL/F/7499 affecting the termination impedance of the transmissic line. Noise pulse width rejection vs the value of the r sponse control capacitor is shown in Figures 7 and 2. Tr combination of filters followed by hysteresis will optimi: performance in a worse case noise environment. 100k 10k NOISE PULSE WIDTH (ns) (FIGURE 2) 100 tk 18% RESPONSE CONTROL CAPACITOR (pF) INPUT CG TL/F/7496 FIGURE 1. Noise Pulse Width vs Response Control Capacitor OUTPUT RESPONSE CONTROL TL CAPACITOR NEGATIVE INPUT NOISE PULSE POSITIVE INPUT NOISE PULSE +--+ NOISE PULSE WIOTH 2V -1 5V TL/F/7499- FIGURE 2 2-78Application Hints (Continued) TRANSMISSION LINE TERMINATION On a transmission line which is electrically long, it is advisa- ble to terminate the line in its characteristic impedance to prevent signal reflection and its associated noise/cross- talk. A 180 termination resistor is provided in the DS78LS120/DS88LS$120 line receiver. To use the termina- tion resistor, connect pins 2 and 3 together and pins 13 and 14 together. The 1802 resistor provides a good compro- mise between line reflections, power dissipation in the driv- er, and IR drop in the transmission line. If power dissipation and IR drop are still a concern, a capacitor may be connect- ed in series with the resistor to minimize power loss. The value of the capacitor is recommended to be the line length (time) divided by 3 times the resistor value. Example: if the transmission line is 1,000 feet long, (approximately 1000 ns), and the termination resistor value is 1800, the capacitor value should be 1852 pF. For additional applica- tion details, refer to application notes AN-22 and AN-108. FAIL-SAFE OPERATION i Communication systems require elements of a system to detect the presence of signals in the transmission lines, and it is desirable to have the system shut-down in a fail-safe mode if the transmission line is open or shorted. To facilitate the detection of input opens or shorts, the DS78LS120/ DS88LS120 incorporates an input threshold voltage offset. This feature will force the line receiver to a specific logic state if presence of either fault is a condition. Given that the receiver input threshold is +200 mV, an input signal greater than +200 mV insures the receiver will be in a specific logic state. When the offset control input (pins 1 and 15) is connected to Vcc = 5V, the input thresholds are oftset from 200 mV to 700 mV, referred to the non-in- verting input, or 200 mV to 700 mV, referred to the inverting input. Therefore, if the input is open or shorted, the input will be greater than the input threshold and the receiv- er will remain in a specified logic state. The input circuit of the receiver consists of a 5k resistor terminated to ground through 1202 on both inputs. This net- work acts as an attenuator, and permits operation with com- mon-mode input voltages greater than 15V. The offset control input is actually another input to the attenuator, but its resistor value is 56k. The offset control input is connect- ed to the inverting input side of the attenuator, and the input valtage to the amplifier is the sum of the inverting input plus 0.09 times the voltage on the offset control input. When the offset control input is connected to 5V the input amplifier will see VIN(INVERTING) + 0.45V or ViINGNVERTING) + 0.9V when the control input is connected to 10V. The offset control input will not significantly affect the differential performance of the receiver over its common-mode operating range, and will not change the input impedance balance of the receiver. It is recommended that the receiver be terminated (5002 or less) to insure it will detect an open circuit in the presence of noise. The offset control can be used to insure fail-safe operation for unbalanced interface (RS-423) or for balanced interface (RS-422) operation. For unbalanced operation, the receiver would be in an inde- terminate logic state if the offset control input was open. Connecting the fail-safe offset pin to 5V, offsets the receiver threshold to 0.45V. The output is forced to a logic zero state if the input is open or shorted. Unbalanced RS-423 and RS-232 Fail-Safe LINE RECEIVER 1/2 DS78L5120 LINE DRIVER + (OFFSET CONTROL INPUT OPEN) OUTPUT VOLTAGE Den 0 INPUT VOLTAGE [ZZ )oo TL/F/7499-11 5v O-- (OFFSET CONTROL INPUT = 5V) OUTPUT VOLTAGE 8 0.45V INPUT VOLTAGE TL/F/7499-12 02+S188S0/021S18ZSdDS78LS120/DS88LS120 Application Hints (continued) Balanced RS-422 Fail-Safe BALANCED LINE DRIVER dl Ft 1 1/2 OS78LS120 LINE RECEIVERS 5v O-________#+ TL/F/7499-13 id Abd Oo a Q < 2 < ~ =< a 5 2 > =: > B A 5 - 5 a = 5 = = a 2 3 s S INPUT VOLTAGE INPUT VOLTAGE INPUT VOLTAGE For balanced operation with inputs open or shorted, receiv- er C will be in an indeterminate logic state. Receivers A and B will be in a logic zero state allowing the NOR gate to detect the open or short condition. The strobe will disable receivers A and B and may therefore be used to sample the fail-safe detector. Another method of fail-safe detection consists of filtering the output of NOR gate D so it would not indicate a fault condition when receiver inputs pass through the threshold region, generating an output transient. Truth Table (For Balanced Fail-Safe) TL/F/7499-14 in a communications system, only the control signals are required to detect input fault conditions. Advantages of a balanced data transmission system over an unbalanced transmission system are: 1. High noise immunity 2. High data ratio 3. Long line lengths Input Strobe A-Out B-Out C-Out D-Out 0 1 0 1 0 0 1 1 1 0 1 0 xX 1 0 0 x 1 0 0 1 1 0 0 1 0 1 1 0 0 xX 0 1 1 0 0 2-80Ae DS78LS120/DS88LS 120 Schematic Diagram e-66PL/4/11 fit Wh lt ul OL inding O t SZ NUL fi "BL 390H1S 1 be ifdNt ONILHJANI 138440 34S TIV4 YOLSIS3H ozL NOLLWNIWYIL oBt inant ONILUIANI-NON 45 151 % WY N We 15 A MI *y, J, >t $0 ul N a v IOYLNOD ISNOdS3u wet 2-8116 Lead (0. 150" Wide) Molded Smail Outline Package, JEDEC NS Package Number M1i6A 0,150 0.187 >| (3.610 3.988) | 0.010-0.020 (0.254 0.608) > B MAX TYP | ALL LEADS i oom ~9.010 on L. 0.016 0.050 (0.203 - 0.264) (0.406 1.270} ALL 0.004 TYP ALL LEADS (0.102) ALL LEAD TIPS All dimensions are in inches (millimeters) 0.386 0.394 (9.804 10.00) 0.228 0.244 30 (5.791 ~ 6.198) TYP LEAD NO.1 1 2 3 4 5 6 7 8 A IDENT 0.010 0.010 way (0.254) 0.053 0.069 (1.346 1.753) 0.004 0.010 y (0.102 0.254) Th Le (0.356 0.508) Yf (0.203) M16A (REV H)