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AT24C01B/02B/04B/08B Automotive [DATASHEET]
Atmel-8517D-SEEPROM-AT24C01B-02B-04B-08B-Auto-Datasheet_082014
4. Pin Description
Serial Clock (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative
edge clock data out of each device.
Serial Data (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may
be wire-ORed with any number of other open-drain or open-collector devices.
Device/Page Addresses (A2, A1, and A0): The A2, A1, and A0 pins are device address inputs which are hard
wired for the AT24C01B/02B/04B/08B Automotive. As many as eight 1K/2K devices may be addressed on a
single bus system (device addressing is discussed in detail under the Device Addressing section). The
AT24C04B uses the A2 and A1 inputs for hardwire addressing and a total of four 4K devices may be addressed
on a single bus system. The A0 pin is a no connect.
The AT24C08B only uses the A2 input for hardwire addressing and a total of two 8K devices may be addressed
on a single bus system. The A0 and A1 pins are no connect.
Write Protect (WP): The AT24C01B/02B/04B/08B has a Write Protect pin which provides hardware data
protection. The Write Protect pin allows normal Read/Write operations when connected to Ground (GND).
When the Write Protect pin is connected to VCC, the write protection feature is enabled and operates as shown
in the following table.
Table 4-1. Write Protect
5. Memory Organization
AT24C01B, 1K Serial EEPROM: Internally organized with 16 pages of 8 bytes each, the 1K requires a 7-bit
data word address for random word addressing.
AT24C02B, 2K Serial EEPROM: Internally organized with 32 pages of 8 bytes each, the 2K requires an 8-bit
data word address for random word addressing.
AT24C04B, 4K Serial EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K requires a 9-bit
data word address for random word addressing.
AT24C08B, 8K Serial EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K requires a 10-bit
data word address for random word addressing.
5.1 Pin Capacitance
Table 5-1. Pin Capacitance(1)
Note: 1. This parameter is characterized and is not 100% tested.
WP Pin Status Part of the Array Protected
At VCC Full Array
At GND Normal Read/Write Operations
Applicable over recommended operating range from TA = 25C, f = 400kHz, VCC = +2.5V.
Symbol Test Condition Max Units Conditions
CI/O Input/Output Capacitance (SDA) 8 pF VI/O = 0V
CIN Input Capacitance (A0, A1, A2, SCL) 6 pF VIN = 0V