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FAN54005 USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator Features Description Fully Integrated, High-Efficiency Charger for Single-Cell Li-Ion and Li-Polymer Battery Packs Charge Voltage Accuracy: The FAN54005 combines a highly integrated switch-mode charger, to minimize single-cell Lithium-ion (Li-ion) charging time from a USB power source, and a boost regulator to power a USB peripheral from the battery. 5% Input Current Regulation Accuracy 0.5% at 25C 1% from 0 to 125C 5% Charge Current Regulation Accuracy 20 V Absolute Maximum Input Voltage 6 V Maximum Input Operating Voltage 1.45 A Maximum Charge Rate 2 Programmable through High-Speed I C Interface (3.4 Mb/s) with Fast Mode Plus Compatibility - Input Current - - - Fast-Charge / Termination Current Charger Voltage Termination Enable 3 MHz Synchronous Buck PWM Controller with Wide Duty Cycle Range Small Footprint 1 H External Inductor Low Reverse Leakage to Prevent Battery Drain to VBUS Safety Timer with Reset Control 1.8 V Regulated Output from VBUS for Auxiliary Circuits Dynamic Input Voltage Control Automatically Reduces Charging Current with Weak Input Sources 5 V, 500 mA Boost Mode for USB OTG for 3.0 V to 4.5 V Battery Input Available in a 1.96 x 1.87 mm, 20-bump, 0.4 mm Pitch WLCSP Package The charging parameters and operating modes are 2 programmable through an I C Interface that operates up to 3.4 Mbps. The charger and boost regulator circuits switch at 3 MHz to minimize the size of external passive components. The FAN54005 provides battery charging in three phases: conditioning, constant current and constant voltage. To ensure USB compliance and minimize charging time, the 2 input current limit can be changed through the I C interface by the host processor. Charge termination is determined by a programmable minimum current level. A safety timer with 2 reset control provides a safety backup for the I C host. 2 Charge status is reported to the host through the I C port. The integrated circuit (IC) automatically restarts the charge cycle when the battery falls below an internal threshold. If the input source is removed, the IC enters a high-impedance mode, preventing leakage from the battery to the input. Charge current is reduced when the die temperature reaches 120C, protecting the device and PCB from damage. The FAN54005 can operate as a boost regulator on command from the system. The boost regulator includes a soft-start that limits inrush current from the battery and uses the same external components used for charging the battery. L1 SW VBUS CBUS 1H 1F COUT 0.1F PGND PMID CMID CSIN 4.7F Applications SDA SCL Cell Phones, Smart Phones, PDAs Tablet, Portable Media Players Gaming Device, Digital Cameras 68m VBAT DISABLE VREG OTG/USB# CREG STAT + Battery CBAT SYSTEM LOAD 10F 1F Figure 1. (c) 2015 Fairchild Semiconductor Corporation FAN54005 * Rev. 1.1 RSENSE FAN54005 Typical Application www.fairchildsemi.com FAN54005 -- USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator March 2016 Part Number Temperature Range FAN54005UCX -40 to 85C IC_INFO[4:2] Packing Method 101 Tape and Reel PN Bits: Package 20-Bump, Wafer-Level Chip-Scale Package (WLCSP), 0.4 mm Pitch, 1.96 x 1.87 mm Block Diagram VREG PMID > VBAT < VBAT 1.8V / PMID REG CREG PMID 1F CMID Q1A CHARGE PUMP 1F 4.7F Q1B L1 SW VBUS OVP Q1B OFF ON PMID Q1 Q3 VBUS CBUS Q1A ON OFF PWM MODULATOR I_IN CONTROL Q2 1H PGND DAC CSIN VREF COUT RSENSE 0.1F VBAT SDA SCL + Figure 2. 47F STAT 30mA SYSTEM LOAD LOGIC AND CONTROL OTG CSYS_DISTRIBUTED Battery 10F OSC DISABLE Table 1. CBAT PMID I2C INTERFACE IC and System Block Diagram Recommended External Components Component Description Vendor Parameter Typ. Unit L1 1 H 20%, 4.0 A, 33 m, 2016 Semco CIGT201610EH1R0M L 1.0 H CBAT 10 F, 20%, 6.3 V, X5R, 0603 Murata: GRM188R60J106M TDK: C1608X5R0J106M C 10 F CMID 4.7 F, 10%, 10 V, X5R, 0603 Murata: GRM188R61A475K TDK: C1608X5R1A475K 4.7 F CBUS 1.0 F, 10%, 25 V, X5R, 0603 Murata: GRM188R61E105K TDK: C1608X5R1E105M C 1.0 F CREG 1.0 F, 10%, 10 V, X5R, 0402 Murata: GRM155R61A105K TDK: C1005X5R1A105K C 1.0 F COUT 0.1 F, 10%, 16 V, X7R, 0402 Murata: GRM155R71C104K TDK: C1005X7R1C104K C 0.1 F n/a n/a C 47 F CSYS_DISTRIBUTED (2) (1) C Notes: 1. A 10 V rating is sufficient for CMID because PMID is protected from over-voltage surges on VBUS by Q3 (Figure 2). 2. A minimum 47 F of distributed capacitance on SYS is required for proper operation of the FAN54005. (c) 2015 Fairchild Semiconductor Corporation FAN54005 * Rev. 1.1 www.fairchildsemi.com 2 FAN54005 -- USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator Ordering Information A1 A2 A3 A4 A4 A3 A2 A1 B1 B2 B3 B4 B4 B3 B2 B1 C1 C2 C3 C4 C4 C3 C2 C1 D1 D2 D3 D4 D4 D3 D2 D1 E1 E2 E3 E4 E4 E3 E2 E1 Top View Bottom View Figure 3. WLCSP-20 Pin Assignments Pin Definitions Pin # Name A1, A2 VBUS A3 NC No Connect. No external connection is made between this pin and the IC's internal circuitry. A4 SCL I C Interface Serial Clock. This pin should not be left floating. B1-B3 PMID Power Input Voltage. Power input to the charger regulator, bypass point for the input current sense, and high-voltage input switch. Bypass with a minimum of 4.7 F, 6.3 V capacitor to PGND. B4 SDA I C Interface Serial Data. This pin should not be left floating. C1-C3 SW Switching Node. Connect to output inductor. C4 STAT Status. Open-drain output indicating charge status. The IC pulls this pin LOW when charging. D1-D3 PGND Power Ground. Power return for gate drive and power transistors. The connection from this pin to the bottom of CMID should be as short as possible. D4 OTG On-The-Go. On VBUS Power-On Reset (POR), this pin sets the input current limit for t 15MIN charging. Also, the OTG pin enables the boost regulator in conjunction with OTG_EN and OTG_PL bits (See Table 15) E1 CSIN Current-Sense Input. Connect to the sense resistor in series with the battery. The IC uses this node to sense current into the battery. Bypass this pin close to RSENSE with a 0.1 F capacitor to PGND. E2 Description Charger Input Voltage and USB-OTG output voltage. Bypass with a 1 F capacitor to PGND. 2 2 Charge Disable. If this pin is HIGH, charging is disabled. When LOW, charging is controlled by the 2 DISABLE I C registers. When this pin is HIGH, the 15-minute timer is reset. This pin does not affect the 32-second timer. E3 VREG Regulator Output. Connect to a 1 F capacitor to PGND. This pin provides regulated 1.8 V and can supply up to 2mA of DC load current. E4 VBAT Battery Voltage. Connect to the positive (+) terminal of the battery pack and close to RSENSE. (c) 2015 Fairchild Semiconductor Corporation FAN54005 * Rev. 1.1 www.fairchildsemi.com 3 FAN54005 -- USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator Pin Configuration Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VBUS VBUS Voltage VSTAT STAT Voltage VI VO Parameter Min. Continuous -0.7 Pulsed, 100 ms Maximum Non-Repetitive -1.0 -0.3 PMID Voltage Unit 20.0 V 16.0 V 7.0 SW, CSIN, VBAT, DISABLE Voltage -0.3 Voltage on Other Pins -0.3 dVBUS dt Maximum VBUS Slope above 5.5 V when Boost or Charger are Active dVBUS dt Negative VBUS Slew Rate during VBUS Short Circuit, CMID < 4.7 F (See VBUS Short While Charging) ESD Max. Electrostatic Discharge Protection Level 7.0 6.5 (3) 4 TA < 60C 4 TA > 60C 2 Human Body Model per JESD22-A114 2000 Charged Device Model per JESD22-C101 1000 V V V/s V/s V TJ Junction Temperature -40 +150 C TSTG Storage Temperature -65 +150 C +260 C TL Lead Soldering Temperature, 10 Seconds Note: 3. Lesser of 6.5 V or VI + 0.3 V. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VBUS VBAT(MAX) Parameter Supply Voltage Min. Max. Unit 4 6 V 4.5 V TA Maximum Battery Voltage when Boost enabled Ambient Temperature -30 +85 C TJ Junction Temperature (See Thermal Regulation and Protection section) -30 +120 C Thermal Properties Junction-to-ambient thermal resistance is a function of application and board layout. This data is measured with four-layer 2s2p boards in accordance to JEDEC standard JESD51. Special attention must be paid not to exceed junction temperature TJ(max) at a given ambient temperature TA. For measured data, see Thermal Regulation and Protection. Symbol Parameter Typical Unit JA Junction-to-Ambient Thermal Resistance 60 C/W JB Junction-to-PCB Thermal Resistance 20 C/W (c) 2015 Fairchild Semiconductor Corporation FAN54005 * Rev. 1.1 www.fairchildsemi.com 4 FAN54005 -- USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator Absolute Maximum Ratings Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for TJ and TA; VBUS=5.0 V; HZ_MODE; OPA_MODE=0; (Charge Mode); SCL, SDA, OTG=0 or 1.8 V; and typical values are for TJ=25C. Symbol Parameter Conditions Min. Typ. Max. Unit Power Supplies IVBUS VBUS Current ILKG VBAT to VBUS Leakage Current IBAT Battery Discharge Current in High-Impedance Mode VBUS > VIN(MIN)1, PWM Switching 10 mA VBUS > VIN(MIN)1; PWM Enabled, Not Switching (Battery OVP Condition); I_IN Setting=100 mA 2.5 mA 0C < TJ < 85C, HZ_MODE=1, 32S Mode 63 90 A 0C < TJ < 85C, HZ_MODE=1, VBAT=4.2 V, VBUS=0 V 0.2 5.0 A 0C < TJ < 85C, HZ_MODE=1, VBAT=4.2 V 10 DISABLE=1, 0C < TJ < 85C, VBAT=4.2 V 10 A Charger Voltage Regulation Charge Voltage Range VOREG Charge Voltage Accuracy 3.5 4.4 -0.5% +0.5% TJ=0 to 125C -1% +1% VSHORT < VBAT < VOREG, RSENSE=68 m 550 1450 mA 20 mV [VCSIN - VBAT ] 40 mV 92 97 102 % [VCSIN - VBAT ] > 40 mV 94 97 100 % TA=25C V Charging Current Regulation Output Charge Current Range IOCHARGE Charge Current Accuracy Across RSENSE Weak Battery Detection VLOWV Weak Battery Threshold Range 3.4 3.7 V Weak Battery Threshold Accuracy -5 +5 % Weak Battery Deglitch Time Rising Voltage 30 ms Logic Levels: DISABLE, SDA, SCL, OTG VIH High-Level Input Voltage VIL Low-Level Input Voltage IIN Input Bias Current 1.05 Input Tied to GND or VBUS V 0.01 0.4 V 1.00 A mA Charge Termination Detection Termination Current Range ITERM Termination Current Accuracy VBAT > VOREG - VRCH, RSENSE=68 m 50 400 [VCSIN - VBAT ] from 3 mV to 20 mV -25 +25 [VCSIN - VBAT ] from 20 mV to 40 mV -5 +5 Termination Current Deglitch Time 30 % ms 1.8 V Linear Regulator VREG 1.8 V Regulator Output IREG from 0 to 2 mA 1.7 1.8 1.9 V Input Power Source Detection VIN(MIN)1 VBUS Input Voltage Rising To Initiate and Pass VBUS Validation 4.29 4.42 V VIN(MIN)2 Minimum VBUS During Charge During Charging 3.71 3.94 V tVBUS_VALID VBUS Validation Time (c) 2015 Fairchild Semiconductor Corporation FAN54005 * Rev. 1.1 30 ms www.fairchildsemi.com 5 FAN54005 -- USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator Electrical Specifications Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for TJ and TA; VBUS=5.0 V; HZ_MODE; OPA_MODE=0; (Charge Mode); SCL, SDA, OTG=0 or 1.8 V; and typical values are for TJ=25C. Symbol Parameter Conditions Min. Typ. Max. Unit +3 % Dynamic Input Voltage Control (VBUS) VSP DIVC Accuracy -3 Input Current Limit IINLIM Input Current Limit Threshold IINLIM Set to 100 mA 88 93 98 IINLIM Set to 500 mA 450 475 500 mA VREF Bias Generator VREF Bias Regulator Voltage VBUS > VIN(MIN)1 6.5 Short-Circuit Current Limit 20 V mA Battery Recharge Threshold VRCH Recharge Threshold Below VOREG Deglitch Time VBAT Falling Below VRCH Threshold 100 120 150 130 mV ms STAT Output VSTAT(OL) STAT Output Low ISTAT=10 mA ISTAT(OH) VSTAT=5 V STAT High Leakage Current 0.4 V 1 A Battery Detection IDETECT Battery Detection Current before (4) Charge Done (Sink Current) tDETECT Battery Detection Time Begins after Termination Detected and VBAT < VOREG -VRCH -0.80 mA 262 ms Sleep Comparator VSLP Sleep-Mode Entry Threshold, VBUS - VBAT 2.3 V < VBAT < VOREG, VBUS Falling tSLP_EXIT Deglitch Time for VBUS Rising Above VBAT by VSLP Rising Voltage 30 IINLIM=500 mA 180 250 Q1 On Resistance (PMID to SW) 130 225 Q2 On Resistance (SW to GND) 150 225 0 0.04 0.10 V ms Power Switches (See Figure 2) Q3 On Resistance (VBUS to PMID) RDS(ON) m Charger PWM Modulator fSW Oscillator Frequency DMAX Maximum Duty Cycle DMIN Minimum Duty Cycle ISYNC Synchronous to NonSynchronous Current Cut-Off (5) Threshold 2.7 Low-Side MOSFET (Q2) Cycle-byCycle Current Limit 3.0 3.3 MHz 100 % 0 % 140 mA Boost Mode Operation (OPA_MODE=1, HZ_MODE=0) VBOOST Boost Output Voltage at VBUS IBAT(BOOST) Boost Mode Quiescent Current 2.5 V < VBAT < 4.5 V, ILOAD from 0 to 200 mA 4.80 5.07 5.17 3.0 V < VBAT < 4.5 V, ILOAD from 0 to 500 mA 4.77 5.07 5.17 140 300 A 1440 1700 1960 mA PFM Mode, VBAT=3.6 V, IOUT=0 ILIMPK(BST) Q2 Peak Current Limit UVLOBST Minimum Battery Voltage for Boost Operation (c) 2015 Fairchild Semiconductor Corporation FAN54005 * Rev. 1.1 V While Boost Active 2.30 To Start Boost Regulator 2.50 2.70 V www.fairchildsemi.com 6 FAN54005 -- USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator Electrical Specifications Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for TJ and TA; VBUS=5.0 V; HZ_MODE; OPA_MODE=0; (Charge Mode); SCL, SDA, OTG=0 or 1.8 V; and typical values are for TJ=25C. Symbol Parameter Conditions Min. Typ. Max. Unit VBUS Load Resistance RVBUS VBUS to PGND Resistance Normal Operation 1500 k Charger Validation 100 Protection and Timers VBUSOVP ILIMPK(CHG) VSHORT ISHORT TSHUTDWN VBUS Over-Voltage Shutdown VBUS Rising Hysteresis VBUS Falling 100 mV Q1 Cycle-by-Cycle Peak Current Limit Charge Mode 2.3 A Battery Short-Circuit Threshold VBAT Rising Hysteresis VBAT Falling Linear Charging Current VBAT < VSHORT Thermal Shutdown Threshold Hysteresis (6) (6) TCF Thermal Regulation Threshold tINT Detection Interval t32S 32-Second Timer t15MIN tLF (6) 6.09 1.95 6.29 2.00 6.49 2.05 100 20 30 V V mV 40 mA TJ Rising 145 TJ Falling 10 Charge Current Reduction Begins 120 C 2.1 s C Charger Enabled 20.5 25.2 28.0 Charger Disabled 18.0 25.2 34.0 15-Minute Timer 15-Minute Mode 12.0 13.5 15.0 min Low-Frequency Timer Accuracy Charger Inactive -25 25 % (7) s Notes: 4. Negative current is current flowing from the battery to GND (discharging the battery). 5. Q2 always turns on for 60 ns, then turns off if current is below ISYNC. 6. Guaranteed by design; not tested in production. 7. This tolerance (%) applies to all timers on the IC, including soft-start and deglitching timers. (c) 2015 Fairchild Semiconductor Corporation FAN54005 * Rev. 1.1 www.fairchildsemi.com 7 FAN54005 -- USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator Electrical Specifications Guaranteed by design, VBAT>2.5 V if valid VBUS not present. Symbol Parameter Conditions Min. Typ. Standard Mode fSCL tBUF SCL Clock Frequency Bus-Free Time between STOP and START Conditions tHD;STA tLOW SCL LOW Period Fast Mode 400 High-Speed Mode, CB < 100 pF 3400 High-Speed Mode, CB < 400 pF 1700 Standard Mode 4.7 Fast Mode 1.3 tSU;STA tSU;DAT SCL HIGH Period Repeated START Setup Time Data Setup Time tRCL tFCL tRDA tRCL1 Data Hold Time SCL Rise Time SCL Fall Time SDA Rise Time Rise Time of SCL after a Repeated START Condition and after ACK Bit s s Fast Mode 600 ns High-Speed Mode 160 ns Standard Mode 4.7 s Fast Mode 1.3 s High-Speed Mode, CB < 100 pF 160 ns High-Speed Mode, CB < 400 pF 320 ns 4 s Fast Mode 600 ns High-Speed Mode, CB < 100 pF 60 ns High-Speed Mode, CB < 400 pF 120 ns Standard Mode 4.7 s Fast Mode 600 ns High-Speed Mode 160 ns Standard Mode 250 Fast Mode 100 High-Speed Mode tHD;DAT kHz 4 Standard Mode tHIGH Unit 100 Standard Mode START or Repeated START Hold Time Max. ns 10 Standard Mode 0 3.45 s Fast Mode 0 900 ns High-Speed Mode, CB < 100 pF 0 70 ns ns High-Speed Mode, CB < 400 pF 0 150 Standard Mode 20+0.1CB 1000 Fast Mode 20+0.1CB 300 High-Speed Mode, CB < 100 pF 10 80 High-Speed Mode, CB < 400 pF 20 160 Standard Mode 20+0.1CB 300 Fast Mode 20+0.1CB 300 High-Speed Mode, CB < 100 pF 10 40 High-Speed Mode, CB < 400 pF 20 80 Standard Mode 20+0.1CB 1000 Fast Mode 20+0.1CB 300 High-Speed Mode, CB < 100 pF 10 80 High-Speed Mode, CB < 400 pF 20 160 ns ns ns Continued on the following page... (c) 2015 Fairchild Semiconductor Corporation FAN54005 * Rev. 1.1 www.fairchildsemi.com 8 FAN54005 -- USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator I2C Timing Specifications Guaranteed by design, VBAT>2.5 V if valid VBUS not present. Symbol Parameter tFDA Conditions SDA Fall Time tSU;STO Stop Condition Setup Time CB Min. Typ. Max. Standard Mode 20+0.1CB 300 Fast Mode Unit 20+0.1CB 300 High-Speed Mode, CB < 100 pF 10 80 High-Speed Mode, CB < 400 pF 20 160 Standard Mode 4 s Fast Mode 600 ns High-Speed Mode 160 ns Capacitive Load for SDA, SCL 400 ns pF Timing Diagrams tF tSU;STA tBUF SDA tR TSU;DAT tHD;STO tHIGH SCL tLOW tHD;STA tHD;DAT tHD;STA REPEATED START START Figure 4. tFDA STOP START 2 I C Interface Timing for Fast and Slow Modes tRDA REPEATED START tSU;DAT STOP SDAH tSU;STA tRCL1 tFCL tRCL tSU;STO tHIGH SCLH tLOW tHD;STA tHD;DAT REPEATED START note A = MCS Current Source Pull-up = RP Resistor Pull-up Note A: First rising edge of SCLH after Repeated Start and after each ACK bit. Figure 5. (c) 2015 Fairchild Semiconductor Corporation FAN54005 * Rev. 1.1 2 I C Interface Timing for High-Speed Mode www.fairchildsemi.com 9 FAN54005 -- USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator I2C Timing Specifications 180 900 160 800 Battery Charge Current (mA) Battery Charge Current (mA) Unless otherwise specified, circuit of Figure 1, VOREG=4.2 V, VBUS=5.0 V, and TA=25C. 140 120 100 5.5 VBUS 80 5.0 VBUS 700 600 500 5.5 VBUS 400 5.0 VBUS 4.7 VBUS 4.7 VBUS 300 60 2.5 3.0 3.5 4.0 2.5 4.5 3.0 4.0 4.5 Battery Voltage, VBAT (V) Battery Voltage, VBAT (V) Figure 6. 3.5 Battery Charge Current vs. VBUS with IINLIM=100 mA, VOREG=4.35V Figure 7. Battery Charge Current vs. VBUS with IINLIM=500 mA, VOREG=4.35V 94% 97% 4.3 VBAT, 5.0 VBUS 3.8 VBAT, 5.0 VBUS 4.3 VBAT, 5.5 VBUS 94% 92% Efficiency Efficiency 3.8 VBAT, 5.5 VBUS 91% 88% 85% 90% 88% 4.7 VBUS 86% 5.0 VBUS 5.5 VBUS 82% 100 84% 300 500 700 900 1100 1300 1500 2.5 Battery Charge Current (mA) 3.5 4.0 4.5 Battery Voltage, VBAT (V) Figure 8. Charger Efficiency, No IINLIM,IOCHARGE=1450 mA Figure 10. Auto-Charge Startup at VBUS Plug-in, OTG=0, VBAT=3.4 V (c) 2015 Fairchild Semiconductor Corporation FAN54005 * Rev. 1.1 3.0 Figure 9. Charger Efficiency vs. VBUS, IINLIM=500 mA, VOREG=4.35 Figure 11. Auto-Charge Startup at VBUS Plug-in, OTG=1, VBAT=3.4 V www.fairchildsemi.com 10 FAN54005 -- USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator Charge Mode Typical Characteristics Unless otherwise specified, circuit of Figure 1, VOREG=4.2 V, VBUS=5.0 V, and TA=25C. Figure 12. Auto-Charge Startup with 300 mA Limited Charger / Adaptor, OTG=1, VBAT=3.4 V Figure 13. Charger Startup with HZ_MODE Bit Reset, IINLIM=500 mA, IOCHARGE=1050 mA, VOREG=4.2 V, VBAT=3.6 V Figure 14. Battery Removal / Insertion During Charging, Figure 15. Battery Removal / Insertion During Charging, VBAT=3.9 V, IOCHARGE=1050 mA, No IINLIM, TE=0 VBAT=3.9 V, IOCHARGE=1050 mA, No IINLIM, TE=1 1.82 250 -30C 1.81 +85C 150 1.80 VREG (V) High-Z Mode Input Current (A) +25C 200 100 50 1.79 -30C, 5.0 VBUS 1.78 +25C, 5.0 VBUS +85C, 5.0 VBUS 0 4.0 4.5 5.0 5.5 1.77 6.0 0 1 Input Voltage, VBUS (V) Figure 16. VBUS Current in High-Impedance Mode with Battery Open (c) 2015 Fairchild Semiconductor Corporation FAN54005 * Rev. 1.1 2 3 4 5 1.8V Regulator Load Current (mA) Figure 17. VREG 1.8 V Output Regulation www.fairchildsemi.com 11 FAN54005 -- USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator Charge Mode Typical Characteristics Unless otherwise specified, circuit of Figure 1, VOREG=4.2 V, VBUS=5.0 V, and TA=25C. Sleep Mode Battery Current (A) 10 8 6 4 -30C 2 +25C +85C 0 2.5 3.0 3.5 4.0 4.5 Battery Voltage, VBAT (V) Figure 18. Sleep Mode Battery Current (A) 10 Figure 19. No Battery, TE=0, VBUS Power Up Sleep Mode Battery Discharge Current, SDA=SCL=0 V, VBUS open VBUS open, SDA=SCL=0V VBUS open, SDA=SCL=1.8V 8 VBUS=5.0V, SDA=SCL=0V, DIS or HZ=1 6 4 2 0 2.5 3.0 3.5 4.0 4.5 Battery Voltage, VBAT (V) Figure 20. Battery Discharge Current vs. Mode (c) 2015 Fairchild Semiconductor Corporation FAN54005 * Rev. 1.1 www.fairchildsemi.com 12 FAN54005 -- USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator Charge Mode Typical Characteristics 100 100 95 95 90 90 Efficiency (%) Efficiency (%) Unless otherwise specified, using circuit of Figure 1 VBAT=3.6 V, TA=25C. 85 80 85 -30C, 3.6VBAT 80 3.0 VBAT +25C, 3.6VBAT 3.6 VBAT +85C, 3.6VBAT 4.2 VBAT 75 75 0 100 200 300 400 500 0 100 VBUS Load Current (mA) Figure 21. 200 300 500 VBUS Load Current (mA) Efficiency vs. VBAT Figure 22. 5.15 Efficiency Over-Temperature 5.15 3.0 VBAT -30C, 3.6VBAT 3.6 VBAT +25C, 3.6VBAT 5.10 5.10 4.2 VBAT +85C, 3.6VBAT 5.05 VBUS (V) 5.05 VBUS (V) 400 5.00 5.00 4.95 4.95 4.90 4.90 4.85 4.85 0 100 200 300 400 500 0 VBUS Load Current (mA) Figure 23. 100 200 300 400 500 VBUS Load Current (mA) Output Regulation vs. VBAT Figure 24. Output Regulation Over-Temperature 300 -30C +25C Quiescent Current (A) 250 +85C 200 150 100 50 2.5 3.0 3.5 4.0 4.5 Battery Voltage, VBAT (V) Figure 25. Quiescent Current (c) 2015 Fairchild Semiconductor Corporation FAN54005 * Rev. 1.1 www.fairchildsemi.com 13 FAN54005 -- USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator Boost Mode Typical Characteristics Unless otherwise specified, using circuit of Figure 1 VBAT=3.6 V, TA=25C. Figure 26. Boost PWM Waveform Figure 27. 50 50 40 3.0 VBAT -30C, 3.6VBAT 3.6 VBAT +25C, 3.6VBAT 40 4.2 VBAT VBUS Ripple (mVpp) VBUS Ripple (mVpp) Boost PFM Waveform 30 20 10 +85C, 3.6VBAT 30 20 10 0 0 0 100 200 300 400 500 0 100 VBUS Load Current (mA) Figure 28. Output Ripple vs. VBAT Figure 30. Startup, 3.6 VBAT, 44 Load, Additional 10 F, X5R Across VBUS (c) 2015 Fairchild Semiconductor Corporation FAN54005 * Rev. 1.1 200 300 400 500 VBUS Load Current (mA) Figure 29. Output Ripple vs. Temperature Figure 31. VBUS Fault Response, 3.6 VBAT www.fairchildsemi.com 14 FAN54005 -- USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator Boost Mode Typical Characteristics Unless otherwise specified, using circuit of Figure 1 VBAT=3.6 V, TA=25C. Figure 32. Load Transient, 5-155-5 mA, tR=tF=100 ns (c) 2015 Fairchild Semiconductor Corporation FAN54005 * Rev. 1.1 Figure 33. Load Transient, 5-255-5 mA, tR=tF=100 ns www.fairchildsemi.com 15 FAN54005 -- USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator Boost Mode Typical Characteristics When charging batteries with a current-limited input source, such as USB, a switching charger's high efficiency over a wide range of output voltages minimizes charging time. with a constant current if sufficient input power is available. The current slew rate is limited to prevent overshoot. During the current regulation phase of charging, IINLIM or the programmed charging current limits the amount of current available to charge the battery and power the system. The effect of IINLIM on IOCHARGE can be seen in Figure 35. The FAN54005 combines a highly integrated synchronous buck regulator for charging with a synchronous boost regulator, which can supply 5 V to USB On-The-Go (OTG) peripherals. The FAN54005 employs synchronous rectification for both the charger and boost regulators to maintain high efficiency over a wide range of battery voltages and charge states. VOREG VOREG ICHARGE The FAN54005 has three operating modes: 1. Charge Mode: Charges a single-cell Li-ion or Li-polymer battery. 2. Boost Mode: Provides 5 V power to USB-OTG with an integrated synchronous rectification boost regulator using the battery as input. 3. VB AT ITERM VSHORT VSHORT ISHORT ISHORT High-Impedance Mode: Both the boost and charging circuits are OFF in this mode. Current flow from VBUS to the battery or from the battery to VBUS is blocked in this mode. This mode consumes very little current from VBUS or the battery. PRECHARGE Figure 34. CONSTANT CURRENT (CC) CONSTANT VOLTAGE (CV) Charge Curve, IOCHARGE Not Limited by IINLIM Charge Mode and Registers VOREG Note: Default settings are denoted by bold typeface. Charge Mode In Charge Mode, FAN54005 employs four regulation loops: T 1. V BA Input Current: Limits the amount of current drawn from VBUS. This current is sensed internally and can be 2 programmed through the I C interface. 2. Charging Current: Limits the maximum charging current. This current is sensed using an external RSENSE resistor. 3. Charge Voltage: The regulator is restricted from exceeding this voltage. As the internal battery voltage rises, the battery's internal impedance and RSENSE work in conjunction with the charge voltage regulation to decrease the amount of current flowing to the battery. Battery charging is completed when the voltage across RSENSE drops below the threshold determined by ITERM. 4. Temperature: If the IC's junction temperature reaches 120C, charge current is reduced until the IC's temperature stabilizes at 120C. 5. Dynamic Input Voltage Control (DIVC) limits the amount of drop on VBUS to a programmable voltage (VSP) to accommodate incompatible adapters that limit current to a lower current than might be available from a "normal" USB adapter. IC HA R GE ITERM VSHORT ISHORT PRECHARGE Figure 35. CURRENT REGULATION VOLTAGE REGULATION Charge Curve, IINLIM Limits IOCHARGE Assuming that VOREG is programmed to the cell's fully charged "float" voltage, the current that the battery accepts with the PWM regulator limiting its output (sensed at VBAT) to VOREG declines, and the charger enters the voltage regulation phase of charging. When the current declines to the programmed ITERM value, the charge cycle is complete. Charge current termination can be disabled by resetting the TE bit (REG 01[3]). The charger output or "float" voltage can be programmed by the OREG bits from 3.5 V to 4.44 V in 20 mV increments as shown in Table 2. Battery Charging Curve If the battery voltage is below VSHORT, a linear current source pre-charges the battery until VBAT reaches VSHORT. The PWM charging circuit is then started and the battery is charged (c) 2015 Fairchild Semiconductor Corporation FAN54005 * Rev. 1.1 www.fairchildsemi.com 16 FAN54005 -- USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator Circuit Description / Overview OREG Decimal Hex VOREG Decimal Hex VOREG The battery voltage falls below VOREG - VRCH VBUS Power on Reset (POR) CE or HZ_MODE is reset through I C write to CONTROL1 (REG 01) register. 2 0 00 3.50 32 20 4.14 1 01 3.52 33 21 4.16 2 02 3.54 34 22 4.18 Charge Current Limit (IOCHARGE) 3 03 3.56 35 23 4.20 4 04 3.58 36 24 4.22 5 05 3.60 37 25 4.24 6 06 3.62 38 26 4.26 Charge current is limited by the IO_LEVEL (Reg 05[5]) bit by default (IO_LEVEL=1). This limits charge current to 500 mA when RSENSE=68 m and 340 mA when RSENSE=100 m. When IO_LEVEL=0 charge current is limited by the IOCHARGE bits. 7 07 3.64 39 27 4.28 8 08 3.66 40 28 4.30 9 09 3.68 41 29 4.32 10 0A 3.70 42 2A 4.34 11 0B 3.72 43 2B 4.36 12 0C 3.74 44 2C 4.38 13 0D 3.76 45 2D 4.40 14 0E 3.78 46 2E 4.42 Table 4. IOCHARGE Current as Function of IOCHARGE (REG 04 [6:4]) Bits and RSENSE Resistor Values IOCHARGE Decimal HEX IOCHARGE (mA) VRSENSE (mV) 68 m 100 m 0 00 37.4 550 374 01 44.2 650 442 15 0F 3.80 47 2F 4.44 1 16 10 3.82 48 30 4.44 2 02 51.0 750 510 17 11 3.84 49 31 4.44 3 03 57.8 850 578 18 12 3.86 50 32 4.44 4 04 71.4 1050 714 05 78.2 1150 782 19 13 3.88 51 33 4.44 5 20 14 3.90 52 34 4.44 6 06 91.8 1350 918 21 15 3.92 53 35 4.44 7 07 98.6 1450 986 22 16 3.94 54 36 4.44 23 17 3.96 55 37 4.44 Termination Current Limit 24 18 3.98 56 38 4.44 25 19 4.00 57 39 4.44 Current charge termination is enabled when TE (REG 01[3])=1. 26 1A 4.02 58 3A 4.44 27 1B 4.04 59 3B 4.44 28 1C 4.06 60 3C 4.44 29 1D 4.08 61 3D 4.44 30 1E 4.10 62 3E 4.44 Table 5. ITERM Current as Function of ITERM Bits (REG 04[2:0]) and RSENSE Resistor Values ITERM Decimal HEX ITERM (mA) VRSENSE (mV) 68 m 100 m 49 33 The following charging parameters can be programmed by 2 the host through I C: 0 00 3.3 1 01 6.6 97 66 Table 3. Programmable Charging Parameters 2 02 9.9 146 99 Parameter Output Voltage Regulation Battery Charging Current Limit Name Register 3 03 13.2 194 132 VOREG REG 02[7:2] 4 04 16.5 243 165 IOCHARGE REG 04[6:4] 5 05 19.8 291 198 Input Current Limit IINLIM REG 01[7:6] 6 06 23.1 340 231 Charge Termination Limit ITERM REG 04[2:0] 7 07 26.4 388 264 Weak Battery Voltage VLOWV REG 01[5:4] (c) 2015 Fairchild Semiconductor Corporation FAN54005 * Rev. 1.1 www.fairchildsemi.com 17 FAN54005 -- USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator A new charge cycle begins when one of the following occurs: Table 2. OREG Bits (REG 02[7:2]) vs. Charger VOUT (VOREG) Float Voltage USB-Friendly Boot Sequence 2 At VBUS POR, the IC operates in accordance with its I C register settings. If no registers have been written (including Safety, and the TMR_RST bit), typically due to an absence of host communication, the chargers input current limit is controlled by the OTG pin (100 mA if OTG is LOW and 500 mA if OTG is HIGH). PWM Controller in Charge Mode The IC uses a current-mode PWM controller to regulate the output voltage and battery charge currents. The synchronous rectifier (Q2) has a current limit that which off the FET when the current is negative by more than 140 mA peak. This prevents current flow from the battery. Once the host processor begins writing to the IC, charging parameters are set by the host, which must continually reset the t32S timer to continue charging using the programmed charging parameters. Input Current Limiting Charger Operation To minimize charging time without overloading VBUS current limitations, the IC's input current limit can be programmed by the IINLIM bits (REG 01[7:6]). VBUS Plug In When the IC detects that VBUS has risen above VIN(MIN)1 (4.4 V), the IC applies a 100 load from VBUS to GND. To clear the VBUS Power-On-Reset (POR) and begin charging, VBUS must remain above VIN(MIN)1 and below VBUSOVP for tVBUS_VALID (30 ms) before the IC initiates charging. Table 6. The VBUS validation sequence always occurs before charging is initiated or re-initiated (for example, after a VBUS OVP fault or a VRCH recharge initiation). TVBUS_VALID ensures that unfiltered 50 / 60 Hz chargers and other non-compliant chargers are rejected. Input Current Limit IINLIM REG 01[7:6] Input Current Limit 00 100 mA 01 500 mA 10 800 mA 11 No limit The OTG pin establishes the input current limit when t15MIN is running. Safety Timer Section references Figure 39. At the beginning of charging, the IC starts a 15-minute timer (t15MIN). When this times out, charging is terminated. Writing 2 to any register through I C stops and resets the t15MIN timer, which in turn starts a 32-second timer (t32S). Setting the TMR_RST bit (REG 00[7]) resets the t32S timer. If the t32S timer times out; charging is terminated, all registers (except Safety) are set to their default values, the FAULT bits are set to 110, STAT is pulsed HIGH and returns LOW, and charging resumes using the default values with the t 15MIN timer running. Normal charging is controlled by the host with the t 32S timer running to ensure that the host is alive. Charging with the t15MIN timer running is used for charging that is unattended by the host. If the t15MIN timer expires; the IC turns off the charger, sets the CE bit, and indicates a timer fault (110) on the FAULT bits (REG 00[2:0]). This sequence prevents overcharge if the host fails to reset the t32S timer. (c) 2015 Fairchild Semiconductor Corporation FAN54005 * Rev. 1.1 www.fairchildsemi.com 18 FAN54005 -- USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator When the charge current falls below ITERM, PWM charging stops and the STAT bits change to READY (00) for about 500 ms while the IC determines whether the battery and charging source are still connected. STAT then changes to CHARGE DONE (10), provided the battery and charger are still connected. FAN54005 -- USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator Flow Charts VBUS POR YES CE or HZ, CE# DISABLE Pin set? YES VBAT > VLOWV HZ State NO NO Charge Configuration State NO CE or HZ, CE# DISABLE Pin set? NO T15Min Timer? YES NO T32Sec Armed? YES YES CE or HZ, CE# DISABLE Pin set? YES NO HZ State T32Sec Armed? YES NO Figure 36. (c) 2015 Fairchild Semiconductor Corporation FAN54005 * Rev. 1.1 Charge State Reset all registers Start T15MIN Charger VBUS POR www.fairchildsemi.com 19 CHARGE STATE Disable Charging NO Indicate VBUS Fault VBAT < VSHORT Enable ISHORT , Reset Safety reg YES VBUS OK? NO Indicate Charging NO YES PWM Charging VBUS OK? T15MIN Timeout? YES Indicate Charging NO YES Disable Charging Indicate timer fault T15MIN Timeout? Indicate VBUS Fault YES Set CE Charge Configuration State NO NO HIGHZ mode NO IOUT < ITERM Termination enabled VBAT > VOREG-VRCH VBAT < VOREG-VRCH Indicate Charge Complete Reset Safety reg Delay tINT NO YES Battery Removed Stop Charging VBAT < VOREG-VRCH Enable IDET for TDETECT Figure 37. (c) 2015 Fairchild Semiconductor Corporation FAN54005 * Rev. 1.1 YES YES Reset charge parameters Charge Mode www.fairchildsemi.com 20 FAN54005 -- USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator Flow Charts (Continued) Charge Configuration State T32Sec ARMED AND CE = 0? CE# YES Charge State NO Has T15Min CE = 0 and CE# NO START T15Min YES VBAT < VOREG for 262ms? NO Figure 38. YES Charge Configuration Charge Start Start T15MIN Reset Registers YES T32SEC NO Expired? Start T32SEC Stop T15MIN T15MIN Active? YES YES NO I2C Write received? NO Timer Fault : Set CE CE Figure 39. (c) 2015 Fairchild Semiconductor Corporation FAN54005 * Rev. 1.1 T15MIN Expired? NO Continue Charging YES Timer Flow Chart www.fairchildsemi.com 21 FAN54005 -- USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator Flow Charts (Continued) The FAN54005 has functionality that limits input current in case a current-limited incompatible adapter is supplying VBUS. These slowly increase the charging current until either: ISAFE Decimal IINLIM or IOCHARGE is reached or HEX ISAFE (mA) VRSENSE (mV) 68 m 100 m 0 00 37.4 550 374 1 01 44.2 650 442 If VBUS collapses to VSP when the current is ramping up, the FAN54005 charges with an input current that keeps VBUS=VSP. When the VSP control loop is limiting the charge current, the SP bit (REG 05[4]) is set. 2 02 51.0 750 510 3 03 57.8 850 578 4 04 71.4 1050 714 Table 7. 05[2:0]) 5 05 78.2 1150 782 6 06 91.8 1350 918 7 07 98.6 1450 986 VBUS=VSP. VSP as Function of VSP Bits (REG VSP Decimal HEX VSP 0 00 4.213 1 01 4.293 2 02 4.373 3 03 4.453 4 04 4.533 5 05 4.613 6 06 4.693 7 07 4.773 Table 9. VSAFE (VOREG Max. Limit) as Function of VSAFE Bits (REG 06[3:0]) VSAFE Safety Settings FAN54005 contain a SAFETY register (REG 06) that prevents the values in OREG (REG 02[7:2]) and IOCHARGE (REG 04[6:4]) from exceeding the values of the VSAFE and ISAFE values. Refer to Table 8 and Table 9 for details. After VBAT exceeds VSHORT, the SAFETY register is loaded with its default value and may be written only before any other register is written. The entire desired Safety register value should be written twice to ensure the register bits are set. After writing to any other register, the SAFETY register is locked until VBAT falls below VSHORT. The ISAFE (REG 06[6:4]) and VSAFE (REG 06[3:0]) registers establish values that limit the maximum values of IOCHARGE and VOREG used by the control logic. If the host attempts to write a value higher than VSAFE or ISAFE to OREG or IOCHARGE, respectively; the VSAFE, ISAFE value appears as the OREG, IOCHARGE register value, respectively. (c) 2015 Fairchild Semiconductor Corporation FAN54005 * Rev. 1.1 Decimal HEX Max. OREG (REG 02[7:2]) VOREG Max. (V) 0 00 100011 4.20 1 01 100100 4.22 2 02 100101 4.24 3 03 100110 4.26 4 04 100111 4.28 5 05 101000 4.30 6 06 101001 4.32 7 07 101010 4.34 8 08 101011 4.36 9 09 101100 4.38 10 0A 101101 4.40 11 0B 101110 4.42 12 0C 101111 4.44 13 0D 110000 4.44 14 0E 110001 4.44 15 0F 110010 4.44 Thermal Regulation and Protection When the IC's junction temperature reaches T CF (about 120C), the charger reduces its output current to 550 mA to prevent overheating. If the temperature increases beyond TSHUTDOWN; charging is suspended, the FAULT bits are set to 101, and STAT is pulsed HIGH. In Suspend Mode, all timers stop and the state of the IC's logic is preserved. Charging resumes at programmed current after the die cools to about 120C. www.fairchildsemi.com 22 FAN54005 -- USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator Table 8. ISAFE (IOCHARGE Limit) as Function of ISAFE Bits (REG 06[6:4]) Dynamic Input Voltage Control Battery Detection during Charging The IC can detect the presence, absence, or removal of a battery if the termination bit (TE) is set. During normal charging, once VBAT is close to VOREG and the termination charge current is detected, the IC terminates charging and sets the STAT bits to 10. It then turns on a discharge current, IDETECT, for tDETECT. If VBAT is still above VOREG - VRCH, the battery is present and the IC sets the FAULT bits to 000. If VBAT is below VOREG - VRCH, the battery is absent and the IC: 1. Sets the registers to their default values. 2. Sets the FAULT bits to 111. 3. Resumes charging with default values after tINT. Table 10. Evaluation Board Measured JA Power (W) JA 0.504 54C/W 0.844 50C/W 1.506 46C/W Battery Short-Circuit Protection If the battery voltage is below the short-circuit threshold (VSHORT); a linear current source, ISHORT, supplies VBAT until VBAT > VSHORT. Charge Mode Input Supply Protection Sleep Mode When VBUS falls below VBAT + VSLP, and VBUS is above VIN(MIN)1, the IC enters Sleep Mode to prevent the battery from draining into VBUS. During Sleep Mode, reverse current is disabled by body switching Q1. System Operation with No Battery The FAN54005 continues charging after VBUS POR with the default parameters, regulating the VBAT line to 3.54 V until the host processor issues commands or the t15MIN timer expires. In this way, the FAN54005 can start the system without a battery. The FAN54005 soft-start function can interfere with the system supply with battery absent. The soft-start activates whenever VOREG, IINLIM, or IOCHARGE are set from a lower to higher value. During soft-start, the IIN limit drops to 100 mA for about 1 ms unless IINLIM is set to 11 (no limit). This could cause the system processor to fail to start. To avoid this behavior, use the following sequence. 1. Set the OTG pin HIGH. When VBUS is plugged in, IINLIM is set to 500 mA until the system processor powers up 2 and can set parameters through I C. 2. Program the Safety Register. 3. Set IINLIM to 11 (no limit). 4. Set OREG to the desired value (typically 4.18). 5. Reset the IO_LEVEL bit, then set IOCHARGE. 6. Set IINLIM to 500 mA if a USB source is connected. During the initial system startup, while the charger IC is being programmed, the system current is limited to 500 mA for 1 ms during steps 4 and 5. This is the value of the softstart IOCHARGE current used when IINLIM is set to No Limit. Input Supply Low-Voltage Detection The IC continuously monitors VBUS during charging. If VBUS falls below VIN(MIN)2, the IC: 1. Terminates charging 2. Pulses the STAT pin, sets the STAT bits to 11, and sets the FAULT bits to 011. If VBUS recovers above the VIN(MIN)1 rising threshold after time tINT (about two seconds), the charging process is repeated. This function prevents the USB power bus from collapsing or oscillating when the IC is connected to a suspended USB port or a low-current-capable OTG device. Input Over-Voltage Detection When VBUS exceeds VBUSOVP, the IC: 1. Turns off Q3 2. Suspends charging 3. Sets the FAULT bits to 001, sets the STAT bits to 11, and pulses the STAT pin. When VBUS falls about 100 mV below VBUSOVP, the fault is cleared and charging resumes after VBUS is revalidated. VBUS Short While Charging If VBUS is shorted with a very low impedance while the IC is charging with IINLIMIT =100 mA, the IC may not meet datasheet specifications until power is removed. To trigger this condition, VBUS must be driven from 5 V to GND with a high slew rate. Achieving this slew rate requires a 0 short from GND to the USB cable that is less than 10 cm from the connector. If the system is powered up without a battery present, the CV bit should be set. When a battery is inserted, the CV bit is cleared. Charger Status / Fault Status The STAT pin indicates the operating condition of the IC and provides a fault indicator for interrupt driven systems. Charge Mode Battery Detection & Protection VBAT Over-Voltage Protection The OREG voltage regulation loop prevents V BAT from overshooting the OREG voltage by more than 50 mV when the battery is removed. When the PWM charger runs with no battery, the TE bit is not set, and a battery is inserted that is charged to a voltage higher than VOREG; PWM pulses stop. If no further pulses occur for 30 ms, the IC sets the FAULT bits to 100, sets the STAT bits to 11, and pulses the STAT pin. (c) 2015 Fairchild Semiconductor Corporation FAN54005 * Rev. 1.1 Table 11. STAT Pin Function EN_STAT Charge State STAT Pin 0 X OPEN X Normal Conditions OPEN 1 Charging LOW X Fault (Charging or Boost) 128 s Pulse, then OPEN www.fairchildsemi.com 23 FAN54005 -- USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator Additional JA data points, measured using the FAN54005 evaluation board, are given in Table 10 (measured with TA=25C). Note that as power dissipation increases, the effective JA decreases due to the larger difference between the die temperature and ambient. Table 14. Operation Mode Control HZ_MODE OPA_MODE FAULT Operation Mode Table 12. Fault Status Bits During Charge Mode Fault Bit Fault Description B2 B1 B0 0 0 0 Normal (No Fault) 0 0 1 VBUS OVP 0 1 0 Sleep Mode 0 1 1 Poor Input Source 1 0 0 Battery OVP 1 0 1 Thermal Shutdown 1 1 0 Timer Fault 1 1 1 No Battery 0 0 0 Charge 0 X 1 Charge Configure 0 1 0 Boost 1 X X High Impedance The IC resets the OPA_MODE bit whenever the boost is deactivated, whether due to a fault or being disabled by setting the HZ_MODE bit. Boost Mode Boost Mode can be enabled if the IC is in 32-Second Mode with the OTG pin and OPA_MODE bits as indicated in Table 15. The OTG pin ACTIVE state is 1 if OTG_PL=1 and 0 when OTG_PL=0. Charge Mode Control Bits If boost is active using the OTG pin, Boost Mode is initiated even if the HZ_MODE=1. The HZ_MODE bit overrides the OPA_MODE bit. 2 Setting either HZ_MODE or CE through I C disables the charger and puts the IC into High-Impedance Mode. The t32S timer will continue to run. If it is allowed to expire, all registers (except SAFETY) reset, which enables t15MIN Table 15. Enabling Boost charging. When the t15MIN expires, the IC sets the CE bit OTG_EN HZ_ MODE OPA_ MODE BOOST and the IC enters High-Impedance Mode. If CE was set by t15MIN overflow, a new charge cycle can only be initiated 2 through I C or VBUS POR. OTG Pin 1 ACTIVE X X Enabled X X 0 1 Enabled Setting the RESET bit clears all registers (except Safety). X ACTIVE X 0 Disabled Table 13. DISABLE Pin and CE Bit Functionality 0 X 1 X Disabled Charging DISABLE Pin CE HZ_MODE 1 ACTIVE 1 1 Disabled ENABLE 0 0 0 0 ACTIVE 0 0 Disabled DISABLE X 1 X DISABLE X X 1 DISABLE 1 X X To remain in Boost Mode, the TMR_RST must be set by the host before the t32S timer times out. If t32S times out in Boost Mode; the IC resets all registers, pulses the STAT pin, sets the FAULT bits to 110, and resets the BOOST bit. VBUS POR or reading REG00 clears the fault condition. Raising the DISABLE pin does stop the t32S from advancing. If the DISABLE pin is raised during t15MIN charging, the t15MIN timer is reset. Boost PWM Control The IC uses a minimum on-time and computed minimum offtime to regulate VBUS. The regulator achieves excellent transient response by employing current-mode modulation. This technique causes the regulator to exhibit a load line. During PWM Mode, the output voltage drops slightly as the input current rises. With a constant VBAT, this appears as a constant output resistance. Operational Mode Control OPA_MODE (REG 01[0]) and the HZ_MODE (REG 01[1]) bits in conjunction with the FAULT state define the operational mode of the charger. The "droop" caused by the output resistance when a load is applied allows the regulator to respond smoothly to load transients with no undershoot from the load line. This can be seen in Figure 32 and Figure 40. (c) 2015 Fairchild Semiconductor Corporation FAN54005 * Rev. 1.1 www.fairchildsemi.com 24 FAN54005 -- USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator The FAULT bits (REG 00[2:0]) indicate the type of fault in Charge Mode. See Table 12 for details. When PMID > VBAT - 400 mV, the boost regulator begins switching with a reduced peak current limit of about 50% of its normal current limit. The output slews up until VBUS is within 5% of its setpoint; at which time, the regulation loop is closed and the current limit is set to 100%. Output Resistance (mW) 325 300 275 If the output fails to achieve 95% of its setpoint (VBST) within 128 s, the current limit is increased to 100%. If the output fails to achieve 95% of its setpoint after this second 384 s period, a fault state is initiated. 250 225 BST State 200 2.0 2.5 3.0 3.5 4.0 4.5 5.0 This is the normal operating mode of the regulator. The regulator uses a scheme of calculated tOFF, modulated tON with a minimum tON. The calculated tOFF is proportional to Battery Voltage, VBAT (V) Figure 40. Output Resistance (ROUT) VIN , which keeps the regulator's switching frequency VOUT VBUS as a function of ILOAD can be computed when the regulator is in PWM Mode (continuous conduction) as: reasonably constant in CCM. VBUS 5.07 ROUT I LOAD (1) To ensure VBUS does not pump significantly above the regulation point, the boost switch remains off as long as the actual output voltage is greater than the regulation point. At VBAT=3.3 V, and ILOAD=200 mA, VBUS would drop to: VBUS 5.07 0.26 0.2 5.018V Boost Faults (1A) If a BOOST fault occurs: 1. The STAT pin pulses. 2. OPA_MODE bit is reset. 3. The power stage is in High-Impedance Mode. 4. The FAULT bits (REG 00[2:0]) are set per Table 17 At VBAT=2.7 V, and ILOAD=200 mA, VBUS would drop to: VBUS 5.07 0.327 0.2 5.005V (1B) PFM Mode Restart After Boost Faults If VBUS > VBOOST (nominally 5.07 V) when the minimum offtime has ended, the regulator enters PFM Mode. Boost pulses are inhibited until VBUS < VBOOST. The minimum ontime is increased to enable the output to pump up sufficiently with each PFM boost pulse. Therefore the regulator behaves like a constant on-time regulator, with the bottom of its output voltage ripple at 5.07 V in PFM Mode. If boost was enabled with the OPA_MODE bit and OTG_EN=0, Boost Mode can only be enabled through 2 subsequent I C commands since OPA_MODE is reset on boost faults. If OTG_EN=1 and the OTG pin is still ACTIVE (see Table 15), the boost restarts after a 5.2 ms delay, as shown in Figure 41. If the fault condition persists, restart is 2 attempted every 5 ms until the fault clears or an I C command disables the boost. Table 16. Boost PWM Operating States Mode Description Invoked When LIN Linear Startup VBAT > VBUS SS Boost Soft-Start VBUS < VBOOST BST Boost Operating Mode VBAT > UVLOBST and SS Completed Table 17. Fault Bits During Boost Mode Fault Bit B2 B1 B0 Fault Description 0 0 0 Normal (no fault) 0 0 1 VBUS > VBUSOVP Startup When the boost regulator is shut down, current flow is prevented from VBAT to VBUS, as well as reverse flow from VBUS to VBAT. 0 1 0 VBUS fails to achieve the voltage required to advance to the next state during soft-start or sustained (>50 s) current limit during the BST state. LIN State 0 1 1 VBAT < UVLOBST When the boost is enabled, if VBAT > UVLOBST, the regulator first attempts to bring PMID within 400 mV of VBAT using an internal 450 mA current source from VBAT (LIN State). If PMID has not achieved VBAT - 400 mV after 560 s, a FAULT state is initiated. 1 0 0 N/A: This code does not appear. 1 0 1 Thermal shutdown 1 1 0 Timer fault; all registers reset. 1 1 1 N/A: This code does not appear. (c) 2015 Fairchild Semiconductor Corporation FAN54005 * Rev. 1.1 www.fairchildsemi.com 25 FAN54005 -- USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator SS State 350 560 5200 450mA BATTERY CURRENT Monitor Register (Reg 10h) 0 64 Additional status monitoring bits enable the host processor to have more visibility into the status of the IC. The monitor bits are real-time status indicators and are not internally debounced or otherwise time qualified. BOOST ENABLED Figure 41. Boost Response Attempting to Start into VBUS Short Circuit (times in s) The state of the MONITOR register bits listed in HighImpedance Mode is only valid when VBUS is valid. VREG Pin The 1.8 V regulated output on this pin can be disabled 2 through I C by setting the DIS_VREG bit (REG 05[6]). VREG can supply up to 2 mA. This circuit, which is powered from (c) 2015 Fairchild Semiconductor Corporation FAN54005 * Rev. 1.1 www.fairchildsemi.com 26 FAN54005 -- USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator PMID, is enabled only when PMID > VBAT and does not drain current from the battery. During boost, VREG is off. It is also off when the HZ_MODE bit (REG 01[1])=1. VBUS 0 The FAN54005's serial interface is compatible with 2 (R) Standard, Fast, Fast Plus, and High-Speed Mode I C-Bus specifications. The SCL line is an input and the SDA line is a bi-directional open-drain output; it can only pull down the bus when active. The SDA line only pulls LOW during data reads and signaling ACK. All data is shifted in MSB (bit 7) first. During a read from the FAN54005 (Figure 47), the master issues a Repeated Start after sending the register address and before resending the slave address. The Repeated Start is a 1-to-0 transition on SDA while SCL is HIGH, as shown in Figure 45. High-Speed (HS) Mode Slave Address The protocols for High-Speed (HS), Low-Speed (LS), and Fast-Speed (FS) Modes are identical except the bus speed for HS Mode is 3.4 MHz. HS Mode is entered when the bus master sends the HS master code 00001XXX after a start condition. The master code is sent in Fast or Fast Plus Mode (less than 1 MHz clock); slaves do not ACK this transmission. 2 Table 18. I C Slave Address Byte Part Type 7 6 5 4 3 2 1 0 FAN54005 1 1 0 1 0 1 0 R/ W In hex notation, the slave address assumes a 0 LSB. The hex slave address for the FAN54005 is D4H and is D6H for all other parts in the family. The master then generates a repeated start condition (Figure 45) that causes all slaves on the bus to switch to HS 2 Mode. The master then sends I C packets, as described above, using the HS Mode clock rate and timing. Bus Timing The bus remains in HS Mode until a stop bit (Figure 44) is sent by the master. While in HS Mode, packets are separated by repeated start conditions (Figure 45). As shown in Figure 42, data is normally transferred when SCL is LOW. Data is clocked in on the rising edge of SCL. Typically, data transitions shortly at or after the falling edge of SCL to allow ample time for the data to set up before the next SCL rising edge. Slave Releases SDA Data change allowed ACK(0) or NACK(1) Figure 45. TH TSU SCL Figure 42. SLADDR MS Bit The figures below outline the sequences for data read and write. Bus control is signified by the shading of the packet, Data Transfer Timing THD;STA Master Drives Bus defined as and All addresses and data are MSB first. SCL Master Drives . Definition S START, see Figure 43 A ACK. The slave drives SDA to 0 to acknowledge the preceding packet. A NACK. The slave sends a 1 to NACK the preceding packet. R Repeated START, see Figure 45 P STOP, see Figure 44 Start Bit A transaction ends with a STOP condition, which is defined as SDA transitioning from 0 to 1 with SCL HIGH, as shown in Figure 44. Slave Releases Slave Drives Bus Table 19. Bit Definitions for Figure 46 and Figure 47 Slave Address MS Bit Symbol Figure 43. Repeated Start Timing Read and Write Transactions Each bus transaction begins and ends with SDA and SCL HIGH. A transaction begins with a START condition, which is defined as SDA transitioning from 1 to 0 with SCL HIGH, as shown in Figure 43. SDA tHD;STA SCL SDA SDA tSU;STA tHD;STO ACK(0) or NACK(1) SCL Figure 44. (c) 2015 Fairchild Semiconductor Corporation FAN54005 * Rev. 1.1 Stop Bit www.fairchildsemi.com 27 FAN54005 -- USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator I2C Interface S Slave Address 0 0 8 bits 0 8 bits 0 A Reg Addr A Data A Figure 46. 7 bits S Slave Address 0 P Write Transaction 0 8 bits 0 A Reg Addr A Figure 47. 7 bits R Slave Address 1 0 8 bits 1 A Data A P Read Transaction Register Descriptions The nine FAN54005 user-accessible registers are defined in Table 20. 2 Table 20. I C Register Address Register Address Bits Name REG# 7 6 5 4 3 2 1 0 CONTROL0 00 0 0 0 0 0 0 0 0 CONTROL1 01 0 0 0 0 0 0 0 1 OREG 02 0 0 0 0 0 0 1 0 IC_INFO 03 0 0 0 0 0 0 1 1 IBAT 04 0 0 0 0 0 1 0 0 SP_CHARGER 05 0 0 0 0 0 1 0 1 SAFETY 06 0 0 0 0 0 1 1 0 MONITOR 10h 0 0 0 0 1 0 1 0 Table 21. Register Bit Definitions This table defines the operation of each register bit for all IC versions. Default values are in bold text. Bit Name Value Type CONTROL0 7 TMR_RST OTG 6 EN_STAT Register Address: 00 1 0 STAT 3 BOOST Writing a 1 resets the t32S timer; writing a 0 has no effect R Returns the OTG pin level (1=HIGH) R/W 2:0 FAULT Prevents STAT pin from going LOW during charging; STAT pin still pulses to enunciate faults Enables STAT pin LOW when IC is charging R Ready 01 Charge in progress 10 Charge done 11 Fault 0 Default Value=X1XX 0XXX W 1 00 5:4 Description R 1 IC is not in Boost Mode IC is in Boost Mode R Fault status bits: for Charge Mode, see Table 12 Continued on the following page... (c) 2015 Fairchild Semiconductor Corporation FAN54005 * Rev. 1.1 www.fairchildsemi.com 28 FAN54005 -- USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator 7 bits Bit Name Value Type CONTROL1 7:6 Register Address: 01 IINLIM 5:4 01 R/W Input current limit, see Table 6 00 R/W 3.4 V 01 3.5 V 10 3.6 V 11 3.7 V VLOWV Default Value=0111 0000 (70h) Weak battery voltage threshold 0 3 R/W Disable charge current termination TE 1 0 2 CE Enable charge current termination R/W 1 0 1 Charger enabled. Charger disabled. The T32S timer is not suspended R/W Not High-Impedance Mode HZ_MODE 1 0 0 Description High-Impedance Mode R/W See Table 15 Charge Mode OPA_MODE 1 Boost Mode OREG Register Address: 02 7:2 OREG 1 OTG_PL 0 OTG_EN Default Value=0000 1010 (0Ah) 000010 R/W Charger output "float" voltage; programmable from 3.5 to 4.44 V in 20 mV increments; defaults to 000010 (3.54 V). See Table 2 0 R/W OTG pin active LOW 1 0 OTG pin active HIGH R/W 1 Disables OTG pin Enables OTG pin IC_INFO Register Address: 03 Default Value=100101XX (9Xh) 7:5 Vendor Code 100 R Identifies Fairchild Semiconductor as the IC supplier 4:2 PN 101 R Part number bits, see the Ordering Information on page 2 1:0 REV XX R IBAT IC Revision bits Register Address: 04 7 RESET 1 W 6:4 IOCHARGE 000 R/W 3 Reserved 1 R 2:0 ITERM 001 R/W Default Value=1000 1001 (89h) Writing a 1 resets charge parameters, except the Safety register (REG 06), to their defaults: writing a 0 has no effect; read returns 1 Programs the maximum charge current when IO_LEVEL (REG 05[5]) = 0. See Table 4 Unused Sets the current used for charging termination. See Table 5 Continued on the following page... (c) 2015 Fairchild Semiconductor Corporation FAN54005 * Rev. 1.1 www.fairchildsemi.com 29 FAN54005 -- USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator Register Bit Definitions (Continued) SP_CHARGER 7 Reserved 6 DIS_VREG Register Address: 05 0 R 0 R/W 1 0 5 IO_LEVEL 4 SP 3 EN_LEVEL 2:0 VSP R R DIVC is not active (VBUS is able to stay above VSP) DISABLE pin is LOW DISABLE pin is HIGH R/W SAFETY 7 Output current is controlled by IOCHARGE bits DIVC has been detected and VBUS is being regulated to VSP 1 100 1.8 V regulator is ON Output current control is set to 34 mV across RSENSE (500 mA for RSENSE=68 m and 340 mA for 100 m) 1 0 Unused 1.8 V regulator is OFF R/W 1 0 DIVC input regulation voltage. See Table 7 Register Address: 06 Reserved Default Value=001X X100 0 R Default Value=0100 0000 (40h) Bit disabled and always returns 0 when read back 6:4 ISAFE 100 R/W Sets the maximum IOCHARGE value used by the control circuit. See Table 8 3:0 VSAFE 0000 R/W Sets the maximum VOREG used by the control circuit. See Table 9 MONITOR 7 Register Address: 10h (16) ITERM_CMP R ITERM comparator output, 1 when VRSENSE > See Table 5 6 VBAT_CMP R Output of VBAT comparator 1 during charging indicates VBAT > VSHORT 1 during HZ_MODE indicates VBAT > VLOWV 1 during Boost Mode indicated VBAT > UVLOBST 5 LINCHG R 30 mA linear charger ON 4 T_120 R Thermal regulation comparator; when=1 and T_145=0, the charge current is limited to 22.1 mV across RSENSE 3 ICHG R 0 indicates the IOCHARGE loop is controlling the battery charge current 2 IBUS R 0 indicates the IBUS (input current) loop is controlling the battery charge current 1 VBUS_VALID R 1 indicates VBUS has passed validation and is capable of charging R 1 indicates the constant-voltage loop (OREG) had been active at least once since the last VBUS plug in 0 indicates the constant-voltage loop (OREG) had never been reached since the last VBUS plug in or the part is in the Charge Done state with TE=1 0 CV (c) 2015 Fairchild Semiconductor Corporation FAN54005 * Rev. 1.1 www.fairchildsemi.com 30 FAN54005 -- USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator Register Bit Definitions (Continued) Bypass capacitors should be placed as close to the IC as possible. In particular, the total loop length for CMID should be minimized to reduce overshoot and ringing on the SW, PMID, and VBUS pins. All power and ground pins must be Figure 48. routed to their bypass capacitors, using top copper whenever possible. Copper area connecting to the IC should be maximized to improve thermal performance if possible. PCB Layout Recommendations The table below pertains to the MOD information on the following page. Product-Specific Dimensions Product D E X Y FAN54005UCX 1.960 +0.030 mm 1.870 +0.030 mm 0.335 mm 0.180 mm (c) 2015 Fairchild Semiconductor Corporation FAN54005 * Rev. 1.1 www.fairchildsemi.com 31 FAN54005 -- USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator PCB Layout Recommendations BALL A1 INDEX AREA F A E 1.20 B A1 Cu Pad 0.03 C 1.20 A1 2X 1.60 D 0.40 Mask Opening Mask Opening 0.40 0.40 option 1 0.03 C 2X TOP VIEW Cu Pad option 2 RECOMMENDED LAND PATTERN (NSMD TYPE) 0.06 C 0.625 0.547 0.05 C E C SEATING PLANE SIDE VIEWS D 0.005 1.20 0.40 20X E D C B 1.60 0.40 A 1 2 3 4 BOTTOM VIEW F C A B NOTES: A. NO JEDEC REGISTRATION APPLIES. B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCE PER ASMEY14.5M, 2009. D. DATUM C IS DEFINED BY THE SPHERICAL CROWNS OF THE BALLS. E. PACKAGE NOMINAL HEIGHT IS 586 MICRONS F. FOR DIMENSIONS D, E, X, AND Y SEE PRODUCT DATASHEET. G. DRAWING FILNAME: MKT-UC020AArev4. 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