FEATURES FUNCTIONAL BLOCK DIAGRAM Flexible architecture to interface with all digital-to-analog converters (DACs) Accepts differential current or voltage input (provides single-ended voltage output) High output current drive capability Greater than 100 mA rms output current Accurately reproduces large music transients into heavy loads (16 to 32 ) Excellent audio fidelity -121 dB total harmonic distortion plus noise (THD + N) at 1 kHz, 2 V rms output with 5 V supply and 32 load Low output integrated noise (10 Hz to 22 kHz) of 1.8 V rms with A-weighted filter Supply range: 3.3 V to 6 V (typical) Low power operation Enabled: 60 mW, VCC = +5 V, VEE = -5 V Disabled/voice select: <30 A Low power disable mode with high output impedance High-Z in power-down mode eliminating voice mode switch from the high fidelity path Greater than 87 dB power supply rejection ratio (PSRR) at 20 kHz Adjustable input common-mode voltage with resistor programmable reference voltage 1.45 V (typical) with no external components Capable of two single-pole, low-pass filters in series 2.2 nF maximum input capacitor Second filter between the GAINx and FILTx pins Pop and click noise suppression Signal chain integration supports small printed circuit board (PCB) area Compact 4 mm x 4 mm LFCSP package APPLICATIONS High fidelity headphone drivers Mobile phones Bluetooth speakers and headphones Gaming notebooks and tablets A/V receivers Professional audio equipment Audio test equipment Automobile infotainment systems Rev. 0 20 19 VEE1 VCC1 24 23 GAIN1 FILT1 21 GND4 SSM6322 2 1 VP1 INPUT VN1 VOUT1 3 GND1 VNFB1 17 REF1 SD 22 9 18 OUTPUT 16 REF2 SD2 15 4 GND2 5 6 VP2 INPUT VN2 VOUT2 13 OUTPUT VNFB2 14 VEE2 VCC2 11 12 GAIN2 FILT2 7 8 GND3 10 15260-001 Data Sheet High Fidelity, Low Power, Integrated Stereo Audio Amplifier SSM6322 Figure 1. GENERAL DESCRIPTION The SSM6322 is an integrated, dual-channel audio amplifier solution that interfaces directly with audio DAC/CODEC, maximizing the fidelity of high fidelity audio signal chains. The highly efficient design of the SSM6322 delivers outstanding audio performance while minimizing power dissipation for maximum battery life in portable applications. The SSM6322 features -121 dB THD + N at 1 kHz, along with very low output noise from 20 Hz to 20 kHz. The low power operation, high peak output current, and high PSRR make the SSM6322 an ideal candidate for applications that require high fidelity audio, high dynamic range, precision, and low power. This highly integrated drive solution also reduces development time while reducing board space and minimizing external components. The SSM6322 is available in a 24-lead LFCSP package. The SSM6322 operates over the industrial temperature of -40C to +85C. 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Technical Support www.analog.com SSM6322 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................8 Applications ....................................................................................... 1 Test Circuit ...................................................................................... 14 Functional Block Diagram .............................................................. 1 Theory of Operation ...................................................................... 15 General Description ......................................................................... 1 Applications Information .............................................................. 16 Revision History ............................................................................... 2 Headphone Drivers in Mobile Phones .................................... 16 Specifications..................................................................................... 3 Common-Mode Control Circuit.............................................. 16 5 V Supply ................................................................................... 3 Capacitive Load Drive ............................................................... 17 3.3 V Supply ................................................................................ 4 SSM6322 in a Headphone Driver Application ....................... 18 Absolute Maximum Ratings............................................................ 6 Design Guidelines ...................................................................... 19 Thermal Resistance ...................................................................... 6 Outline Dimensions ....................................................................... 20 ESD Caution .................................................................................. 6 Ordering Guide .......................................................................... 20 Pin Configuration and Function Descriptions ............................. 7 REVISION HISTORY 3/2017--Revision 0: Initial Version Rev. 0 | Page 2 of 20 Data Sheet SSM6322 SPECIFICATIONS 5 V SUPPLY TA = 25C, reference voltage (VREF) = 0 V, feedback resistor (RF) = gain resistor (RG) = 1 k (see Figure 38), unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE Gain Bandwidth Slew Rate Channel Separation DISTORTION PERFORMANCE THD + N Intermodulation Distortion (IMD) NOISE PERFORMANCE A-Weight Output Noise Input Voltage Noise Input Current Noise DC PERFORMANCE Output Offset Voltage Output Offset Voltage Drift Input Bias Current Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection VREF1/VREF2 Open Circuit Voltage Output Current OUTPUT CHARACTERISTICS Output Voltage Swing Each Output Output Current Short-Circuit Current Closed-Loop Output Impedance Test Conditions/Comments Min Typ Max Unit RIN1 = 1 k, RIN2 = 1 k (see Figure 38), output voltage (VOUT) = 0.2 V p-p Gain = 1, VOUT = 2 V step 1 kHz to 10 kHz, input voltage (VIN) = 5 V p-p, RL = 600 , 32 , 16 25 MHz 18 -140 V/s dB 1 kHz, VOUT = 2 V rms, low-pass filter = 80 kHz, RL = 600 1 kHz, VOUT =2 V rms, low-pass filter = 80 kHz, RL = 32 1 kHz, VOUT = 1.6 V rms, low-pass filter = 80 kHz, RL = 16 SMPTE two-tone, 4:1 (60 Hz and 7 kHz), gain = 1, VOUT = 2 V rms, RL = 600 , 90 kHz measurement bandwidth CCIF two-tone (19 kHz and 20 kHz), gain = 1, VOUT = 2 V rms, RL = 600 , 90 kHz measurement bandwidth -122 dB -121 dB -118 dB -125 dB -131 dB f = 10 Hz to 22 kHz f = 10 Hz f = 100 kHz f = 10 Hz f = 100 kHz 1.8 5.2 3.6 10 1.2 V rms nV/Hz nV/Hz pA/Hz pA/Hz VOUT = 2.3 V, RL = 600 107 90 1.5 -1.8 60 120 113 2 1.5 140 pF V dB 1.45 15 V A 3.4 2.9 2.6 100 V V V mA rms +240/-190 0.04 mA -2.4 IDIFF = 3 mA VCM = 1 V Referenced to ground RL = 600 RL = 32 RL = 16 RL = 16 , rms voltage (VRMS) = 1.6 V, THD + N= -118 dB RL = 10 ; source/sink 10 Hz to 20 kHz Rev. 0 | Page 3 of 20 3.3 2.8 2.0 250 7.5 -1 320 V V/C A nA dB SSM6322 Data Sheet Parameter POWER SUPPLY Operating Range Quiescent Current Test Conditions/Comments Quiescent Current Power-Down Mode DC Power Supply Rejection Ratio AC Power Supply Rejection Ratio POWER-DOWN INPUTS Logic High Logic Low VSD = VSD2 = VCCx, VREF = 0 V, per channel -40C TA +85C VSD = 0 V, VSD2 = VCCx, per channel VSD = VSD2 = 0 V, per channel Supply voltage (VSY) = 3.3 V to 5.5 V 20 kHz Min 115 Chip on, referenced to ground Chip off, referenced to ground Typ Max 3.3 to 6 3 3.1 1.4 15 140 87 3.35 >1.5 <0.75 Unit V mA mA mA A dB dB V V 3.3 V SUPPLY TA = 25C, VREF = 0 V, RF = RG = 1 k (see Figure 38), unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Gain Bandwidth Slew Rate Channel Separation DISTORTION PERFORMANCE THD + N NOISE PERFORMANCE A-Weight Output Noise Input Voltage Noise Input Current Noise DC PERFORMANCE Output Offset Voltage Output Offset Voltage Drift Input Bias Current Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection VREF1/VREF2 Open Circuit Voltage Output Current OUTPUT CHARACTERISTICS Output Voltage Swing Each Output Output Current Short-Circuit Current Closed-Loop Output Impedance Test Conditions/Comments Min Typ Max Unit RIN1 = 1 k, RIN2 = 1 k (see Figure 38), VOUT = 0.2 V p-p Gain = 1, VOUT = 2 V step 1 kHz to 10 kHz, VIN = 1 V p-p, RL = 600 , 32 , and 16 25 14 -140 MHz V/s dB 1 kHz, VOUT = 1 V rms, low-pass filter = 80 kHz, RL = 600 1 kHz, VOUT = 1 V rms, low-pass filter = 80 kHz, RL = 32 1 kHz, VOUT = 0.9 V rms, low-pass filter = 80 kHz, RL = 16 -116 -116 -111 dB dB dB f = 10 Hz to 22 kHz f = 10 Hz f = 100 kHz f = 10 Hz f = 100 kHz 1.8 5.2 3.6 10 1.2 V rms nV/Hz nV/Hz pA/Hz pA/Hz VOUT = 2.3 V, RL = 600 90 1.5 -1.8 60 120 -2.4 106 Differential current (IDIFF) = 3 mA Common-mode voltage (VCM) = 0.3 V 109 Referenced to ground RL = 600 RL = 32 RL = 16 RL = 16 , VRMS = 0.9 V, THD + N = -111 dB RL = 10 10 Hz to 20 kHz Rev. 0 | Page 4 of 20 1.6 1.4 1.2 250 7.5 -1 300 V V/C A nA dB 2 0.3 pF V 135 1.45 15 dB V V A 1.7 1.45 1.4 56 +115/-120 0.04 V V V mA rms mA Data Sheet Parameter POWER SUPPLY Operating Range Quiescent Current Quiescent Current Power-Down Mode DC Power Supply Rejection Ratio AC Power Supply Rejection Ratio POWER-DOWN INPUTS Logic High Logic Low SSM6322 Test Conditions/Comments Min 3.3 to 6 2.9 3.0 1.3 VSD = VSD2 = VCCx, VREF = 0 V, per channel -40C TA +85C VSD = 0 V, VSD2 = VCCx VSD = VSD2 = 0 V VSY = 3.3 V to 5.5 V 20 kHz 115 Chip on, referenced to ground Chip off, referenced to ground Rev. 0 | Page 5 of 20 Typ Max 3.35 Unit V mA mA mA 10 140 85 A dB dB >1.5 <0.75 V V SSM6322 Data Sheet ABSOLUTE MAXIMUM RATINGS The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). Table 3. Parameter Supply Voltage Single Supply Dual Supply Exposed Pad Voltage Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering 10 sec) Junction Temperature Rating PD = Quiescent Power + (Total Drive Power - Load Power) 12.6 V 6.3 V -VSY or ground -65C to +125C -40C to + 85C 300C 150C V V PD VS I S S OUT RL 2 Consider the rms output voltages. If RL is referenced to -VSY, as in single-supply operation, the total drive power is VSY x IOUT. If the rms signal levels are indeterminate, consider the worst case, when VOUT = VSY/4 for RL to midsupply. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Thermal performance is directly linked to PCB design and operating environment. Careful attention to PCB thermal design is required. The values in Table 4 were obtained per JEDEC standard JESD51-12. RL Airflow increases heat dissipation, effectively reducing JA. Also, more metal directly in contact with the package leads and exposed paddle from metal traces, through holes, ground, and power planes reduce JA. Board layout impacts thermal characteristics, such as JA. When proper thermal management techniques are used, a better JA value can be achieved. Although the exposed pad can be left floating, it must be connected to an external V- plane or ground plane for proper thermal management. 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -40 -25 -10 5 20 35 50 AMBIENT TEMPERATURE (C) 65 80 15260-002 Unit C/W MAXIMUM POWER DISSIPATION (W) JC 3.3 VS / 42 4.5 Table 4. Thermal Resistance JA 47 PD VS I S Figure 2 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 24-lead LFCSP package on a JEDEC standard 4-layer board. THERMAL RESISTANCE Package Type CP-24-15 VOUT 2 - RL Figure 2. Maximum Power Dissipation vs. Ambient Temperature for a 4-Layer Board Maximum Power Dissipation The maximum safe power dissipation for the SSM6322 is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150C, which is the glass transition temperature, the properties of the plastic change. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the SSM6322. Exceeding a junction temperature of 175C for an extended period can result in changes in silicon devices, potentially causing degradation or loss of functionality. The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the die due to the SSM6322 drive at the output. ESD CAUTION Rev. 0 | Page 6 of 20 Data Sheet SSM6322 20 VEE1 19 VCC1 22 REF1 21 GND4 24 GAIN1 18 VOUT1 VN1 1 VP1 2 17 VNFB1 GND1 3 SSM6322 16 SD GND2 4 TOP VIEW (Not to Scale) 15 SD2 VP2 5 14 VNFB2 VN2 6 VEE2 11 VCC2 12 REF2 9 GND3 10 FILT2 8 GAIN2 7 13 VOUT2 NOTES 1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO A NEGATIVE POWER PLANE (V-) OR GROUND. 15260-003 PIN 1 IDENTIFIER 23 FILT1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 9 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Mnemonic VN1 VP1 GND1 GND2 VP2 VN2 GAIN2 FILT2 REF2 GND3 VEE2 VCC2 VOUT2 VNFB2 SD2 SD VNFB1 VOUT1 VCC1 VEE1 GND4 REF1 FILT1 GAIN1 EPAD Description Negative Input of Channel 1 Input Stage. Positive Input of Channel 1 Input Stage. Ground 1. Ground 2. Positive Input of Channel 2 Input Stage. Negative Input of Channel 2 Input Stage. Output of Channel 2 Input Stage. Positive Input of Channel 2 Output Stage. Input Common-Mode Voltage of Channel 2 Input Stage. Ground 3. Negative Supply 2. This pin is internally shorted to Pin 20. Positive Supply 2. This pin is internally shorted to Pin 19. Output of Channel 2 Output Stage. Negative Feedback of Channel 2 Output Stage. Shuts Down Power for the Entire Device. This pin is referenced to ground. Shuts Down Power for the Output Stage. This pin is referenced to ground. Negative Feedback of Channel 1 Output Stage. Output of Channel 1 Output Stage. Positive Supply 1. This pin is internally shorted to Pin 12. Negative Supply 1. This pin is internally shorted to Pin 11. Ground 4. Input Common-Mode Voltage of Channel 1 Input Stage. Positive Input of Channel 1 Output Stage. Output of Channel 1 Input Stage. Exposed Pad. Connect the exposed pad to a negative power plane (V-) or ground. Rev. 0 | Page 7 of 20 SSM6322 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 20 120 100 0 80 -40 -50 1k PSRR+ PSRR- 40 VSY = 5V VSD = 5V AV = 1 RL = 600 VSY = 3.3V VSD = 3.3V 20 10k 100k 1M 10M 100M FREQUENCY (Hz) 0 1k CHANNEL SEPARATION (dB) CL1 = OPEN CL1 = 10pF CL1 = 25pF CL1 = 150pF CL1 = 100pF CL1 = 200pF VSY = 3.3V VSD = 3.3V AV = 1 RL = 600 -100 RL = OPEN RL = 600 RL = 32 RL = 16 -110 -120 -130 -140 -150 -160 -170 10k 100k 1M 10M 100M FREQUENCY (Hz) -180 20 15260-005 -80 -90 CHANNEL SEPARATION (dB) 100 80 60 PSRR+ PSRR- VSY = 5V VSD = 5V -100 -110 -120 VSY = 3.3V VIN = 1V p-p 80kHz LP FILTER RL = OPEN RL = 600 RL = 32 RL = 16 -130 -140 -150 -160 -170 0 1k 10k 100k 1M FREQUENCY (Hz) 10M -180 20 15260-006 PSRR (dB) 20k Figure 8. Channel Separation vs. Frequency, VSY = 5 V 120 20 2k FREQUENCY (Hz) Figure 5. Frequency Response for Various Capacitive Loads, VSY = 3.3 V 40 200 200 2k 20k FREQUENCY (Hz) Figure 9. Channel Separation vs. Frequency, VSY = 3.3 V Figure 6. PSRR vs. Frequency, VSY = 5 V Rev. 0 | Page 8 of 20 15260-009 CLOSED-LOOP GAIN (dB) -50 1k VSY = 5V VIN = 5V p-p 80kHz LP FILTER -90 0 -40 10M -80 10 -30 1M Figure 7. PSRR vs. Frequency, VSY = 3.3 V 20 -20 100k FREQUENCY (Hz) Figure 4. Frequency Response for Various Capacitive Loads, VSY = 5 V -10 10k 15260-007 -30 60 15260-008 -20 PSRR (dB) -10 CL1 = OPEN CL1 = 10pF CL1 = 25pF CL1 = 150pF CL1 = 100pF CL1 = 200pF 15260-004 CLOSED-LOOP GAIN (dB) 10 Data Sheet SSM6322 0.1 1 RL = 16, VIN = 1.6V rms RL = 32, VIN = 2V rms RL = 600, VIN = 2V rms VSY = 5V VSD = 5V AV = 1 80kHz LP FILTER 0.1 0.0001 0.00001 0.001 RL = 16 RL = 32 RL = 600 0.001 0.0001 VSY = 5V, VSD = 5V AV = 1 FREQUENCY = 1kHz 80kHz LP FILTER 0.01 0.1 1 AMPLITUDE (VRMS) 0.00001 20 200 2k 20k FREQUENCY (Hz) 15260-013 0.001 THD + N (%) 0.01 15260-010 THD + N (%) 0.01 Figure 13. THD + N vs. Frequency, VSY = 5 V Figure 10. THD + N vs. Amplitude, VSY = 5 V 0.1 1 RL = 16, VIN = 0.6V rms RL = 32, VIN = 1V rms RL = 600, VIN = 1V rms VSY = 3.3V VSD = 3.3V AV = 1 80kHz LP FILTER 0.1 0.00001 0.001 0.001 0.0001 VSY = 3.3V, VSD = 3V AV = 1 FREQUENCY = 1kHz 80kHz LP FILTER 0.01 0.1 1 AMPLITUDE (VRMS) 0.00001 20 200 Figure 11. THD + N vs. Amplitude, VSY = 3.3 V INTERMODULATION DISTORTION (dB) 1 0.01 0.00001 0.001 RL = 16 RL = 32 RL = 600 VSY = 6V, VSD = 6V AV = 1 FREQUENCY = 1kHz 80kHz LP FILTER 0.01 0.1 AMPLITUDE (VRMS) 1 15260-012 THD + N (%) 0.1 0.0001 20k Figure 14. THD + N vs. Frequency, VSY = 3.3 V 1 0.001 2k FREQUENCY (Hz) 15260-014 0.0001 RL = 16 RL = 32 RL = 600 Figure 12. THD + N vs. Amplitude, VSY = 6 V RL = 16 RL = 32 RL = 600 0.1 0.01 0.001 0.0001 0.00001 0.01 0.1 1 VIN (VRMS) Figure 15. SMPTE vs. Input Voltage (VIN), VSY = 5 V Rev. 0 | Page 9 of 20 15260-015 0.001 THD + N (%) 0.01 15260-011 THD + N (%) 0.01 SSM6322 Data Sheet 100 0.1 0.01 0.001 0.0001 0.00001 0.01 0.1 1 VIN (VRMS) RS = 100k BUFFER AV = 1 10 1 1 1k 10k 100k 1k VSY = 5V, VSD = 5V, AV = 10 5V 3.3V OUTPUT IMPEDANCE () 100 10 10 1 0.1 1 10 100 1k 10k 100k FREQUENCY (Hz) 0.001 10 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 20. Enabled Output Impedance vs. Frequency Figure 17. Input Voltage Noise vs. Frequency, VSY = 5 V 100 100 15260-020 0.01 15260-017 60 VSY = 3.3V, VSD = 3.3V, AV = 10 CH1 CH2 NUMBER OF UNITS 50 10 VSY = 5V, TA = 25C 600 CHANNELS MEAN = 42V STDEV = 45V 40 30 20 1 10 100 1k 10k 100k FREQUENCY (Hz) 0 -250 -230 -210 -190 -170 -150 -130 -110 -90 -70 -50 -30 -10 10 30 50 70 90 110 130 150 170 190 210 230 250 1 15260-018 10 VOS (V) Figure 21. Input Offset Voltage (VOS) Distribution, VSY = 5 V Figure 18. Input Voltage Noise vs. Frequency, VSY = 3.3 V Rev. 0 | Page 10 of 20 15260-021 INPUT VOLTAGE NOISE (nV/Hz) 100 Figure 19. Input Current Noise vs. Frequency CH1 CH2 1 INPUT VOLTAGE NOISE (nV/Hz) 10 FREQUENCY (Hz) Figure 16. CCIF vs. Input Voltage (VIN), VSY = 5 V 100 5V 3.3V 15260-019 INPUT CURRENT NOISE (pA/Hz) RL = 16 RL = 32 RL = 600 15260-016 INTERMODULATION DISTORTION (dB) 1 Data Sheet SSM6322 10 OUTPUT VOLTAGE HIGH TO SUPPLY RAIL (V) 40 30 20 10 VOS (V) 0.01 0.1 1 10 100 1000 ILOAD (mA) 10 VSY = 5V 1 0.1 0.001 0.01 0.1 1 10 100 1000 ILOAD (mA) Figure 23. Output Voltage High (VOH) to Supply Rail vs. Load Current (ILOAD), VSY = 5 V 1 +85C +25C 0C -40C 0.1 0.001 15260-023 +85C +25C 0C -40C VSY = 3.3V 0.01 0.1 1 10 100 1000 ILOAD (mA) 15260-026 OUTPUT VOLTAGE LOW TO SUPPLY RAIL (V) 10 OUTPUT VOLTAGE HIGH TO SUPPLY RAIL (V) +85C +25C 0C -40C Figure 25. Output Voltage High (VOH) to Supply Rail vs. Load Current (ILOAD), VSY = 3.3 V Figure 22. Input Offset Voltage (VOS) Distribution, VSY = 3.3 V Figure 26. Output Voltage Low (VOL) to Supply Rail vs. Load Current (ILOAD) , VSY = 3.3 V 7 10 VSY = 0V TO 6V VSY = 5V 6 +ISY (mA) 5 1 +85C +25C 0C -40C 4 3 ISY ISY ISY ISY 2 = +85C = +25C = 0C = -40C 1 0.1 0.001 0.01 0.1 1 ILOAD (mA) 10 100 1000 15260-024 OUTPUT VOLTAGE LOW TO SUPPLY RAIL (V) 1 0.1 0.001 15260-022 -250 -230 -210 -190 -170 -150 -130 -110 -90 -70 -50 -30 -10 10 30 50 70 90 110 130 150 170 190 210 230 250 0 VSY = 3.3V Figure 24. Output Voltage Low (VOL) to Supply Rail vs. Load Current (ILOAD) VSY = 5 V Rev. 0 | Page 11 of 20 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VSY (V) Figure 27. Positive Supply Current (+ISY) vs. Supply Voltage (VSY) 15260-027 NUMBER OF UNITS 50 VSY = 3.3V, TA = 25C 600 CHANNELS MEAN = 42V STDEV = 45V 15260-025 60 SSM6322 Data Sheet -1.00 0 ISY ISY ISY ISY -1 VSY = 3.3V = +85C = +25C = 0C = -40C -1.25 -1.50 IB (A) -3 -4 -2.00 VSY = 0V TO 6V -5 -2.25 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VSY (V) -2.50 -40 15260-028 -6 -1.75 -15 10 35 60 85 TEMPERATURE (C) 15260-031 -ISY (mA) -2 IB+ IB- Figure 31. Input Bias Current (IB) vs. Temperature, VSY = 3.3 V Figure 28. Supply Current (-ISY) vs. Supply Voltage (VSY) 125 4.00 VSY = 5V AVO = 5V, RL = 600 AVO = 3.3V, RL = 600 3.75 123 RL = 16 RL = 32 RL = 600 VOH (V) AVO (dB) 3.50 121 3.25 119 3.00 117 10 35 60 85 TEMPERATURE (C) 2.50 -40 -15 10 35 60 85 TEMPERATURE (C) Figure 29. Open-Loop Gain (AVO) vs. Temperature 15260-032 -15 15260-029 115 -40 2.75 Figure 32. Output Voltage High (VOH) vs. Temperature, VSY = 5 V -1.00 -2.50 VSY = 5V -2.75 IB+ IB- VOL (V) -3.00 -1.75 -3.25 -2.00 -3.50 -2.25 -3.75 -2.50 -40 -15 10 35 60 85 TEMPERATURE (C) 15260-030 IB (A) -1.50 Figure 30. Input Bias Current (IB) vs. Temperature, VSY = 5 V -4.00 -40 VSY = 5V RL = 16 RL = 32 RL = 600 -15 10 35 60 85 TEMPERATURE (C) Figure 33. Output Voltage Low (VOL) vs. Temperature, VSY = 5 V Rev. 0 | Page 12 of 20 15260-033 -1.25 Data Sheet SSM6322 2.00 6.5 VSY = 3.3V RL = 16 RL = 32 RL = 600 6.3 1.50 6.1 5.9 1.25 5V 3.3V 5.7 -15 10 35 60 85 TEMPERATURE (C) 5.5 -40 15260-034 1.00 -40 -15 10 35 60 85 TEMPERATURE (C) Figure 34. Output Voltage High (VOH) vs. Temperature, VSY = 3.3 V 15260-036 +ISY (mA) VOH (V) 1.75 Figure 36. Supply Current (+ISY) vs. Temperature -1.00 -5.3 VSY = 3.3V RL = 16 RL = 32 RL = 600 -1.50 -5.5 -5.6 -1.75 -5.7 -2.00 -40 -15 10 35 60 85 TEMPERATURE (C) Figure 35. Output Voltage Low (VOL) vs. Temperature, VSY = 3.3 V -5.8 -40 5V 3.3V -15 10 35 60 TEMPERATURE (C) Figure 37. Supply Current (-ISY) vs. Temperature Rev. 0 | Page 13 of 20 85 15260-037 -ISY (mA) -5.4 15260-035 VOL (V) -1.25 SSM6322 Data Sheet TEST CIRCUIT 9 REF2 SD2 4 RG RIN1 5 RIN2 6 15 GND2 SSM6322 VP2 INPUT VN2 VOUT2 OUTPUT 13 RL VNFB2 RF 14 11 12 GAIN2 FILT2 7 8 499 Figure 38. Test Circuit Rev. 0 | Page 14 of 20 GND3 10 15260-138 VEE2 VCC2 Data Sheet SSM6322 THEORY OF OPERATION The SSM6322 is designed using Analog Devices, Inc., proprietary extra fast complementary bipolar (XFCB) process. The device features exceptionally low 1/f noise, low power, and load drive capability. The device combines a classic difference amplifier configuration with a common-mode loop that maintains a fixed common-mode input level, regardless of the differential or common-mode currents going into the device. This combination results in the DAC operating in optimal conditions to reach the THD specifications. This configuration of a common-mode loop and a difference amplifier also has much lower noise and power consumption than other solutions by eliminating two additional amplifiers from the signal path. The output driver has many features including heavy load drive, multiplexing, and pop click suppression. In both shutdown conditions, the output is high impedance in the audio band when the applied external signal is between the supply rails. An additional shutdown pin is included to power up the input difference amplifier so that it can settle before any unwanted signals are applied to the driver. The output driver is capable of delivering -120 dB THD with a 100 mA peak output current and a 2 V rms signal. REF1 and REF2 Pin Voltage REF1 and REF2 set the input common-mode signal. Internally, there is a 15 A current source; by externally adding a resistor, 15 A of current flows through the resistor to generate a common-mode voltage. For example, a 51 k resistor and 15 A current results in a common-mode voltage of 0.765 V. Shutdown Control The SSM6322 features two shutdown pins to control different sections of the device. When SD and SD2 are Logic 1, the entire device is enabled. When SD is Logic 0 and SD2 is Logic 1, the input stage is enabled, and the output buffer is disabled. When SD2 is Logic 0, the entire device is disabled with a quiescent current of only 15 A (see Table 6). Table 6. Disabled Mode and Enabled Mode Logic Level of the Shutdown Pins SD and SD2 = 1 SD = 0 and SD2 = 1 SD2 = 0 Rev. 0 | Page 15 of 20 Device Status Entire device is enabled. Input stage is enabled, and the output buffer is disabled. Entire device is disabled with a quiescent current of 15 A. SSM6322 Data Sheet APPLICATIONS INFORMATION HEADPHONE DRIVERS IN MOBILE PHONES In a headphone driver application, some high performance audio DACs can be configured as a voltage output or a current output. Typically, the current output configuration results in the best THD + N performance. For a current output configuration, implement an current to voltage (I to V) circuit to convert the differential current signal from the R channel and the L channel to the differential voltage signal, followed by a difference amplifier circuit (see Figure 41). For a voltage output configuration, the conditioning circuit is a difference amplifier circuit, which converts the differential signal from the R channel or L channel to a single-ended signal (see Figure 39). Current output audio DACs are typically used to achieve the best THD + N performance (see Figure 41). Six amplifiers and many passive components are required to perform current mode signal conditioning, which consumes more PCB area and more power. Area consumption and power consumption are important considerations in mobile phone applications. DIFFERENTIAL TO SINGLE-END V+ R The SSM6322 contains an additional buffer to support high current drive capabilities. The buffer is also capable of being configured in true high-Z mode in the audio band, which is desirable in some portable applications for the multiplexing of other signals on the same output port. COMMON-MODE CONTROL CIRCUIT The differential output stage of the DAC can be modeled as two voltage sources, which both have the same amplitude and a 180 phase difference. RS1 and RS2 are the source resistors of the voltage source (see Figure 40). In a typical current output DAC signal chain (see Figure 41), four amplifiers are configured as an I to V circuit. The noninverting inputs are connected to a dc voltage that is the output common-mode level of the DAC, making the voltage at the I+/I- terminals a dc signal. This signal makes the voltage drop at two internal source resistors of the DAC (RS1 and RS2) the same, which makes the DAC achieve the best distortion performance. In the SSM6322, the input difference amplifier performs the I to V conversion. V- DAC V+ L RS1 15260-039 V- RG AUDIO DAC REF2 4 GND2 5 RS2 Figure 39. Voltage Output DAC Configuration 9 6 RF VP2 INPUT VN2 SSM6322 VEE2 VCC2 11 12 GAIN2 7 15260-100 VOLTAGE OUTPUT The SSM6322 is an integrated solution for mobile phone applications requiring low distortion and noise performance while directly driving a low impedance load. The device also saves more PCB area and power than the current discrete solution. Figure 40. Common-Mode Circuit Without Common-Mode Control CURRENT OUTPUT I TO V DIFFERENTIAL TO SINGLE-END I+ R I- DAC I+ L 15260-038 I- Figure 41. Current Output DAC Configuration Rev. 0 | Page 16 of 20 Data Sheet SSM6322 REF2 9 5 RS2 AUDIO DAC VOUT RSERIES 10 6 CL Figure 43. Schematic for Driving Capacitive Loads 10 0 -10 -20 -30 -40 CL2 = 330pF CL2 = 470pF CL2 = 1nF CL2 = 2.2nF VSY = 5V VSD = 5V AV = 1 RL = 600 INPUT VN2 -50 1k SSM6322 VEE2 VCC2 11 600 20 VP2 RF VLOAD 12 10k 100k 1M 10M 100M FREQUENCY (Hz) GAIN2 7 15260-042 RG 499 4 GND2 15260-101 RS1 Figure 43 shows the schematic of the output stage for driving capacitive loads. Figure 44 and Figure 45 show the frequency response for a gain of 1 at the 5 V and 3.3 V power supply voltages, respectively. The peaking is high with a small capacitive load. With a 2.2 nF capacitive load (CL), the frequency response is flat and without peaking. 15260-041 After a common-mode control circuit (indicated by the dashed outline shown in Figure 42) is included, the signal at the input terminals (VP2 and VN2) is a dc signal set by the voltage at the REF2 pin (typically this voltage is the same as the dc commonmode voltage of the DAC). The voltage drop at RS1 and RS2 in the DAC is the same. Additionally, the high dc CMRR performance of the amplifier renders the CMRR error negligible. Both the DAC and the amplifier have the best performance in this configuration. The SSM6322 implements the circuit shown in Figure 42. CAPACITIVE LOAD DRIVE CLOSED-LOOP GAIN (dB) Assuming there is no common-mode control (see Figure 40), the signals at the input terminals (VP2/VN2) are ac signals that have the same amplitude and phase. In addition, the internal voltage source of the DAC is differential, which makes the voltage drop at RS1 and RS2 different values. This difference degrades the performance of the DAC. Simultaneously, from the amplifier, the ac common-mode signal at two input terminals (VP2 and VN2) generates additional error signal at the output by its limited ac common-mode rejection ratio (CMRR) performance. Figure 44. Frequency Response for Driving Capacitive Loads, VSY = 5 V 20 Figure 42. Common-Mode Circuit with Common-Mode Control 0 -10 -20 -30 -40 -50 1k CL2 = 330pF CL2 = 470pF CL2 = 1nF CL2 = 2.2nF VSY = 3.3V VSD = 3.3V AV = 1 RL = 600 10k 100k 1M FREQUENCY (Hz) 10M 100M 15260-043 CLOSED-LOOP GAIN (dB) 10 Figure 45. Frequency Response for Driving Capacitive Loads, VSY = 3.3 V Rev. 0 | Page 17 of 20 SSM6322 Data Sheet 25 ppm/C temperature coefficient. The 1 nF capacitors must be NP0 capacitors. There are no specific requirements for the 51 k resistor and the 1 F capacitor at REF1 and REF2. SSM6322 IN A HEADPHONE DRIVER APPLICATION SSM6322 Circuit with Current Output DAC For an audio DAC with a differential current output, two gain resistors convert the current to voltage (see Figure 46). The resistor value is determined by the DAC output full-scale current and the input stage output range (the output range is 3 V at a 5 V supply). Assuming that the DAC single-ended output current is 1.5 mA, and that the differential current is 3 mA, the output of the input stage is 3 V when using two 1 k gain resistors. The feedback capacitors, in parallel with the gain resistors, form a single-pole, low-pass filter. The SSM6322 can handle up to a 1 k and 2.2 nF resistor capacitor combination. SSM6322 Circuit with Voltage Output DAC For audio DACs that output a differential voltage, four gain resistors convert the differential voltage to single-ended voltage (see Figure 47). The feedback capacitors must be in parallel with the gain resistors to form the single-pole, low-pass filter. As shown in Figure 47, four 1 k resistors and two 1 nF capacitors are used to achieve a gain of 1 and a first-order, 159 kHz cutoff frequency low-pass filter. For REF1 and REF2, refer to the DAC data sheet for the common-mode voltage; then, calculate the resistor value at REF1 and REF2. As shown in Figure 47, a 51 k resistor is suggested to obtain a 0.765 V voltage. Typically, audio DACs generate a dc offset current, which is converted to an input common-mode voltage at the input of the SSM6322. The REF1 and REF2 pins of the SSM6322 set the input common-mode voltage of each channel. The voltage at the REF1 and REF2 pins is achieved by an internal 15 A current source and an external resistor; a 51 k resistor is suggested to achieve a 0.765 V voltage. A 1 F capacitor can be used in parallel with the resistor to remove noise. A 499 resistor and 1 nF capacitor can be added between the input stage and output stage for a second single-pole, low-pass filter, as shown in Figure 47. For better gain matching and better distortion performance, all 1 k and 499 k resistors must be of a 0.1% tolerance and 25ppm/C temperature coefficent; the 1 nF capacitor must be NP0 capacitor. A 499 resistor and 1 nF capacitor can be added between the input stage and output stage for a second single-pole, low-pass filter, as shown in Figure 46. There are no specific requirement for the 51 k resistor and 1 F capacitor at REF1 and REF2. For better gain matching and better distortion performance, all 1 k and 499 resistors must to be of 0.1% tolerance and a VCM 9 51k REF2 SD2 SSM6322 1k 1nF AUDIO DAC 1k 1nF 4 GND2 5 VP2 6 VOUT2 INPUT VN2 15 13 OUTPUT VNFB2 14 VEE2 VCC2 GAIN2 11 12 FILT2 7 499 GND3 8 10 15260-044 1F 1nF Figure 46. SSM6322 Circuit with Current Output DAC VCM 1k AUDIO DAC 9 51k 1k SD2 SSM6322 1nF 1k 1k REF2 1nF 4 GND2 5 VP2 VOUT2 INPUT VN2 6 15 OUTPUT 13 VNFB2 14 VEE2 VCC2 GAIN2 11 12 7 FILT2 499 GND3 8 10 1nF Figure 47. SSM6322 Circuit with Voltage Output DAC Rev. 0 | Page 18 of 20 15260-045 1F Data Sheet SSM6322 DESIGN GUIDELINES The performance of the SSM6322 is such that any minor external interference can destroy the circuit. When using this device, consider the following: The sensing ground of the input stage is sensitive to external interference. In the PCB layout, it is recommended to refer the sensing ground to the output interface ground (in high fidelity headphone driver applications, the output interface is the jack). As shown in Figure 48, the dashed outline enclosed ground is the input stage sensing ground, which must be routed directly to the ground of the jack. Note that Figure 48 only shows one channel; for the other channel, route the sensing ground to the jack ground separately. The SSM6322 circuit is different with a typical current output DAC signal chain (see Figure 41); there is only one op amp that performs the differential I to V conversion. The power across the noninverting grounded resistor is fixed, but the power across the feedback resistor varies with the output signal. This variability creates a mismatch between the two resistors, as well as distortion if the heat cannot be well dissipated. Low drift (25 ppm/C) metal film or thin film resistors are suggested to avoid this situation (see Figure 46). VCM 1F 9 51k REF2 SD2 SSM6322 1k 1nF 5 AUDIO DAC 1k 1nF 15 4 GND2 6 VP2 INPUT VN2 OUTPUT VOUT2 VNFB2 VEE2 VCC2 GAIN2 11 12 7 FILT2 499 14 GND3 8 10 1nF Figure 48. Sensing Ground of Input Stage Rev. 0 | Page 19 of 20 13 15260-046 If there is a resistor between the final output and the headphone, the resistor must be low drift (25 ppm/C) and metal film or thin film to avoid distortion when driving heavy loads. Use a low dropout regulator (LDO) as the power supply. Place the decoupling capacitors (0.1 F and 4.7 F) near the amplifier power pins. If there is switching power on the board, keep the switching power circuit and return path far away from the SSM6322 circuit. For better heat dissipation, solder the exposed pad of the LFCSP package to the board pad and, using vias, connect the exposed pad to a large, solid copper plane at the opposite side of the board. The copper plane can be connected to the negative supply plane or ground plane. Shielding is important in mobile phone applications. To reach <-100 dB THD + N specifications, even small interferences can degrade THD + N performance, particularly when listening to music and browsing the internet simultaneously. Metal shielding helps prevent performance degradation. The maximum input filter capacitor values are 2.2 nF. SSM6322 Data Sheet OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 4.10 4.00 SQ 3.90 1 0.50 BSC 2.70 2.60 SQ 2.50 EXPOSED PAD 13 TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 6 12 7 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF PKG-004273/5069 SEATING PLANE PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 24 19 18 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8 03-02-2017-A PIN 1 INDICATOR 0.30 0.25 0.18 Figure 49. 24-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm x 4 mm Body and 0.75 mm Package Height (CP-24-15) Dimensions shown in millimeters ORDERING GUIDE Model1 SSM6322ACPZ-R2 SSM6322ACPZ-R7 SSM6322ACPZ-RL SSM6322CP-EBZ 1 Temperature Package -40C to +85C -40C to +85C -40C to +85C Package Description 24-Lead Lead Frame Chip Scale Package [LFCSP] 24-Lead Lead Frame Chip Scale Package [LFCSP] 24-Lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board Z = RoHS Compliant Part. (c)2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D15260-0-3/17(0) Rev. 0 | Page 20 of 20 Package Option CP-24-15 CP-24-15 CP-24-15 Branding 6322A 6322A 6322A