Spartan-II: DC and Switching Characteristics - Xilinx, Inc.

DS001-3 (v2.4) August 28, 2001 www.xilinx.com Module 3 of 4

Preliminary Product Specification 1-800-255-7778 1

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

Definition of Term s

In this document, some specifications may be designated as Advance or Preliminary. These terms are defined as foll ows:

Advance: Initial estima tes based on s imulati on and/or extrapolation from other speed grades, devices, or families. Val ues

are subject to change. U se as estimates, n ot for production.

Preliminary: Based on preliminary characterization. Further changes are not expected.

Unmarked: Specif ications not identified as either Advance or Prel iminar y are to be considered Final.

Except for pin-to-pin input and output parameters, the AC parameter delay specifications included in this document are

derived from measuring internal test patterns. All limits are representative of worst-case supply voltage and junction

temperature conditions. Typical numbers are based on measurements taken at a nominal VCCINT lev el of 2.5V and a junction

temperature of 25°C. The parameters included are common to popular designs and typical applications. All specifications

are subject to change without noti ce.

DC Specifications

Ab solu te Maxim u m Rati ng s(1)

0Spartan-II 2.5V FPGA Family:

DC and Switc hing Characteristics

DS001-3 (v2.4) August 28, 2001 00Preliminary Product Speci fication

Symbol Description Min Max Units

VCCINT Supply voltage relativ e to GND(2) –0.5 3.0 V

VCCO Supply voltage relative to GND(2) –0.5 4.0 V

VREF Input reference voltage –0.5 3.6 V

VIN Input voltage relative to GND(3) 5V tolerant I/O(4) –0.5 5.5 V

No 5V tolera n ce(5) –0.5 VCCO+0.5 V

VTS Voltage applied to 3-state output 5V tolerant I/O(4) –0.5 5.5 V

No 5V tolera n ce(5) –0.5 VCCO +0.5 V

TSTG Storage temperature (ambient) –65 +150 °C

TJJunction temperature - +125 °C

Notes:

1. Stresses beyond those listed under Absolute Maximum Ratings ma y cause permanent dam age to the device. These are stress

ratings onl y, and fu nctional operat ion of the d evice at these or any other c onditions be yon d those li sted under Oper ating Conditions

is not imp lied. Exposure to Absol ute Maximum Ratings condition s for ext ended periods of tim e may affect device reliability.

2. Power supplies may turn on in any order.

3. VIN should not exceed VCCO by more t han 3.6V over extended per iods of tim e (e.g., longer than a day).

4. Spartan-II I/Os are 5V Toler ant whenever the LVTTL, LVCMOS2, or PCI33_5 signal standard has been selec ted. With 5V Toler ant

I/Os se lected , the Maxi mum DC overshoot must be limite d to e ither +5.5 V or 10 mA, and unders hoot m ust be l imite d to either –0.5V

or 10 mA , whi chev er is easier to achieve. The Maxi m um AC condi tions are as follows: The device pins may undershoot to –2.0V or

overshoot to +7. 0V, provided this over/undersh oot lasts no more t han 11 ns wit h a forcing cur rent no great er than 100 mA.

5. Without 5V Tolerant I/Os sel ected, th e Maxi mum DC ove rshoot must be limite d to eit her VCCO + 0. 5V or 10 mA, and under shoot m ust

be limi ted to –0.5V or 10 mA, whicheve r is ea sier to achi eve . The Maximum AC conditi ons are as follows: The de vice pins may

undershoot to –2.0V or overs hoot to VCCO + 2.0V, provided this o ver/undershoot lasts no more than 11 ns with a forcing current no

greater than 100 mA.

6. For solderi ng guidelines , see the Packaging Information on the Xilin x website: www.xilinx.com/partinfo/pkgs.htm

Spartan -II 2.5V FPGA Family: DC a nd Switching Characteristics

Modu le 3 of 4 www.xilinx.com DS001-3 (v 2.4) August 28, 2001

2 1-800-255-7778 Preliminary Product Spec ification

Recommended Operating Conditions

DC Characteristics Over Operating Conditions

Symbol Description Min Max Units

TJJunct ion temperature(1) Commercial 0 85 °C

Industrial –40 100 °C

VCCINT Supply voltage relative to GND(2,5) Com mercial 2.5 – 5% 2.5 + 5% V

Industr ial 2.5 – 5% 2.5 + 5% V

VCCO Supply vol tage relativ e to GND(3,5) Commercial 1.4 3.6 V

Industrial 1.4 3.6 V

TIN Input signal transition time(4) - 250 ns

Notes:

1. At junct ion temperatures above those listed as Ope rating Condi tions, all delay parameters increase by 0.35% per °C.

2. Functi onal operati on is gua ranteed down to a minimum VCCINT of 2.25V (Nomi nal VCCINT – 10%). For ev ery 50 mV reduction in

VCCINT below 2.375V (nominal VCCINT – 5%), all delay param eters increase by 3% .

3. Mi nimum and maximum values for VCCO vary according to the I/O st andard selected.

4. Input and output measurement threshold is ~50% of VCCO.

5. Supply voltages ma y be applied in any or der desired.

Symbol Description Min Typ Max Units

VDRINT Data Retention VCCINT voltage (below which configuration data

may be lost) 2.0 - - V

VDRIO Data Retention VCCO voltage (below which configuration data may

be lost) 1.2 - - V

ICCINTQ Qui esce nt VCCINT s uppl y current(1) XC2S15 Commercial - 10 30 mA

Industrial - 10 60 mA

XC2S30 Commercial - 10 30 mA

Industrial - 10 60 mA

XC2S50 Commercial - 12 50 mA

Industrial - 12 100 mA

XC2S100 Commercial - 12 50 mA

Industrial - 12 100 mA

XC2S150 Commercial - 15 50 mA

Industrial - 15 100 mA

XC2S200 Commercial - 15 75 mA

Industrial - 15 150 mA

ICCOQ Quies cent VCCO supply current(1) --2mA

IREF VREF current per VREF pin - - 2 0 µA

ILInput or output leakage current –10 - +10 µA

CIN Input capacitance (sample tested) VQ, CS, TQ, PQ, FG

packages --8pF

IRPU Pad pull-up (when selected) @ VIN = 0V, VCCO = 3.3V

(sample tested)(2) - - 0.25 mA

IRPD Pad pull-down (when selected) @ VIN = 3.6V (sample tested)(2) - - 0.15 mA

Notes:

1. With no output curr ent l oads, no activ e input pull -up resistors , all I/O pins 3-st ated and floating.

2. Internal pul l-up and pull -do wn resi stors guarant ee v ali d logi c le v els at unconnect ed input pi ns. The se pull -up and pul l-do wn resistors

do not provide valid logic levels when input pins are connected to ot her ci rcuits.

Spartan -II 2.5V FPGA Family: DC a nd Switching Characteristics

DS001-3 (v2.4) August 28, 2001 www.xilinx.com Module 3 of 4

Preliminary Product Specification 1-800-255-7778 3

Supply Current Requirements During Power-On

Spartan-II FPGAs require that a minimum supply current

ICCPO be provided to the VCCINT lines for a successful

power-on. If more current is available, the FPGA can con-

sume more than ICCPO min., though this cannot adversely

affe c t r e l iabil ity.

A maximum limit for ICCPO is not specified. Be careful when

using foldback/crowbar s upplies and fuses. It is possible to

control the magnitude of ICCPO by limiting the supply current

av ailable to the FPGA. A current limit below the trip lev el will

avoid inadvertently activating over-current protection cir-

cuits.

DC Input and Output Levels

Values for VIL and VIH are recommended input voltages.

Values for VOL and VOH are guaranteed output voltages

over t he recom mended ope rating conditi ons. Only sele cted

standards are tested. These are chosen to ensure that all

standards meet their specifications. The selected standards

are tested at minimum VCCO with the respective IOL and IOH

currents shown. Other standards are sample tested.

Symbol Description Min(1) Max Units

ICCPO Total VCCINT supply current required

dur ing power-on 0°C ≤ TJ ≤ 100°C(2) 500 - mA

–40°C ≤ TJ < 0°C2 -A

TCCPO VCCINT ramp time(3,4) -50ms

Notes:

1. The ICCPO requirement applies for a brief time (commonly only a few m illiseconds) when VCCINT ramps from 0 to 2.5V.

2. Appli es to both Commerc ial and Industria l devices.

3. The ramp ti m e is measured from GND to VCCINT max on a fully loaded board.

4. VCCINT mus t not dip i n the negative direction during power on.

Input/Output

Standard VIL VIH VOL VOH IOL IOH

V, Min V, Max V, Min V, Max V, Max V, Min mA mA

LVTTL(1) –0.5 0.8 2.0 5.5 0.4 2.4 24 –24

LVCMOS2 –0.5 0.7 1.7 5.5 0.4 1.9 12 –12

PCI, 3.3V –0.5 44% VCCINT 60% VCCINT VCCO + 0.5 10% VCCO 90% V CCO Not e (2) Note (2)

PCI, 5.0V –0.5 0.8 2.0 5 .5 0.55 2.4 Note (2) Note (2)

GTL –0.5 VREF – 0.05 VREF + 0.05 3.6 0.4 N/A 40 N/A

GTL+ –0.5 VREF – 0.1 VREF + 0.1 3.6 0.6 N/A 36 N/A

HSTL I –0.5 VREF – 0.1 VREF + 0.1 3.6 0.4 VCCO – 0.4 8 –8

HSTL III –0.5 VREF – 0.1 VREF + 0.1 3.6 0.4 VCCO – 0.4 24 –8

HSTL IV –0.5 VREF – 0.1 VREF + 0.1 3.6 0.4 VCCO – 0.4 48 –8

SSTL3 I –0.5 VREF – 0.2 VREF + 0.2 3.6 VREF – 0.6 VREF + 0.6 8 –8

SSTL3 II –0.5 VREF – 0.2 VREF + 0.2 3.6 VREF – 0.8 VREF + 0.8 16 –16

SSTL2 I –0.5 VREF – 0.2 VREF + 0.2 3.6 VREF – 0.6 VREF + 0.6 7 .6 –7.6

SSTL2 II –0.5 VREF – 0.2 VREF + 0.2 3.6 VREF – 0.8 VREF + 0.8 15.2 –15.2

CTT –0.5 VREF – 0.2 VREF + 0.2 3.6 VREF – 0.4 VREF + 0.4 8 –8

AGP –0.5 VREF – 0.2 VREF + 0.2 3.6 10% VCCO 90% VCCO Note (2) Note (2)

Notes:

1. VOL and VOH fo r lo wer drive currents ar e sample tested.

2. Tested according to the relevant specifications.

Spartan -II 2.5V FPGA Family: DC a nd Switching Characteristics
Modu le 3 of 4 www.xilinx.com DS001-3 (v 2.4) August 28, 2001
4 1-800-255-7778 Preliminary Product Spec ification
R
Switching Characteristics
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
der ived from m easuring i nter n al tes t  patter ns. Listed bel ow
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment S y stem) and back-ann otated  to  th e simu lation n etlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all Spartan-II devices unless otherwise noted.
Global Clock Input to Output Delay for LVTTL, with DLL (Pin-to-Pin)(1)  
Global Clock Input to Output Delay for LVTTL, without DLL (Pin-to-Pin)(1)  
Symbol Description Device
Spee d Grad e
Units
All -6 -5
Min Max Max
TICKOFDLL Glob al clock in put to output delay 
using output flip-flop for LVT TL, 
12 mA, fast sl ew rate, with DLL. 
All 2.9 3.3 ns
Notes: 
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and 
where all accessible IOB and CLB flip-fl ops are clocked b y the global clock net.
2. Output timing is me asured at 1.4V wi th 35 pF external capacitive load f or LVTTL. The 35 pF load does not apply to the Min v alues. 
For other I/O st andards and di ffer ent loads, see the tables Constants for  Calcul ating TIOOP and D e lay M eas urement 
Methodology, page 10.
3. DLL output jitter  is al ready includ ed in the timin g calc ulation.
4. For data output wit h different st andards, adju st delays with the values sho wn in IOB Output Delay Adjust men ts f or Differ ent 
Standards, page 9. For a global clock input with  standards other than LVTTL, adjust delays with values from the I/O Standard 
Global Clock Input Adjustments, page 11.
Symbol Description Device
Speed Grade
Units
All -6 -5
Min Max Max
TICKOF Global clock in put to output delay 
using output flip-flop for LVT TL, 
12 mA, fast slew rate, without DLL. 
XC2S15 4.5 5.4 ns
XC2S30 4.5 5.4 ns
XC2S50 4.5 5.4 ns
XC2S100 4.6 5.5 ns
XC2S150 4.6 5.5 ns
XC2S200 4.7 5.6 ns
Notes: 
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and 
where all accessible IOB and CLB flip-fl ops are clocked b y the global clock net.
2. Output timing is meas ured at 1.4V with 35 pF exte rnal capa citiv e load for LVTTL. The 35 pF load does not apply to the  Min values. 
For other I/O st andards and di ffer ent loads, see the tables Constants for  Calcul ating TIOOP and D e lay M eas urement 
Methodology, page 10.
3. For data output wit h different st andards, adju st delays with the values sho wn in IOB Output Delay Adjust men ts f or Differ ent 
Standards, page 9. For a global clock input with  standards other than LVTTL, adjust delays with values from the I/O Standard 
Global Clock Input Adjustments, page 11.

Spartan -II 2.5V FPGA Family: DC a nd Switching Characteristics
DS001-3 (v2.4) August 28, 2001 www.xilinx.com Module 3 of 4
Preliminary Product Specification 1-800-255-7778 5
R
Global Clock Setup and Hold for LVTTL Standard, with DLL (Pin-to-Pin)  
Global Clock Setup and Hold for LVTTL Standard, without DLL (Pin-to-Pin)  
Symbol Description Device
Speed Grade
Units
-6 -5
Min Min
TPSDLL / TPHDLL Input setup and hold time relative 
to global clock input signal for 
LVTTL standa rd , no delay, IFF,(1) 
wit h DLL
Al l 1. 7  / 0 1.9 /  0 n s
Notes: 
1. IFF = Input Flip-Flop or Latch
2. Setup tim e is measured  rel ati ve to the Global Clock input  signal with the fastest route  and the l ightest l oad. Hold time is measur ed 
relat ive to the Global Clock in put signal with the slowe st route and heaviest load.
3. DLL output jitter  is al ready includ ed in the timin g calc ulation.
4. A zero hold time listing indicates no  hold t ime or a negative hold tim e. 
5. For data input wi th differ ent standards, adjust the setup time delay by the values shown in IOB Input Delay Adj ustments for 
Different Standar ds, page 7. For  a global clock input with standards other th an LVTTL, adjust dela ys wit h values from the I/O 
Standard Global Clock Input Adjustm ents, page 11.
Symbol Description Device
Speed Grade
Units
-6 -5
Min Min
TPSFD / TPHFD Input setup and hold time relative 
to global clock input signal for 
LVTTL standa rd , no delay, IFF,(1) 
wit hout DLL
XC2S 15 2.2 / 0 2.7 / 0 ns
XC2S 30 2.2 / 0 2.7 / 0 ns
XC2S 50 2.2 / 0 2.7 / 0 ns
XC2 S10 0 2.3  / 0 2.8 / 0 n s
XC2 S15 0 2.4  / 0 2.9 / 0 n s
XC2 S20 0 2.4  / 0 3.0 / 0 n s
Notes: 
1. IFF = Input Flip-Flop or Latch
2. Setup tim e is measured  rel ati ve to the Global Clock input  signal with the fastest route  and the l ightest l oad. Hold time is measur ed 
relat ive to the Global Clock in put signal with the slowe st route and heaviest load.
3. A zero hold time listing indicates no  hold t ime or a negative hold tim e. 
4. For data input wi th differ ent standards, adjust the setup time delay by the values shown in IOB Input Delay Adj ustments for 
Different Standar ds, page 7. For  a global clock input with standards other th an LVTTL, adjust dela ys wit h values from the I/O 
Standard Global Clock Input Adjustm ents, page 11.

Spartan -II 2.5V FPGA Family: DC a nd Switching Characteristics

Modu le 3 of 4 www.xilinx.com DS001-3 (v 2.4) August 28, 2001

6 1-800-255-7778 Preliminary Product Spec ification

IOB Input Switching Characteristics(1)

Input delays assoc iated with the pad are specified for LVTTL levels. For other standa rd s, adjust the delays with the values

shown in IOB Input Delay Adjus tments for Different Stan dards, page 7.

Symbol Description Device

Spee d Grad e

Units

-6 -5

Min Max Min Max

Propagation De lays

TIOPI Pad to I output, no delay All - 0.8 - 1.0 ns

TIOPID Pad to I output, with delay All - 1.5 - 1.8 ns

TIOPLI Pad to output IQ via transparent latch,

no delay All - 1.7 - 2.0 ns

TIOPLID Pad to output IQ via transparent latch,

with delay XC2S15 - 3.8 - 4.5 ns

XC2S30 - 3.8 - 4.5 ns

XC2S50 - 3.8 - 4.5 ns

XC2S100 - 3.8 - 4.5 ns

XC2S150 - 4.0 - 4.7 ns

XC2S200 - 4.0 - 4.7 ns

Sequential Delays

TIOCKIQ Clo ck CLK to output IQ All - 0.7 - 0.8 ns

Setup/Hold Times with Respect to Clock CLK(2)

TIOPICK / TIOICKP Pad, no delay All 1.7 / 0 - 1.9 / 0 - ns

TIOPICKD / TIOICKPD Pad , with delay(1) XC2S15 3.8 / 0 - 4.4 / 0 - ns

XC2S30 3.8 / 0 - 4.4 / 0 - ns

XC2S50 3.8 / 0 - 4.4 / 0 - ns

XC 2S 1 00 3.8 / 0 - 4.4 / 0 - ns

XC 2S 1 50 3.9 / 0 - 4.6 / 0 - ns

XC 2S 2 00 3.9 / 0 - 4.6 / 0 - ns

TIOICECK / TIOCKICE ICE input All 0.9 / 0. 0 1 - 0.9 / 0.01 - ns

Set/Reset Delays

TIOSRCKI SR input (IFF, synchronous ) All - 1.1 - 1.2 ns

TIOSRIQ SR input to IQ (asynchronou s) All - 1.5 - 1.7 ns

TGSRQ GSR to output IQ All - 9 .9 - 11.7 ns

Notes:

1. Input timing for LVTTL is measured at 1.4V. For other I/O standards, see t he table Delay Measurement Methodology, page 10.

2. A zero hold time listing indicates no hold t ime or a negative hold tim e.

Spartan -II 2.5V FPGA Family: DC a nd Switching Characteristics

DS001-3 (v2.4) August 28, 2001 www.xilinx.com Module 3 of 4

Preliminary Product Specification 1-800-255-7778 7

IOB Input Delay Adjustments for Different Standards(1)

Input delay s associated with the pad are specified for LVTTL. For other standards, adjust the delays by the values sho wn. A

delay adjusted in this way constitutes a worst-case limit.

Symbol Description Standard

Speed Grade

Units-6 -5

Data I n put Delay Adjus tments

TILVTTL Sta ndard-spec ific data input delay

adjustments LVTTL 0 0 ns

TILVCMOS2 LVCMOS2 –0.04 –0.05 ns

TIPCI33_3 P CI , 33 MHz, 3.3V –0.11 –0.13 ns

TIPCI33_5 P CI , 33 MHz, 5.0V 0.26 0 .30 ns

TIPCI66_3 P CI , 66 MHz, 3.3V –0.11 –0.13 ns

TIGTL GTL 0.20 0.24 ns

TIGTLP GTL+ 0.11 0.13 ns

TIHSTL HSTL 0.03 0.04 ns

TISSTL2 SSTL2 –0.08 –0.09 ns

TISSTL3 SSTL3 –0.04 –0.05 ns

TICTT CTT 0.02 0.02 ns

TIAGP AGP –0.06 –0.07 ns

Notes:

1. Input timing for LVTTL is measured at 1.4V. For other I/O standards, see t he table Delay Measurement Methodology, page 10.

Spartan -II 2.5V FPGA Family: DC a nd Switching Characteristics

Modu le 3 of 4 www.xilinx.com DS001-3 (v 2.4) August 28, 2001

8 1-800-255-7778 Preliminary Product Spec ification

IOB Output Switch ing Characteristics

Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate . For other standards, adjust

the delays with the values shown in IOB Output Delay Adjustments for Different Standards, page 9.

Symbol Description

Spee d Grad e

Units

-6 -5

Min Max Min Max

Propagation Delays

TIOOP O input to pad - 2.9 - 3.4 ns

TIOOLP O input to pad via transparent latch - 3.4 - 4.0 ns

3-state Delays

TIOTHZ T input to pad high-impedance(1) - 2.0 - 2.3 ns

TIOTON T input to valid data on pad - 3.0 - 3.6 ns

TIOTLPHZ T input to pad high impedan ce via transparent latch(1) - 2.5 - 2.9 ns

TIOTLPON T input to valid data on pad via transparent latch - 3.5 - 4.2 ns

TGTS GTS to pad high impedanc e(1) - 5.0 - 5.9 ns

Sequential Delays

TIOCKP Cl ock CLK to pad - 2.9 - 3.4 ns

TIOCKHZ Cl ock CLK to pad hig h impedance (synchronous)(1) - 2.3 - 2.7 ns

TIOCKON Cl ock CLK to valid data on pad (synchronous) - 3.3 - 4.0 ns

Setup/Hold Times wi th Respec t to Clock CL K(2)

TIOOCK / TIOCKO O input 1.1 / 0 - 1.3 / 0 - ns

TIOOCECK /

TIOCKOCE

OC E input 0.9 / 0.01 - 0.9 / 0.01 - ns

TIOSRCKO /

TIOCKOSR

SR input (OFF ) 1.2 / 0 - 1.3 / 0 - ns

TIOTCK / TIOCKT 3-st ate setup times, T input 0.8 / 0 - 0.9 / 0 - ns

TIOTCECK /

TIOCKTCE

3-state setup times, TCE input 1.0 / 0 - 1.0 / 0 - ns

TIOSRCKT /

TIOCKTSR

3-state setup times, SR input (TFF) 1.1 / 0 - 1.2 / 0 - ns

Set/Reset Delays

TIOSRP S R input to pad (asynchronous ) - 3.7 - 4.4 ns

TIOSRHZ S R input to pad high imped ance (asynchrono us )(1) - 3.1 - 3.7 ns

TIOSRON SR input to valid data on pad (asynchronous) - 4.1 - 4.9 ns

TIOGSRQ GSR to pad - 9.9 - 11.7 ns

Notes:

1. Three-state turn-off delays should not be adjusted.

2. A zero hold time listing i ndicates no hold time or a negative hold time.

Spartan -II 2.5V FPGA Family: DC a nd Switching Characteristics

DS001-3 (v2.4) August 28, 2001 www.xilinx.com Module 3 of 4

Preliminary Product Specification 1-800-255-7778 9

IOB Output Delay Adjustments for Different Standards(1)

Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate . For other standards, adjust

the delays by the values shown. A delay adjusted in this way constitutes a worst-case limit.

Symbol

Description Standard

Speed Grade

Units-6 -5

Output D e lay Adjustments (Adj)

TOLVTTL_S2 Standard-spe cific adjustment s for

output delays ter m ina ting at pads

(based on standard capacitive

load, CSL)

LVTTL, Slow, 2 mA 14. 2 16.9 ns

TOLVTTL_S4 4 mA 7.2 8.6 ns

TOLVTTL_S6 6 mA 4.7 5.5 ns

TOLVTTL_S8 8 mA 2.9 3.5 ns

TOLVTTL_S12 12 mA 1.9 2.2 ns

TOLVTTL_S16 16 mA 1.7 2.0 ns

TOLVTTL_S24 24 mA 1.3 1.5 ns

TOLVTTL_F2 LVTTL, Fast, 2 mA 12.6 15.0 ns

TOLVTTL_F4 4 m A 5.1 6.1 ns

TOLVTTL_F6 6 m A 3.0 3.6 ns

TOLVTTL_F8 8 m A 1.0 1.2 ns

TOLVTTL_F12 12 mA 0 0 ns

TOLVTTL_F16 16 mA –0.1 –0.1 ns

TOLVTTL_F24 24 mA –0.1 –0.2 ns

TOLVCMOS2 LVCMOS2 0.2 0.2 ns

TOPCI33_3 PCI, 33 MHz, 3.3V 2.4 2.9 ns

TOPCI33_5 PCI, 33 MHz, 5.0V 2.9 3.5 ns

TOPCI66_3 PCI, 66 MHz, 3.3V –0.3 –0.4 ns

TOGTL GTL 0.6 0.7 ns

TOGTLP GTL+ 0.9 1.1 ns

TOHSTL_I HSTL I –0.4 –0.5 ns

TOHSTL_III HSTL III –0.8 –1.0 ns

TOHSTL_IV HSTL IV –0.9 –1.1 ns

TOSSTL2_I SSTL2 I –0.4 –0.5 ns

TOSSLT2_II SSTL2 II –0.8 –1.0 ns

TOSSTL3_I SSTL3 I –0.4 –0.5 ns

TOSSTL3_II SST L3 II –0.9 –1.1 ns

TOCTT CTT –0.5 –0.6 ns

TOAGP AGP –0.8 –1.0 ns

Notes:

1. Output tim ing is measur ed at 1.4V with 35 pF external capaci tiv e load fo r LVTTL. Fo r other I/O standar ds and different loads , see th e

tables Constants for Calcul ating TIOOP and Delay Measurement Methodology, page 10.

Spartan -II 2.5V FPGA Family: DC a nd Switching Characteristics

Modu le 3 of 4 www.xilinx.com DS001-3 (v 2.4) August 28, 2001

10 1-800-255-7778 Preliminary Product Specification

Calculation of TIOOP as a Function of

Capacitance

TIOOP is the prop agation d elay from the O Input of the IOB

to the pad. The value s for T IOOP a re based on the standard

capacitive load (CSL) for each I/O standard as listed in the

table C onsta nts f or Calculat i ng TIOOP, below.

F or other capacitive l oads, use the formulas below to calcu-

late an adjusted propagation delay, TIOOP1.

TIOOP1 = TIOOP + A d j + (C LOAD – CSL) * FL

Where:

Adj is select ed from IOB Output Delay

Adjustments for Different Stand ards,

page 9, according to the I/O standard used

CLOAD is the capacitive load for th e design

FLis the c apacitanc e scaling factor

Delay Measurement Methodology

Standard VL(1) VH(1) Meas.

Point VREF

Typ(2)

LVTTL 0 3 1.4 -

LVCMOS2 0 2.5 1.125 -

PCI33_5 Per PCI Spec -

PCI33_3 Per PCI Spec -

PCI66_3 Per PCI Spec -

GTL VREF – 0.2 VREF + 0. 2 V REF 0.80

GTL+ VREF – 0.2 VREF + 0.2 VREF 1.0

HSTL Class I VREF – 0.5 VREF + 0.5 V REF 0.75

HSTL Class III VREF – 0.5 V REF + 0.5 VREF 0.90

HSTL Class IV VREF – 0.5 VREF + 0. 5 V REF 0.90

SSTL3 I and II VREF – 1.0 V REF + 1.0 VREF 1.5

SSTL2 I and II VREF – 0.75 VREF + 0.75 VREF 1.25

CTT VREF – 0.2 VREF + 0.2 V REF 1.5

AGP VREF –

(0.2xVCCO)VREF +

(0.2xVCCO)VREF Per AGP

Spec

Notes:

1. Input wavefor m swi tches between VL and V H.

2. Meas urements are made at VREF Typ, Maximum, and

Minimum. Worst-case values are reported.

3. I/O param eter mea surements are made with the capacitance

values shown in the previous table, Constants for

Calcul ating TIOOP. See Xilinx application note XAPP179 for

the appropriat e termina ti ons.

4. I/O standard measurements are reflected in the IBIS model

informati on except where th e IBIS format pre cludes it.

Constants for Calcul ating TIOOP

Standard CSL(1)

(pF) FL

(ns/pF)

LVTTL Fast Slew Rate, 2 mA drive 35 0.41

LVTTL Fast Slew Rate, 4 mA drive 35 0.20

LVTTL Fast Slew Rate, 6 mA drive 35 0.13

LVTTL Fast Slew Rate, 8 mA dr ive 35 0.079

LVTTL Fast Slew Rate, 12 mA dr ive 35 0.044

LVTTL Fast Slew Rate, 16 mA dr ive 35 0.043

LVTTL Fast Slew Rate, 24 mA dr ive 35 0.033

LVTTL Slow Slew Rate, 2 mA driv e 35 0.41

LVTTL Slow Slew Rate, 4 mA driv e 35 0.20

LVTTL Slow Slew Rate, 6 mA drive 35 0.100

LVTTL Slow Slew Rate, 8 mA drive 35 0.086

LVTTL Slow Slew Rate, 12 mA drive 35 0.058

LVTTL Slow Slew Rate, 16 mA drive 35 0.050

LVTTL Slow Slew Rate, 24 mA drive 35 0.048

LVCMOS2 35 0.041

PCI 33 MHz 5V 50 0.050

PCI 33 MHZ 3.3V 10 0.050

PCI 66 MHz 3.3V 10 0.033

GTL 0 0.014

GTL+ 0 0.017

HSTL Class I 20 0.022

HSTL Class III 20 0.016

HSTL Class IV 20 0.014

SSTL2 Class I 30 0.028

SSTL2 Class II 30 0.016

SSTL3 Class I 30 0.029

SSTL3 Class II 30 0.016

CTT 20 0.035

AGP 10 0.037

Notes:

1. I/ O par ameter measuremen ts are made with the cap acitance

valu es shown abov e. See Xilinx application note XAPP179

for the appropriat e termin ati ons.

2. I/O standard measurements are reflected in the IBIS model

information except where the IBIS format precludes it.

Spartan -II 2.5V FPGA Family: DC a nd Switching Characteristics

DS001-3 (v2.4) August 28, 2001 www.xilinx.com Module 3 of 4

Preliminary Product Specification 1-800-255-7778 11

Clock Distribution Guidelines(1)

Clock Distribution Switching Characteristics

TGPIO is specified for LVTTL le v e ls. F or other standards, adjust TGPIO with the values shown in I/O Standard Global Clock

Input Adjustments.

I/O Standard Global Clock Input Adjustments

Dela ys associated with a global clock input pad are specified for LVTTL levels. For other standards, adjust the delay s by the

values shown. A delay adjusted in the way constitutes a worst-case limit.

Symbol Description

Speed Grad e

Units

-6 -5

Max Max

GCLK Clock Skew

TGSKEWIOB Glob al clock skew betwe en IOB flip-flops 0.13 0.14 ns

Notes:

1. These cl ock distribution delays are provided for guidance only. They reflect the delay s encountered in a typical design under

worst-case conditi ons. Precise values for a partic ular design are provided by the ti m ing analyzer.

Symbol Description

Speed Grade

Units

-6 -5

Max Max

GCLK IOB and Buffer

TGPIO Global clock pad to output 0.7 0.8 ns

TGIO Global clock buffer I input to O output 0.7 0.8 ns

Symbol Description Standard Speed Grade Units-6 -5

Data I n put Delay Adjus tments

TGPLVTTL Standa rd-spe cific global clock

input dela y adjustments LVTTL 0 0 ns

TGPLVCMOS2 LVCMOS2 –0.04 –0.05 ns

TGPPCI33_3 PC I, 33 M Hz, 3.3V –0.11 –0.13 ns

TGPPCI33_5 PC I, 33 M Hz, 5.0V 0.26 0.30 ns

TGPPCI66_3 PC I, 66 M Hz, 3.3V –0.11 –0.13 ns

TGPGTL GTL 0.800.84ns

TGPGTLP GTL+ 0.71 0.73 ns

TGPHSTL HSTL 0.63 0.64 ns

TGPSSTL2 SSTL2 0.52 0.51 ns

TGPSSTL3 SSTL3 0.56 0.55 ns

TGPCTT CTT 0.620.62ns

TGPAGP AGP 0.540.53ns

Notes:

1. Input timin g for GPLVTTL i s measured at 1.4V. F or other I /O standards, see the table De lay Meas urement Meth odology, pa ge 10.

Spartan -II 2.5V FPGA Family: DC a nd Switching Characteristics

Modu le 3 of 4 www.xilinx.com DS001-3 (v 2.4) August 28, 2001

12 1-800-255-7778 Preliminary Product Specification

DLL Timing Parameters

Switching parameters testing is modeled after testing meth-

ods specified by MIL-M-38510/605; all de vices are 100 per-

cent fun ction ally tested. Be ca use of the diff iculty in directly

measuring many internal timing parameters, those parame-

ters are derived from benchmark timing patterns. The fol-

lowing guidelines reflect worst-case values across the

recomm ended operating conditions.

DLL Clock Tolerance, Jitter, and Phase Information

All DLL output jitter and phase specifications were deter-

mined through statisti cal mea suremen t at the package pins

using a clock mirror configuration and matched drivers.

Figure 1, pag e 1 3, provides definitions fo r various pa rame-

ters in the table below.

Symbol Description

Sp eed Gr ade

Units

-6 -5

Min Max Min Max

FCLKINHF Input clock frequen cy (CLKDLLHF ) 60 200 60 180 MHz

FCLKINLF Input clock frequen cy (CLKDLL) 25 100 25 90 MHz

TDLLPWHF Input clock pulse width (CLKDLL HF) 2.0 - 2.4 - ns

TDLLPWLF Input clock pulse width (CLKDLL) 2 .5 - 3.0 - ns

Symbol Description FCLKIN

CLKDLLHF CLKDLL

UnitsMin Max Min Max

TIPTOL Input clock period tolerance - 1.0 - 1 .0 ns

TIJITCC Input clock jitter tolerance (cycle-to-cycle) - ±150 - ±300 ps

TLOCK Time required for D LL to acquire lock > 60 MHz - 20 - 20 µs

50-60 MHz - - - 25 µs

40-50 MHz - - - 50 µs

30-40 MHz - - - 90 µs

25-30 MHz - - - 120 µs

TOJITCC Output jitter (cycle-to -cycl e ) for an y DLL clock output(1) - ±60 - ±60 ps

TPHIO P has e offset between CLKIN and CLKO(2) - ±100 - ±100 ps

TPHOO Phas e offset between clock outpu ts on the DLL(3) - ±140 - ±140 ps

TPHIOM Maximum phas e difference betwe en CLKIN and CLKO(4) - ±160 - ±160 ps

TPHOOM Maximum phase difference betwe en clock outputs on the DLL(5) - ±200 - ±200 ps

Notes:

1. Output Jitter is cycle-to-cycle ji tt er measured on the DLL o utput clock, excluding input clo ck jitt er.

2. Phase Offset between CLKIN and CLK O is the wor st-case fixed time differ ence between r ising edges of CLKIN and CLKO,

excluding output jitte r and input cloc k jitt er.

3. Phase Offset between Cloc k Outputs on the DLL is the worst-case fixed time dif fe rence between ri sing edges of any two DLL

outputs, excluding Output Jitter and i nput clock jitter.

4. Maxim um Phase Dif ference between CLKIN an CLKO is the sum of Output Jit ter and Phase Off set between CLKIN and CLKO ,

or the gr eatest dif ference between CLKIN and CLKO rising edges due to DLL alo ne (excluding input cloc k jitter).

5. Maxim um Phase Differen ce between Clock Outputs on the DLL is t he sum of Output JI tter and Phase Offset between any DLL

clock outputs, or the greatest difference between any t wo DLL output rising edges due to DLL alone (excluding input clock jitte r).

Spartan -II 2.5V FPGA Family: DC a nd Switching Characteristics

DS001-3 (v2.4) August 28, 2001 www.xilinx.com Module 3 of 4

Preliminary Product Specification 1-800-255-7778 13

F igur e 1: Period Tolerance and Clock Jitter

Period Tolerance:

the allowed input clock period change in nanoseconds.

Output Jitter:

the difference between an ideal

reference clock edge and the actual design.

TCLKIN + TIPTOL

DS001_52_090800

Actual Period

+ Jitter

+/- Jitter

+ Maximum

Phase Difference

Phase Offset and Maximum Phase Difference

+ Phase Offset

Ideal Period

FCLKIN

T =

CLKIN

Spartan -II 2.5V FPGA Family: DC a nd Switching Characteristics

Modu le 3 of 4 www.xilinx.com DS001-3 (v 2.4) August 28, 2001

14 1-800-255-7778 Preliminary Product Specification

CLB Switching Char acte ristics

Delays or iginating at F/G i nputs va ry slightly according to th e input used. T he values listed be low are worst-case. Precise

values are provided by the timing anal yzer.

Sym bol De sc ript ion

Speed Grad e

Units

-6 -5

Min Max Min Max

Combinatorial Delays

TILO 4-input function: F/G inputs to X/Y outputs - 0.6 - 0.7 ns

TIF5 5-input function: F/G inputs to F5 output - 0.7 - 0.9 ns

TIF5X 5-input function: F/G inputs to X output - 0.9 - 1.1 ns

TIF6Y 6-input function: F/G inputs to Y output via F6 MUX - 1.0 - 1.1 ns

TF5INY 6-input function: F5IN input to Y output - 0.4 - 0.4 ns

TIFNCTL Incremental dela y routing through transparent latch

to XQ/YQ ou tp uts - 0.7 - 0.9 ns

TBYYB BY input to YB output - 0.6 - 0.7 ns

Sequential Delays

TCKO FF clock CLK to XQ /YQ outputs - 1.1 - 1.3 ns

TCKLO Latch clock CLK to XQ/YQ outputs - 1.2 - 1.5 ns

Setup/Hold Times with Respect to Clock CL K(1)

TICK / TCKI 4-i nput function: F/G inputs 1.3 / 0 - 1.4 / 0 - ns

TIF5CK / TCKIF5 5-input function: F/G inputs 1.6 / 0 - 1.8 / 0 - ns

TF5INCK / TCKF5IN 6-input function: F5IN input 1.0 / 0 - 1.1 / 0 - ns

TIF6CK / TCKIF6 6-input function: F/G inputs via F6 MUX 1.6 / 0 - 1.8 / 0 - ns

TDICK / TCKDI BX/BY inputs 0.8 / 0 - 0.8 / 0 - n s

TCECK / TCKCE CE input 0.9 / 0 - 0.9 / 0 - n s

TRCK / TCKR SR/BY inputs (synchronous) 0.8 / 0 - 0.8 / 0 - n s

Clock CLK

TCH Minimum pulse width, Hig h - 1.9 - 1.9 ns

TCL Minimum pulse width, Low - 1.9 - 1.9 ns

Set/Reset

TRPW Minimum pulse width, SR/BY inputs - 3.1 - 3.1 ns

TRQ Del ay from SR/BY input s to XQ/Y Q out put s

(asynchronous) - 1.1 - 1.3 ns

TIOGSRQ Dela y from GSR to XQ/YQ outputs - 9.9 - 11.7 ns

FTOG Toggle freque ncy (for expor t con trol) - 263 - 263 MHz

Notes:

1. A zero hold time listing indicates no hold t ime or a negative hold tim e.

Spartan -II 2.5V FPGA Family: DC a nd Switching Characteristics

DS001-3 (v2.4) August 28, 2001 www.xilinx.com Module 3 of 4

Preliminary Product Specification 1-800-255-7778 15

CLB Arithmetic Switching Characteristics

Setup time s not list ed explicitly can be approximated by dec reasing the co mbinat oria l del ays by th e set up t ime adj us tment

listed. Precise values are provided by the timing analyzer.

Sym bol De sc ript ion

Speed Grad e

Units

-6 -5

MinMaxMinMax

Combinatorial Delays

TOPX F operand inputs to X via XOR - 0.8 - 0.9 ns

TOPXB F operand input to XB output - 1.3 - 1.5 ns

TOPY F operand input to Y via XOR - 1.7 - 2.0 ns

TOPYB F operand input to YB output - 1.7 - 2.0 ns

TOPCYF F operand input to COUT output - 1.3 - 1.5 ns

TOPGY G operand inputs to Y via XOR - 0.9 - 1.1 ns

TOPGYB G opera nd input to YB output - 1.6 - 2. 0 ns

TOPCYG G operand input to COUT output - 1.2 - 1.4 ns

TBXCY BX initialization input to COUT - 0.9 - 1.0 ns

TCINX CIN input to X outpu t via XOR - 0.4 - 0.5 ns

TCINXB C IN i n p ut to XB - 0.1 - 0 . 1 n s

TCINY CIN input to Y via XOR - 0.5 - 0.6 ns

TCINYB C IN i n p ut to YB - 0.6 - 0 . 7 n s

TBYP CIN inpu t to COUT output - 0.1 - 0.1 ns

Multiplier Oper ation

TFANDXB F1/2 operand inputs to XB outp ut via AND - 0.5 - 0.5 ns

TFANDYB F1/2 opera nd inputs to YB output via AND - 0.9 - 1.1 ns

TFANDCY F1/2 operand inputs to COUT output via AND - 0.5 - 0.6 ns

TGANDYB G1/2 operand inputs to YB output via AND - 0.6 - 0.7 ns

TGANDCY G1/2 operand inputs to COUT output via AND - 0.2 - 0.2 ns

Setup/Hold Times with Respect to Clock CLK(1)

TCCKX / TCKCX CIN input to FFX 1.1 / 0 - 1.2 / 0 - ns

TCCKY / TCKCY CIN input to FFY 1.2 / 0 - 1.3 / 0 - ns

Notes:

1. A zero hold time listing indicates no hold t ime or a negative hold tim e.

Spartan -II 2.5V FPGA Family: DC a nd Switching Characteristics

Modu le 3 of 4 www.xilinx.com DS001-3 (v 2.4) August 28, 2001

16 1-800-255-7778 Preliminary Product Specification

CLB Distributed RAM Switching Characteristics

CLB Shift Register Switching Characteristics

Symb ol Description

Speed Grade

Units

-6 -5

Min Max Min Max

Sequential Delays

TSHCKO16 Clock CLK to X/Y outp uts (WE active, 16 x 1 mode) - 2. 2 - 2 .6 ns

TSHCKO32 Clock CLK to X/Y outp uts (WE active, 32 x 1 mode) - 2. 5 - 3 .0 ns

Setup/Hold Times with Respect to Clock CLK(1)

TAS / TAH F/G address inputs 0.7 / 0 - 0.7 / 0 - ns

TDS / T DH B X/BY d a ta in puts ( D IN) 0.8 / 0 - 0. 9 / 0 - n s

TWS / T WH CE input (WS) 0.9 / 0 - 1.0 / 0 - ns

Clock CLK

TWPH Minimum pulse width, High - 2.9 - 2.9 ns

TWPL Minimum pulse width, Low - 2.9 - 2.9 ns

TWC Minimum clock period to meet address write cycle time - 5.8 - 5.8 ns

Notes:

1. A zero hold time listing indicates no hold t ime or a negative hold tim e.

Symb ol Description

Speed Grade

Units

-6 -5

Min Max Min Max

Sequential Delays

TREG Clock CLK to X/Y outputs - 3.47 - 3.88 ns

Setup Times with Respect to Clock CLK

TSHDICK B X/BY d a ta i n puts ( D IN) 0.8 - 0. 9 - n s

TSHCECK CE input (WS) 0.9 - 1.0 - ns

Clock CLK

TSRPH Minimum pulse width, High - 2.9 - 2.9 ns

TSRPL Minimum pulse width, Low - 2.9 - 2.9 ns

Spartan -II 2.5V FPGA Family: DC a nd Switching Characteristics

DS001-3 (v2.4) August 28, 2001 www.xilinx.com Module 3 of 4

Preliminary Product Specification 1-800-255-7778 17

Block RAM Switching Characteristics

TBUF Sw itching Characteristics

JTAG Test Access Port Switching Characteristics

Sym bol De sc ript ion

Spee d Grad e

Units

-6 -5

Min Max Min Max

Sequential Delays

TBCKO Clock CLK to DOUT output - 3.4 - 4.0 ns

Setup/Hold Times with Respect to Clock CLK(1)

TBA CK / T BCKA ADDR inputs 1.4 / 0 - 1.4 / 0 - ns

TBDCK/ TBCKD DIN inputs 1.4 / 0 - 1.4 / 0 - ns

TBECK/ TBCKE EN inputs 2. 9 / 0 - 3.2 / 0 - ns

TBRCK/ TBCKR RST input 2.7 / 0 - 2.9 / 0 - ns

TBWCK/ TBCKW WEN input 2.6 / 0 - 2.8 / 0 - ns

Clock CLK

TBPWH Minimum pulse width, High - 1.9 - 1.9 ns

TBPWL Mi nimum pulse width, Low - 1.9 - 1. 9 ns

TBCCS CLKA -> CLKB setup time for different ports - 3.0 - 4.0 ns

Notes:

1. A zero hold time listing indicates no hold t ime or a negative hold tim e.

Symbol Description

Speed Grade

Units

-6 -5

Max Max

Combinatorial Delays

TIO IN i n p ut to O U T ou tpu t 0 0 ns

TOFF TRI input to OUT output high impedance 0.1 0.2 ns

TON TRI input to valid data on OUT output 0.1 0.2 ns

Symbol Description

Speed Grade

Units

-6 -5

Min Max Min Max

Setup and Hold Times with Respect to TCK

TTAPTCK / TTCKTAP TMS and TDI setup and hol d times 4.0 / 2.0 - 4.0 / 2.0 - ns

Sequential Delays

TTCKTDO Outp ut delay from clock TCK to o utpu t TDO - 11.0 - 11.0 ns

FTCK Max imum TCK c lock frequency - 33 - 33 MHz

Spartan -II 2.5V FPGA Family: DC a nd Switching Characteristics

Modu le 3 of 4 www.xilinx.com DS001-3 (v 2.4) August 28, 2001

18 1-800-255-7778 Preliminary Product Specification

Revision History

The Spartan-II Family Data Sheet

DS001-1, Spa r t a n-I I 2.5V FPGA Fami ly: Introduction and Ordering Information (Module 1)

DS001-2, Spa r t a n-I I 2.5V FPGA Fami ly: Functional Description (M odule 2)

DS001-3, Spartan-II 2.5V FPGA Family: DC and Switching Characteristics (Module 3)

DS001-4, Spa r t a n-I I 2.5V FPGA Fami ly: Pinout Tables (M odule 4)

Version No. Date Description

2.0 09/18/00 Sectioned the Spartan-II Family data sheet into four modules. Updated timing to reflect the

latest speed files. Added current supply numbers and XC2S200 -5 timing numbers. A pprov ed

-5 timing numbers as preliminary information with exceptions as noted.

2.1 11/02 /00 Removed Power Down feature.

2.2 01 /19/01 DC and timing numbers updat ed to Prelimina ry for the XC2S50 and XC2S100. Indu str ial

power-on current specifications and -6 DLL timing numbers added. Power-on specification

clarified.

2.3 03/09 /01 Added not e on power seq uencing. Clarified power-on curre nt requirement.

2.4 08/28/01 Added -6 preliminary timing. Added typical and industrial standby current numbers. Specified

min. power-on current by junction tem perature instead of by device type (Com me rcial vs.

Industr ial) . Eliminated minimum V CCINT ramp time requirement. Removed footnot e limiting

DLL operation to the Commercial temperature range.