Product Brief
May 2000
ORCA
® OR T4622 Field-Programmable System Chip (FPSC)
Four Channel x 622 Mbits/s Backplane Transceiver
Introduction
Lucent Technologies Microelectronics Group has
developed a solution for designers who need the
many advantages of FPGA-based design implemen-
tation, coupled with high-speed serial backplane data
transfer. The 622 Mbits/s backplane transceiv er
offers a clockless, high-speed interface for interde-
vice communication on a board or across a back-
plane. The built-in clock recovery of the ORT4622
allows for higher system performance, easier-to-
design clock domains in a multiboard system, and
fewer signals on the backplane. Network designers
will benefit from the backplane transceiver as a net-
work termination device. The backplane transceiver
offers SONET scrambling/descrambling of data and
streamlined SONET framing, pointer moving, and
transport overhead handling, plus the programmable
logic to terminate the network into proprietary sys-
tems. For non-SONET applications, all SONET func-
tionality is hidden from the user and no prior
networking knowledge is required.
Embedded Core Features
■Implemented in an
ORCA
Series 3 FPGA array.
■Allows wide range of applications for SONET net-
work termination application as well as generic
data moving for high-speed backplane data trans-
fer.
■No knowledge of SONET/SDH needed in generic
applications. Simply supply data, 78 MHz clock,
and a frame pulse.
■High-speed interface (HSI) function for clock/data
recov ery serial backplane data transfer without
external clocks.
■HSI function uses Lucent Technologies Microelec-
tronics Group’s proven 622 Mbits/s serial interface
core.
■Four-channel HSI function provides 622 Mbits/s
serial interface per channel for a total chip band-
width of 2.5 Gbits/s (full duplex).
■LVDS I/Os compliant with
EIA
*-644, support hot
insertion.
■8:1 data multiplexing/demultiplexing for 77.76 MHz
byte-wide data processing in FPGA logic.
■On-chip phase-lock loop (PLL) clock meets B jitter
tolerance specification of ITU-T Recommendation
G.958 (0.6 UIp-p at 250 kHz).
■Powerdown option of HSI receiver on a per-
channel basis.
■Highly efficient implementation with only 3% over-
head vs. 25% for 8B10B coding.
■In-Band management and configuration.
■Streamlined pointer processor (pointer mover) for
8 kHz frame alignment to system clocks.
■Built- in boun dry scan (
IEEE
† 1149.1 JTAG).
*
EIA
is a re
g
istered trademark of Electronic Industries Associa-
tion.
†
IEEE
is a re
g
istered trademark of The Institute of Electrical and
Electronics En
g
ineers, Inc.
Table 1.
ORCA
ORT4622—Available FPGA Lo
g
ic
* The embedded core and interface are not included in t he above
g
ate counts. The usable
g
ate count ran
g
e from a lo
g
ic-onl
y
g
ate count to
a
g
ate count assumin
g
30% of the PFUs/SLICs bein
g
used as RAMs. The lo
g
ic-onl
y
g
ate count includes each PFU/SLIC
(
counted as
108
g
ates per PFU/SLIC
)
, includin
g
12
g
ates pre-LUT/FF pair
(
ei
g
ht per PFU
)
, and 12
g
ates per SLC/FF pair
(
one per PFU
)
. Each of the
four PIOs per PIC is counted as 16
g
ates
(
two FFs, fast-capture latch, output lo
g
ic, CLK drivers, and I/O buffers
)
. PFUs used as RAM are
counted at four
g
ates per bit, with each PFU capable of implementin
g
a 32 x 4 RAM
(
or 512
g
ates
)
per PFU.
Device Usable
S
y
stem
Gates*
Number of
LUTs Number of
Re
g
isters Max User
RAM Max User
I/Os Arra
y
Size Number of
PFUs
ORT4622 60K—120K 4032 5304 64K 259 18 x 28 504
2Lucent Technologies Inc.
Product Brief
May 2000
Four Channel x 622 Mbits/s Backplane Transceiver
ORCA
ORT4622 FPSC
Embedded Core Features (continued)
■FIFOs ali
g
n incomin
g
data acros s all fo ur c hannels for ST S-48
(
2.5 Gbits /s
)
operati on
(
in
q
uad STS- 12 f orm at
)
.
■1 + 1 protect ion suppo rt s S TS -12/STS- 48 redundanc
y
b
y
either sof t w are or hardw are control for protect ion switch-
in
g
applications.
■Pseudo-SONET protocol includin
g
A1/A2 framin
g
.
■SONET scramblin
g
and descramblin
g
for re
q
uired ones densit
y
(
optional
)
.
■Selected transport overhead
(
TOH
)
b
y
tes insertion and extraction for interdevice communication via the TOH
serial link.
5-8098(F)
Figure 1.
ORCA
ORT4622 Block Diagram
5-8337(F)
Figure 2. SONET Network Terminaton Application
CLOCK/DATA
RECOVERY
4 FULL-
DUPLEX
SERIAL
CHANNELS
BYTE-
WIDE
DATA FPGA LOGIC STANDARD
FPGA
I/Os
LVDS
622 Mbits/s
DATA
622 Mbits/s
DATA
PSEUDO-
SONET
FRAMER
• POINTER MOVER
• SCRA MB LING
• FIFO ALIGNMENT
• TOH PROCESSOR
CUSTOMER
NETWORK
TERMINATION
EMBEDDED CORE
UTOPIA,
DS3,
SDL,
ETC.
ORT4622
FPSC
ADM
ADM
ADM
ADM SONET
RING
CUSTOMER
BACKPLANE
Product Brief
May 2000
Lucent Technologies Inc. 3
Four Channel x 622 Mbits/s Backplane Transceiver
ORCA
ORT4622 FPSC
Embedded Core Features (continued)
5-8338(F)
Figure 3. High-Speed Backplane Data Transfer
8
8
8
8
BOARD A
ORT4622
FPSC
4 x 622 Mbits/s
SYSTEM BACKPLANE
78 MHZ
8
8
8
8
BOARD B
ORT4622
FPSC
78 MHZ
BUS
BUS
44 Lucent Technologies Inc.
Product Brief
May 2000
Four Channel x 622 Mbits/s Backplane Transceiver
ORCA
ORT4622 FPSC
FPSC Hi
g
hli
g
hts
■Implemented as an embedded core in the
ORCA
Series 3+ FPSC architecture.
■Allows the user to inte
g
rate the core with up to 120K
g
ates of pro
g
rammable lo
g
ic
(
all in one device
)
and
provides up to 242 user I/Os in addition to the
embedded core I/O pins.
■FPGA portion retains all of the features of the
ORCA
Series 3 FPGA architecture:
— High-perf ormance, cost-effectiv e, 0.25 µm, 5-le vel
metal technology.
— Twin-quad programmable function unit (PFU)
architecture with eight 16-bit look-up tables
(LUTs) per PFU, organized in two nibbles for use
in nibble- or byte-wide functions. Allows for mixed
arithmetic and logic functions in a single PFU.
— Softwired LUTs (SWL) allow fast cascading of up
to three levels of LUT logic in a single PFU.
— Supplemental logic and interconnect cell (SLIC)
provides 3-statable buffers, up to 10-bit decoder,
and
PAL
*-like AND-OR-INVERT (AOI) in each
programmable logic cell (PLC).
— Up to three ExpressCLK inputs allow extremely
fast clocking of signals on- and off-chip plus
access to internal general clock routing.
— Dual-use microprocessor interface (MPI) can be
used for configuration, as well as for a general-
purpose interface to the FPGA. Glueless interf ace
to
i960
† and
PowerPC
‡ processors with user-
configurable address space provided.
*
PAL
is a trademark of Advanced Micro Devices, Inc.
†
i960
is a re
g
istered trademark of Intel Corporation.
‡
PowerPC
is a re
g
istered trademark of International Business
Machines Corporation.
— Programmable clock manager (PCM) adjusts
clock phase and duty cycle for input clock rates
from 5 MHz to 120 MHz. The PCM may be com-
bined with FPGA logic to create complex
functio ns, such as digit al phas e- l ocked loop s,
frequen cy cou nter s, and frequenc y sy nth esizers
or clock doublers. Two PCMs are provided per
device.
— True internal 3-state, bidirectional buses with
simple control provided by the SLIC.
— 32 x 4 RAM per PFU, configurable as single or
dual port. Create large, fast RAM/ROM blocks
(128 x 8 in only eight PFUs) using the SLIC
decoders as bank drivers.
— Bui lt -in bound ary scan (
IEEE
114 9.1 JTAG) and
TS_ALL testability function to 3-state all I/O pins.
■High-speed on-chip interface provided between
FPGA logic and embedded core to reduce bottle-
necks typically found when interfacing off-chip.
Software Su
pp
ort
■Supported b
y
ORCA
Foundr
y
software and third-
part
y
CAE tools for implementin
g
ORCA
Series 3+
devices and simulation/timin
g
anal
y
sis with the
embedded core functions.
■Embedded core confi
g
uration options and simulation
netlists
g
enerated b
y
the FPSC Confi
g
uration Man-
a
g
er utilit
y
.
Product Brief
May 2000
Lucent Technologies Inc. 5
Four Channel x 622 Mbits/s Backplane Transceiver
ORCA
ORT4622 FPSC
Ordering Information
5-6435 (F).i
DEVICE TYPE
PACKAGE TYPE
ORT4622 BC
NUMBER OF PINS
TEMPERATURE RANG E
432
Table 2. Voltage Options
Table 3. Temperature Options
Table 4. Package Type Options
Table 5
. ORCA
Series 3+ Package Matrix
Key: C = commercial, I = industrial.
Device Voltage
ORT4622 2.5 V/3.3 V
Symbol Description Temperature
(Blank) Commercial 0 °C to 70 °C
I Industrial –40 °C to +85 °C
Symbol Description
BC Enhanced Ball Grid Array (EB GA)
BM Plastic Ball Grid Array, Multilayer
Device
Package
432-Pin
EBGA 680-Pin
PBGAM
BC432 BM680
ORT4622 CI CI
Lucent Technologies Inc. reserves the right to make changes to the product(s) or infor mation contained herein without notice. No liability is assumed as a result of their use or application. No
rights under any patent accompany the sale of any such product(s) or information.
ORCA
is a registered trademark of Lucent Technologies Inc. Foundry is a trademark of Xilinx, Inc.
Copyright © 2000 Lucent Technologies Inc.
All Rights Reserved
May 2000
PN00-072FPGA (Replaces DS99-143FPGA -1)
For additional information, contact your Microelectronics Group Account Manager or the following:
INTERNET: http://www.lucent.com/micro, or for FPGA information, http://www.lucent.com/orca
E-MAIL: docmaster@micro.lucent.com
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Tel. (65) 778 8833, FAX (65) 777 7495
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