RMLV0816BGSD-4S2#AC0 - RENESAS TECHNOLOGY

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RMLV0816BGSD - 4S2

8Mb Advanced LPSRAM (512k word × 16bit / 1024k word x 8bit)

Description

The RMLV0816BGSD is a family of 8-Mbit static RAMs organized 524,288-word × 16-bit, fabricated by Renesas’s

high-performance Advanced LPSRAM technologies. The RMLV0816BGSD has realized higher density, higher

performance and low power consumption. The RMLV0816BGSD offers low power standby power dissipation;

therefore, it is suitable for battery backup systems. It is offered in 52pin TSOP (II).

Features

 Single 3V supply: 2.4V to 3.6V

 Access time:

── Power supply voltage from 2.7V to 3.6V: 45ns (max.)

── Power supply voltage from 2.4V to 2.7V: 55ns (max.)

 Current consumption:

── Standby: 0.45µA (typ.)

 Equal access and cycle times

 Common data input and output

── Three state output

 Directly TTL compatible

── All inputs and outputs

 Battery backup operation

Part Name Information

Part Name Power supply Access time Temperature

Range Package

RMLV0816BGSD-4S2

2.7V to 3.6V 45 ns

-40 ~ +85°C 10.79mm × 10.49mm 52pin plastic µTSOP (II)

2.4V to 2.7V 55 ns

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Pin Arrangement

Pin Description

Pin name Function

VCC Power supply

VSS Ground

A0 to A18 Address input (word mode)

A-1 to A18 Address input (byte mode)

DQ0 to DQ15 Data input/output

CS1# Chip select 1

CS2 Chip select 2

OE# Output enable

WE# Write enable

LB# Lower byte select

UB# Upper byte select

BYTE# Byte control mode enable

NC No connection

A14

A13

A12

A11

A10

CS1#

WE#

Vcc

CS2

A18

A17

BYTE#

UB#

Vss

LB#

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

Vss

52pin



TSOP (II)

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Block Diagram

CS1#

CS2

LB#

UB#

WE#

OE#

A18

BYTE#

DQ0

DQ1

DQ7

DQ8

DQ9

DQ15

/ A -1

Vcc

Vss

COLUMN DECODER

x8 / x16

CONTROL

BUFFER

ADDRESS

BUFFER

ROW

DECODER

BUFFER

DAT

SELECTOR

SENSE / WRITE AMPLIFIER

CLOCK

GENERATOR

MEMORY ARRAY

512k-word x16-bit

1M-word x8-bit

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Operation Table

CS1# CS2 BYTE# UB# LB# WE# OE# DQ0~7 DQ8~14 DQ15 Operation

H X X X X X X High-Z High-Z High-Z Stand-by

X L X X X X X High-Z High-Z High-Z Stand-by

X X H H H X X High-Z High-Z High-Z Stand-by

L H H H L L X Din High-Z High-Z Write in lower byte

L H H H L H L Dout High-Z High-Z Read in lower byte

L H H H L H H High-Z High-Z High-Z Output disable

L H H L H L X High-Z Din Din Write in upper byte

L H H L H H L High-Z Dout Dout Read in upper byte

L H H L H H H High-Z High-Z High-Z Output disable

L H H L L L X Din Din Din Word write

L H H L L H L Dout Dout Dout Word read

L H H L L H H High-Z High-Z High-Z Output disable

L H L X X L X Din High-Z A-1 Byte write

L H L X X H L Dout High-Z A-1 Byte read

L H L X X H H High-Z High-Z A-1 Output disable

Note 1. H: VIH L:V

IL X: V

IH or VIL

Absolute Maximum Ratings

Parameter Symbol Value unit

Power supply voltage relative to VSS V

CC -0.5 to +4.6 V

Terminal voltage on any pin relative to VSS V

T -0.5*2 to VCC+0.3*3 V

Power dissipation PT 0.7 W

Operation temperature Topr -40 to +85 °C

Storage temperature range Tstg -65 to +150 °C

Storage temperature range under bias Tbias -40 to +85 °C

Note 2. -3.0V for pulse ≤ 30ns (full width at half maximum)

3. Maximum voltage is +4.6V.

DC Operating Conditions

Parameter Symbol Min. Typ. Max. Unit Test conditions Note

Supply voltage VCC 2.4 3.0 3.6 V

VSS 0 0 0 V

Input high voltage VIH 2.0 ─ V

CC+0.2 V Vcc=2.4V to 2.7V

2.2 ─ V

CC+0.2 V Vcc=2.7V to 3.6V

Input low voltage VIL -0.2 ─ 0.4 V Vcc=2.4V to 2.7V 4

-0.2 ─ 0.6 V Vcc=2.7V to 3.6V 4

Ambient temperature range Ta -40 ─ +85 °C

Note 4. -3.0V for pulse ≤ 30ns (full width at half maximum)

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DC Characteristics

Parameter Symbol Min. Typ. Max. Unit Test conditions

Input leakage current | ILI | ─ ─ 1 A Vin = VSS to VCC

Output leakage current

| ILO | ─ ─ 1 A

BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V

CS1# = VIH or CS2 = VIL or OE# = VIH

or WE# = VIL or LB# = UB# = VIH,

VI/O = VSS to VCC

Average operating current

ICC1

─ 20*5 25 mA

Cycle = 55ns, duty =100%, II/O = 0mA,

BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V

CS1# = VIL, CS2 = VIH, Others = VIH/VIL

─ 25*5 30 mA

Cycle = 45ns, duty =100%, II/O = 0mA,

BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V

CS1# = VIL, CS2 = VIH, Others = VIH/VIL

ICC2 ─ 1.5*5 3 mA

Cycle = 1s, duty =100%, II/O = 0mA,

BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V

CS1# ≤ 0.2V, CS2 ≥ VCC-0.2V,

VIH ≥ VCC-0.2V, VIL ≤ 0.2V

Standby current ISB ─ ─ 0.3 mA BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V

CS2 = VIL, Others = VSS to VCC

Standby current

ISB1

─ 0.45*5 2 A ~+25°C Vin = VSS to VCC,

BYTE# ≥ Vcc -0.2V or

BYTE# ≤ 0.2V

(1) CS2 ≤ 0.2V or

(2) CS1# ≥ VCC-0.2V,

CS2 ≥ VCC-0.2V or

(3) LB# = UB# ≥ VCC-0.2V,

CS1# ≤ 0.2V

CS2 ≥V

-0.2V

─ 0.6*6 4 A ~+40°C

─ ─ 7 A ~+70°C

─ ─ 10 A ~+85°C

Output high voltage

VOH 2.4 ─ ─ V

BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V

IOH = -1mA

Vcc≥2.7V

VOH2 2.0 ─ ─ V

BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V

IOH = -0.1mA

Output low voltage

VOL ─ ─ 0.4 V

BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V

IOL = 2mA

Vcc≥2.7V

VOL2 ─ ─ 0.4 V

BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V

IOL = 0.1mA

Note 5. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested.

Note 6. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=40ºC), and not 100% tested.

Capacitance

(Ta =25°C, f =1MHz)

Parameter Symbol Min. Typ. Max. Unit Test conditions Note

Input capacitance C in ─ ─ 8 pF Vin =0V 7

Input / output capacitance C I/O ─ ─ 10 pF VI/O =0V 7

Note 7. This parameter is sampled and not 100% tested.

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AC Characteristics

Test Conditions (Vcc = 2.4V ~ 3.6V, Ta = -40 ~ +85°C)

 Input pulse levels:

VIL = 0.4V, VIH = 2.4V (Vcc=2.7V to 3.6V)

VIL = 0.4V, VIH = 2.2V (Vcc=2.4V to 2.7V)

 Input rise and fall time: 5ns

 Input and output timing reference level: 1.4V

 Output load: See figures (Including scope and jig)

Read Cycle

Parameter Symbol

Vcc=2.7V to 3.6V Vcc=2.4V to 2.7V Unit Note

Min. Max. Min. Max.

Read cycle time tRC 45 ─ 55 ─ ns

Address access time tAA ─ 45 ─ 55 ns

Chip select access time tACS1 ─ 45 ─ 55 ns

tACS2 ─ 45 ─ 55 ns

Output enable to output valid tOE ─ 22 ─ 30 ns

Output hold from address change tOH 10 ─ 10 ─ ns

LB#, UB# access time tBA ─ 45 ─ 55 ns

Chip select to output in low-Z tCLZ1 10 ─ 10 ─ ns 8,9

tCLZ2 10 ─ 10 ─ ns 8,9

LB#, UB# enable to low-Z tBLZ 5 ─ 5 ─ ns 8,9

Output enable to output in low-Z tOLZ 5 ─ 5 ─ ns 8,9

Chip deselect to output in high-Z tCHZ1 0 18 0 20 ns 8,9,10

tCHZ2 0 18 0 20 ns 8,9,10

LB#, UB# disable to high-Z tBHZ 0 18 0 20 ns 8,9,10

Output disable to output in high-Z tOHZ 0 18 0 20 ns 8,9,10

Note 8. This parameter is sampled and not 100% tested.

9. At any given temperature and voltage condition, tCHZ1 max is less than tCLZ1 min, tCHZ2 max is less than tCLZ2

min, tBHZ max is less than tBLZ min, and tOHZ max is less than tOLZ min, for any device.

10. tCHZ1, tCHZ2, tBHZ and tOHZ are defined as the time when the DQ pins enter a high-impedance state and are not

referred to the DQ levels.

1.4V

RL = 500 ohm

CL = 30 pF

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Write Cycle

Parameter Symbol

Vcc=2.7V to 3.6V Vcc=2.4V to 2.7V Unit Note

Min. Max. Min. Max.

Write cycle time tWC 45 ─ 55 ─ ns

Address valid to write end tAW 35 ─ 50 ─ ns

Chip select to write end tCW 35 ─ 50 ─ ns

Write pulse width tWP 35 ─ 40 ─ ns 11

LB#,UB# valid to write end tBW 35 ─ 50 ─ ns

Address setup time to write start tAS 0 ─ 0 ─ ns

Write recovery time from write end tWR 0 ─ 0 ─ ns

Data to write time overlap tDW 25 ─ 25 ─ ns

Data hold from write end tDH 0 ─ 0 ─ ns

Output enable from write end tOW 5 ─ 5 ─ ns 12

Output disable to output in high-Z tOHZ 0 18 0 20 ns 12,13

Write to output in high-Z tWHZ 0 18 0 20 ns 12,13

Note 11. tWP is the interval between write start and write end.

A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active.

A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#.

A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive.

12. This parameter is sampled and not 100% tested.

13. tOHZ and tWHZ are defined as the time when the DQ pins enter a high-impedance state and are not referred to

the DQ levels.

BYTE# Timing Conditions

Parameter Symbol

Vcc=2.7V to 3.6V Vcc=2.4V to 2.7V Unit Note

Min. Max. Min. Max.

Byte setup time tBS 5 ─ 5 ─ ms

Byte recovery time tBR 5 ─ 5 ─ ms

BYTE# Timing Waveforms

CS2

BYTE#

tBS t

CS1#

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Timing Waveforms

Read Cycle*14

Note 14. BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V

15. tCHZ1, tCHZ2, tBHZ and tOHZ are defined as the time when the DQ pins enter a high-impedance state and are not

referred to the DQ levels.

16. This parameter is sampled and not 100% tested

17. At any given temperature and voltage condition, tCHZ1 max is less than tCLZ1 min, tCHZ2 max is less than tCLZ2

min, tBHZ max is less than tBLZ min, and tOHZ max is less than tOLZ min, for any device.

tAA

CS1#

tOH

tCLZ1

tACS1

tOE

tOLZ

tCHZ1

OE#

WE# VIH

tOHZ

WE# = “H” level

tRC

tBLZ tBHZ

LB#,UB#

tBA

CS2 tACS2

tCLZ2 tCHZ2

High impedance Valid Data

*16,17

*15,16,17

Valid address

A0~18

A -1~18

(Word Mode)

(Byte Mode)

DQ0~15

DQ0~7

(Word Mode)

(Byte Mode)

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Write Cycle (1)*18 (WE# CLOCK, OE#=”H” while writing)

Note 18. BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V

19. tWP is the interval between write start and write end.

A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active.

A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#.

A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive.

20. tOHZ and tWHZ are defined as the time when the DQ pins enter a high-impedance state and are not referred to

the DQ levels.

21. This parameter is sampled and not 100% tested

22. During this period, DQ pins are in the output state so input signals must not be applied to the DQ pins.

CS1#

tCW

tWHZ

OE#

WE#

tDH

tWC

LB#,UB#

tBW

CS2 tCW

Valid address

tWR

tAW

tAS

tWP

tDW

*19

*20,21

tOHZ

Valid Data

*22

A0~18

A -1~18

(Word Mode)

(Byte Mode)

DQ0~15

DQ0~7

(Word Mode)

(Byte Mode)

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Write Cycle (2)*23 (WE# CLOCK, OE# Low Fixed)

Note 23. BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V

24. tWP is the interval between write start and write end.

A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active.

A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#.

A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive.

25. tWHZ is defined as the time when the DQ pins enter a high-impedance state and are not referred to the DQ

levels.

26. This parameter is sampled and not 100% tested.

27. During this period, DQ pins are in the output state so input signals must not be applied to the DQ pins.

CS1#

tCW

tWHZ

OE#

WE#

tDH

tWC

LB#,UB#

tBW

CS2 tCW

Valid address

tWR

tAW

tAS

tWP

tDW

tOW

*24

*25,26

VIL

OE# = “L” level

Valid Data

*27 *27

A0~18

A -1~18

(Word Mode)

(Byte Mode)

DQ0~15

DQ0~7

(Word Mode)

(Byte Mode)

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Write Cycle (3)*28 (CS1#, CS2 CLOCK)

Note 28. BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V

29. tWP is the interval between write start and write end.

A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active.

A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#.

A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive.

CS1#

tCW

OE#

WE#

tDH

tWC

LB#,UB#

tBW

CS2

Valid address

tWR

tAW

tAS

tWP

tDW

VIH

OE# = “H” level

tCW tAS

*29

Valid Data

A0~18

A -1~18

(Word Mode)

(Byte Mode)

DQ0~15

DQ0~7

(Word Mode)

(Byte Mode)

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Write Cycle (4)*30 (LB#, UB# CLOCK, Word Mode)

Note 30. BYTE# ≥ Vcc -0.2V

31. tWP is the interval between write start and write end.

A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active.

A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#.

A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive.

CS1#

tCW

OE#

WE#

tDH

tWC

LB#,UB#

tBW

CS2

Valid address

tWR

tAW

tAS

tWP

tDW

VIH

OE# = “H” level

tCW

*31

Valid Data

A0~18

(Word Mode)

DQ0~15

(Word Mode)

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Low VCC Data Retention Characteristics

Parameter Symbol Min. Typ. Max. Unit Test conditions*34

VCC for data retention VDR 1.5 ─ 3.6 V

Vin ≥ 0V,

BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V

(1) CS2 ≤ 0.2V or

(2) CS1# ≥ VCC-0.2V,

CS2 ≥ VCC-0.2V or

(3) LB# = UB# ≥ VCC-0.2V,

CS1# ≤ 0.2V, CS2 ≥ VCC-0.2V

Data retention current ICCDR

─ 0.45*32 2 A ~+25°C VCC = 3.0V, Vin ≥ 0V,

BYTE# ≥ Vcc -0.2V or

BYTE# ≤ 0.2V

(1) CS2 ≤ 0.2V or

(2) CS1# ≥ VCC-0.2V,

CS2 ≥ VCC-0.2V or

(3) LB# = UB# ≥ VCC-0.2V,

CS1# ≤ 0.2V,

CS2 ≥ VCC-0.2V

─ 0.6*33 4 A ~+40°C

─ ─ 7 A ~+70°C

─ ─ 10 A ~+85°C

Chip deselect time to data retention tCDR 0 ─ ─ ns

See retention waveform.

Operation recovery time tR 5 ─ ─ ms

Note 32. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested.

33. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=40ºC), and not 100% tested.

34. CS2 controls address buffer, WE# buffer, CS1# buffer, OE# buffer, LB# buffer, UB# buffer and DQ buffer. If

CS2 controls data retention mode, Vin levels (address, WE#, CS1#, OE#, LB#, UB#, DQ) can be in the high

impedance state. If CS1# controls data retention mode, CS2 must be CS2 ≥ VCC-0.2V or CS2 ≤ 0.2V. The

other inputs levels (address, WE#, OE#, LB#, UB#, DQ) can be in the high-impedance state.

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Low Vcc Data Retention Timing Waveforms (CS1# controlled)*35

Low Vcc Data Retention Timing Waveforms (CS2 controlled)*35

Low Vcc Data Retention Timing Waveforms (LB#,UB# controlled, Word Mode)*36

Note 35. BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V

36. BYTE# ≥ Vcc -0.2V

LB#,UB#

VCC

LB#,UB# Controlled

tCDR tR

2.4V 2.4V

2.0V 2.0V

LB#

UB# ≥

-0.2V

CS1#

VCC

CS1# Controlled

tCDR tR

2.4V 2.4V

2.0V 2.0V

CS1# ≥

-0.2V

CS2

VCC

CS2 Controlled

tCDR tR

2.4V 2.4V

0.4V 0.4V

CS2 ≤0.2V

All trademarks and registered trademarks are the property of their respective owners.

Revision History RMLV0816BGSD Data Sheet

Rev. Date

Description

Page Summary

1.00 2014.11.28 ─ First Edition issued

2.00 2015.06.26 P.1, 5

P.5

P.13

Standby current ISB1 : 25°C 0.6µA ->0.45µA (typ.), 40°C 2µA ->0.6µA (typ.)

Average operating current ICC2 : 25°C 2mA ->1.5mA (typ.)

Data retention current ICCDR : 25°C 0.6µA ->0.45µA (typ.), 40°C 2µA ->0.6µA (typ.)

Notice

1. Descripti ons of cir cuit s , sof tware an d other relat ed inform ation in this document are pr ov i de d only to illustr a te the o per a t i on of sem ic o nd uc tor pr odu c ts and a ppl ic ation ex amples. You ar e f u ll y r es p ons i bl e f o r

the incorpor ation of the s e c i r c u its, s oftw ar e , and inf ormation in t h e de s ign o f your equi pm e nt. Rene s as Electronics as s umes no responsibility for any losses incurred by you or third parties arising from the

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incur r ed by you or third par ties arising from the use of any Rene s as Electroni c s pr o du c t for w hic h t h e product is not int e nded by Re ne s as E l ec troni c s .

6. You shou ld us e t h e Rene s a s E lectr o nic s p r odu c ts des c r i be d in t h is docum e nt withi n the ra nge s p ec i fied by Re nesas El ec tron ic s , esp ec ial ly wit h r espect to the m aximum r ating, operating su pply volt a ge

range, movement pow er v ol tage ran ge, heat radiat ion c ha r ac teri s tics , installat i on and other p r odu c t char acter is tics . Renes as Electroni c s s hal l h av e no l iabi li ty fo r malf u nc tions or damag es arising ou t of t he

use of R enes a s E le c tronic s p r odu c ts bey o nd such spe c i f i ed ra ng es .

7. Alt ho ugh R ene s as E l ec troni c s e ndeavors to im pr ove the qua lity and r e liab il ity of its products, semic ondu c tor pr o ducts have specif ic characterist ics such as the occurrence of failure at a certain rate and

malf un c tions u nd er c er tain us e c o nd itions. Furthe r, Renes a s E le c tronic s produc ts ar e no t s u bj ect t o radiation res i s tance design. P l ease be sur e to implement s afet y m ea s ur e s to guard t he m ag ains t t he

possi bili ty of physi c a l in ju r y , and inju ry or dam ag e c au s e d by fire in t h e event of th e failur e o f a Renesas El ec tron ic s produc t, such as safety design for hardware and software including but not limited to

redundan c y , fire control an d m alfunction pr e v ention, approp ri ate treat m en t for agin g d egr a da t i on or any othe r appropri ate meas u r es . Bec a use the eval ua t i on of micr o c o m pu t e r s oft war e al on e i s v ery difficult ,

please ev al ua te the s a fet y of the f i nal pr o duc ts or s y stem s m a nu f a c tured by you.

8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics

produc ts in c om p li an ce w i t h al l appl icable laws a nd r eg ul ations that r egu la te the i nc l usion or use of c o ntrolle d s ubs tance s , including without limitation, the EU RoHS Directive. Renesas Electronics assumes

no liability for dam ag es o r losses oc c u r ring as a r e s ult of y ou r non c ompliance with applicable laws a nd r eg ul ations .

9. Renesas E l ec troni c s p r o duc ts and techno lo gy m a y no t be used for or incorporated into any products or s yst em s whose m an ufact u re, us e , or sal e i s pr oh ib ited under an y appl icable dom e stic or f o r ei gn l aws o r

regulations . You should not use R enes a s E le c troni cs produc ts or techn olo gy describ ed in this do c ument for any pu r pose relating to military applications or use by the military, including but not limited to the

development of weapons of mass destruction. W hen exporting the Renesas Electronics products or technology described in this document , you s h oul d c omply wi t h t h e ap pl ic ab le e x po r t control laws an d

regulations and follow the procedures required by such laws and regulations.

10. It is t he responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places t he pr od uct with a th ir d par ty, to no t i fy su c h third pa r ty in adv a nc e of the

contents and conditions set forth in this document, Renesas Electronics assumes no responsibility f or any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics

products.

11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.

12. Please contact a Renesas Electronics sales office if you have any questions regarding the informat ion contained in this document or R enes a s E lectr o ni c s p r o duc ts, or if y o u ha v e a ny other in qu ir i es .

(Not e 1) " Re nesas El ec tronics" as u s ed in t h is d oc um en t means R en es as Electronic s Corpor a t i on and al s o i nc lud es its m aj or i ty- own e d s u bs id ia r ies.

(Not e 2) " Re nesas El ec tronics prod uct( s ) " mean s an y pr od uct dev e lope d or manufactured by or for Ren es a s E le c tronic s.

http://www.renesas.com

Refer to "http://www.renesas.com/" for the latest and detailed information.

Renesas Electronics America Inc.

2801 Scott Boulevard Santa Clara, CA 95050-2549, U.S.A.

Tel: +1-408-588-6000, Fax: +1-408-588-6130

Renesas Electronics Canada Limited

9251 Yonge Street, Suite 8309 Richmond Hill, Ontario Canada L4C 9T3

Tel: +1-905-237-2004

Renesas El e ctronics E ur ope Limited

Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K

Tel: +44-1628-585-100, Fax: +44-1628-585-900

Renesas El e ctronics Eur ope G m bH

Arcadiastrasse 10, 40472 Düsseldorf, Germany

Tel: +49-211-6503-0, Fax: +49-211-6503-1327

Renesas El e ctronics (China) Co., Ltd.

Room 1709, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100191, P.R.China

Tel: +86-10-8235-1155, Fax: +86-10-8235-7679

Renesas El e ctronics (Sha ngha i ) Co., Ltd.

Unit 301, Tower A, Central Towers, 555 Langao Road, Putuo District, Shanghai, P. R. China 200333

Tel: +86-21-2226-0888, Fax: +86-21-2226-0999

Renesas Ele ctronics Hong Kong Limited

Unit 1601-1611, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong

Tel: +852-2265-6688, Fax: +852 2886-9022

Renesas El e ctronics Taiwan Co., Ltd.

13F, No. 363, Fu Shing North Road, Taipei 10543, Taiwan

Tel: +886-2-8175-9600, Fax: +886 2-8175-9670

Renesas Electronics Singapore Pte. Ltd.

80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre, Singapore 339949

Tel: +65-6213-0200, Fax: +65-6213-0300

Renesas El e ctronics Ma lays i a Sdn.Bhd.

Unit 1207, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia

Tel: +60-3-7955-9390, Fax: +60-3-7955-9510

Renesas El e ctronics Indi a Pvt. Ltd.

No.777C, 100 Feet Road, HALII Stage, Indiranagar, Bangalore, India

Tel: +91-80-67208700, Fax: +91-80-67208777

Renesas Electronics Korea Co., Ltd.

12F., 234 Teheran-ro, Gangnam-Gu, Seoul, 135-080, Korea

Tel: +82-2-558-3737, Fax: +82-2-558-5141

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