FEATURES
APPLICATIONS
DESCRIPTION
ADS5500 PRODUCT FAMILY
ADS5542
SBAS308D – MAY 2004 – REVISED FEBRUARY 2007
14-Bit, 80 MSPSAnalog-To-Digital Converter
•TQFP-64 PowerPAD™ Package•14-Bit Resolution •Recommended Amplifiers:OPA695, OPA847, THS3201, THS3202,•80 MSPS Sample Rate
THS4503, THS4509, THS9001•High SNR: 72.9 dBFS at 100 MHz f
IN•High SFDR: 88 dBc at 100 MHz f
IN•2.3-V
PP
Differential Input Voltage
•Wireless Communication•Internal Voltage Reference
– Communication Receivers•3.3-V Single-Supply Voltage
– Base Station Infrastructure•Analog Power Dissipation: 545 mW
•Test and Measurement Instrumentation•Single and Multichannel Digital Receivers•Serial Programming Interface
•Communication Instrumentation– Radar, Infrared•Video and Imaging•Medical Equipment
The ADS5542 is a high-performance, 14-bit, 80 MSPS analog-to-digital converter (ADC). To provide a completeconverter solution, it includes a high-bandwidth linear sample-and-hold stage (S&H) and internal reference.Designed for applications demanding the highest speed and highest dynamic performance in little space, theADS5542 has excellent power consumption of 545 mW at 3.3-V single-supply voltage. This allows an evenhigher system integration density. The provided internal reference simplifies system design requirements.Parallel CMOS-compatible output ensures seamless interfacing with common logic.
The ADS5542 is available in a 64-pin TQFP PowerPAD package over the industrial temperature range -40 °C to85 °C.
80 MSPS 105 MSPS 125 MSPS
12 Bit ADS5522 ADS5521 ADS554214 Bit ADS5542 ADS5541 ADS5500
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004–2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
www.ti.com
.
.
.
ADS5542
Serial Programming Register
Control Logic
Timing Circuitry
Internal
Reference
Output
Control
CLKOUT
CLK+
CLK−
VIN+
VIN−
CM
AVDD DRVDD
OVR
DFS
Digital
Error
Correction
14-Bit
Pipeline
ADC
Core
S&H
AGND DRGND
SCLKSDATASEN
D0
D13
ABSOLUTE MAXIMUM RATINGS
ADS5542
SBAS308D – MAY 2004 – REVISED FEBRUARY 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may bemore susceptible to damage because very small parametric changes could cause the device not to meet its publishedspecifications.
ORDERING INFORMATION
(1)
SPECIFIEDPACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORTPRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY
ADS5542IPAP Tray, 160HTQFP-64
(2)ADS5542 PAP –40 °C to 85 °C ADS5542IPowerPAD
ADS5542IPAPR Tape and Reel, 1000
(1) For the most current product and ordering information, see the Package Option Addendum at the end of this data sheet.(2) Thermal pad size: 3,5 mm ×3,5 mm (min), 4 mm x 4 mm (max). θ
JA
= 21.47 °C/W and θ
JC
= 2.99 °C/W, when used with 2 oz. coppertrace and pad soldered directly to a JEDEC standard, four-layer, 3 in ×3 in PCB.
over operating free-air temperature range (unless otherwise noted)
(1)
ADS5500 UNIT
AV
DD
to A
GND
, DRV
DD
to DR
GND
–0.3 to 3.7 VSupply Voltage
A
GND
to DR
GND
±0.1 VAnalog input to A
GND
(2) (3)
–0.3 to minimum (AV
DD
+ 0.3, 3.6) VLogic input to DR
GND
–0.3 to DRV
DD
VDigital data output to DR
GND
–0.3 to DRV
DD
VOperating temperature range –40 to 85 °CJunction temperature 105 °CStorage temperature range –65 to 150 °C
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods maydegrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyondthose specified is not implied.(2) If the input signal can exceed 3.6 V, then a resistor greater than or equal to 25 Ωshould be added in series with each of the analoginput pins to support input voltages up to 3.8 V. For input voltages above 3.8 V, the device can only handle transients and the duty cycleof the overshoot should be limited to less than 5% for inputs up to 3.9 V.(3) The overshoot duty cycle can be defined as the ratio of the total time of overshoot to the total intended device lifetime, expressed as apercentage. The total time of overshoot is the integrated time of all overshoot occurences over the lifetime of the device.
2
Submit Documentation Feedback
www.ti.com
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
ADS5542
SBAS308D – MAY 2004 – REVISED FEBRUARY 2007
MIN TYP MAX UNIT
SUPPLIES
Analog supply voltage, AV
DD
3 3.3 3.6 V
Output driver supply voltage, DRV
DD
3 3.3 3.6 V
ANALOG INPUT
Differential input range 2.3 V
PP
Input common-mode voltage, V
CM
(1)
1.45 1.55 1.65 V
DIGITAL OUTPUT
Maximum output load 10 pF
CLOCK INPUT
ADCLK input sample rate (sine wave) 1/t
C
2 80 MSPS
Clock amplitude, sine wave, differential
(2)
1 3 V
PP
Clock duty cycle
(3)
50%
Open free-air temperature range –40 85 °C
(1) Input common-mode should be connected to CM.(2) See Figure 47 for more information.(3) See Figure 46 for more information.
Typical values given at T
A
= 25 °C, min and max specified over the full recommended operating temperature range, AV
DD
=DRV
DD
= 3.3 V, sampling rate = 80 MSPS, 50% clock duty cycle, 3-V
PP
differential clock, and –1dBFS differential input,unless otherwise noted
PARAMETER CONDITIONS MIN TYP MAX UNIT
Resolution 12 Bits
Analog Inputs
Differential input range 2.3 V
PP
Differential input impedance See Figure 37 6.6 k ΩDifferential input capacitance See Figure 37 4 pFAnalog input common-mode current (per
200 µAinput)
Analog input bandwidth Source impedance = 50 Ω750 MHzVoltage overload recovery time 4 Clock cycles
Internal Reference Voltages
Reference bottom voltage, V
REFM
1.0 VReference top voltage, V
REFP
2.15 VReference error –4% ±0.6% 4%Common-mode voltage output, V
CM
1.55 ±0.05 V
Dynamic DC Characteristics and Accuracy
No missing codes AssuredDifferential nonlinearity error, DNL f
IN
= 10 MHz -0.9 0.5 1.1 LSBIntegral nonlinearity error, INL f
IN
= 10 MHz –5 ±2 5 LSBOffset error -11 ±1.5 11 mVOffset temperature coefficient 0.02 mV/ °C∆offset error/ ∆AV
DD
from AV
DD
= 3 V toDC power-supply rejection ratio, DC PSRR 0.25 mV/VAV
DD
= 3.6 VGain error
(1)
-2 0.3 2 %FSGain temperature coefficient –0.02 ∆%/ °C
(1) Gain error is specified by design and characterization; it is not tested in production.
3Submit Documentation Feedback
www.ti.com
ADS5542
SBAS308D – MAY 2004 – REVISED FEBRUARY 2007
ELECTRICAL CHARACTERISTICS (continued)Typical values given at T
A
= 25 °C, min and max specified over the full recommended operating temperature range, AV
DD
=DRV
DD
= 3.3 V, sampling rate = 80 MSPS, 50% clock duty cycle, 3-V
PP
differential clock, and –1dBFS differential input,unless otherwise noted
PARAMETER CONDITIONS MIN TYP MAX UNIT
Dynamic AC Characteristics
25 °C to 85 °C 72.7 74.3f
IN
= 10 MHz
Full temp range 71.5 74.0f
IN
= 55 MHz 73.725 °C to 85 °C 71.5 73.5Signal-to-noise ratio, SNR f
IN
= 70 MHz dBFSFull temp range 70.0 73f
IN
= 100 MHz 72.9f
IN
= 150 MHz 71.9f
IN
= 220 MHz 70.7RMS output noise Input tied to common-mode 1.1 LSB25 °C 80 92f
IN
= 10 MHz
Full temp range 78 90f
IN
= 55 MHz 8825 °C 80 87Spurious-free dynamic range, SFDR f
IN
= 70 MHz dBcFull temp range 78 86f
IN
= 100 MHz 88f
IN
= 150 MHz 85f
IN
= 220 MHz 7725 °C 80 92f
IN
= 10 MHz
Full temp range 78 90f
IN
= 55 MHz 8825 °C 80 87Second-harmonic, HD2 f
IN
= 70 MHz dBcFull temp range 78 86f
IN
= 100 MHz 88f
IN
= 150 MHz 85f
IN
= 220 MHz 7725 °C 80 89f
IN
= 10 MHz
Full temp range 78 88f
IN
= 55 MHz 7925 °C 80 85Third-harmonic, HD3 f
IN
= 70 MHz dBcFull temp range 78 83f
IN
= 100 MHz 83f
IN
= 150 MHz 80f
IN
= 220 MHz 76f
IN
= 10 MHz 25 °C 88Worst-harmonic/spur (other than HD2 and
dBcHD3)
f
IN
= 70 MHz 25 °C 8725 °C to 85 °C 72.2 73.8f
IN
= 10 MHz
Full temp range 71 73.5f
IN
= 55 MHz 73.225 °C to 85 °C 71 73.2Signal-to-noise + distortion, SINAD f
IN
= 70 MHz dBFSFull temp range 69.5 72.5f
IN
= 100 MHz 72.5f
IN
= 150 MHz 71.8f
IN
= 220 MHz 69.8
4
Submit Documentation Feedback
www.ti.com
DIGITAL CHARACTERISTICS
ADS5542
SBAS308D – MAY 2004 – REVISED FEBRUARY 2007
ELECTRICAL CHARACTERISTICS (continued)Typical values given at T
A
= 25 °C, min and max specified over the full recommended operating temperature range, AV
DD
=DRV
DD
= 3.3 V, sampling rate = 80 MSPS, 50% clock duty cycle, 3-V
PP
differential clock, and –1dBFS differential input,unless otherwise noted
PARAMETER CONDITIONS MIN TYP MAX UNIT
25 °C 78 90f
IN
= 10 MHz
Full temp range 76 88f
IN
= 55 MHz 83.425 °C 78 86Total harmonic distortion, THD f
IN
= 70 MHz dBcFull temp range 76 84f
IN
= 100 MHz 83.4f
IN
= 150 MHz 81.2f
IN
= 220 MHz 75.8Effective number of bits, ENOB f
IN
= 70 MHz 11.9 Bitsf = 10.1 MHz, 15.1 MHz (–7dBFS each tone) 93.8f = 50.1 MHz, 55.1 MHz (–7dBFS each tone) 92.4Two-tone intermodulation distortion, IMD dBFSf = 148.1 MHz, 153.1 MHz (–7dBFS each
92.6tone)AC power supply rejection ratio, ACPSRR Supply noise frequency ≤100 MHz 35 dB
Power Supply
Total supply current, I
CC
f
IN
= 70 MHz 204 230 mAAnalog supply current, IAV
DD
f
IN
= 70 MHz 165 180 mAOutput buffer supply current, IDRV
DD
f
IN
= 70 MHz 39 50 mAAnalog only 545 594Power dissipation mWOutput buffer power with 10-pF load on
129 165digital output to groundStandby power With Clocks running 180 250 mW
Valid over full recommended operating temperature range, AV
DD
= DRV
DD
= 3.3 V, unless otherwise noted
PARAMETER CONDITIONS MIN TYP MAX UNIT
Digital Inputs
V
IH
High-level input voltage 2.4 VV
IL
Low-level input voltage 0.8 VI
IH
High-level input current 10 µAI
IL
Low-level input current –10 µAInput current for RESET –20 µAInput capacitance 4 pF
Digital Outputs
V
OL
Low-level output voltage C
LOAD
= 10 pF 0.3 0.4 VV
OH
High-level output voltage C
LOAD
= 10 pF 2.4 3 VOutput capacitance 3 pF
5Submit Documentation Feedback
www.ti.com
TIMING CHARACTERISTICS
(1) (2)
Input Clock
Analog
Input
Signal
Sample
NN + 1 N + 2 N + 3 N + 4
N + 14 N + 16 N + 17
N + 15
N − 17 N − 16 N − 15 N − 14 N − 13 N − 3 N − 2 N − 1 N
tsu
th
tSTART
tA
tEND
tPDI
Data Out
(D0−D11)
17.5 Clock Cycles
Data Invalid
Output Clock
ADS5542
SBAS308D – MAY 2004 – REVISED FEBRUARY 2007
Typical values given at T
A
= 25 °C, min and max specified over the full recommended operating temperature range, AV
DD
=DRV
DD
= 3.3 V, sampling rate = 80 MSPS, 50% clock duty cycle, 3-V
PP
differential clock, and C
LOAD
= 10 pF, unlessotherwise noted
PARAMETER DESCRIPTION MIN TYP MAX UNIT
Switching Specification
t
A
Aperture delay Input CLK falling edge to data sampling point 1 nsAperture jitter (uncertainty) Uncertainty in sampling instant 300 fst
SETUP
Data setup time Data valid
(3)
to 50% of CLKOUT rising edge 3.2 4.2 nst
HOLD
Data hold time 50% of CLKOUT rising edge to data becoming invalid
(3)
1.8 3.0 nst
START
Input clock to output data valid Input clock rising edge to data valid start delay 3.8 5.0 nsstart
(4) (5)
t
END
Input clock to output data valid Input clock rising edge to data valid end delay
(4) (5)
8.4 11.0 nsendt
JIT
Output clock jitter Uncertainty in CLKOUT rising edge, peak-to-peak 210 315 ps
PP
t
r
Output clock rise time Rise time of CLKOUT from 20% to 80% of DRV
DD
2.5 2.8 nst
f
Output clock fall time Fall time of CLKOUT from 80% to 20% of DRV
DD
2.1 2.3 nst
PDI
Input clock to output clock Input clock rising edge, zero crossing, to output clock rising 7.1 8.0 8.9 nsdelay edge 50%t
r
Data rise time Data rise time measured from 20% to 80% of DRV
DD
5.8 6.6 nst
f
Data fall time Data fall time measured from 80% to 20% of DRV
DD
4.4 5.3 nsOutput enable(OE) to data Time required for outputs to have stable timings with regard to 1000 Clockoutput delay input clock
(6)
after OE is activated cyclesTime to valid data after coming out of software power down 1000
ClockWakeup time
cyclesTime to valid data after stopping and restarting the clock 1000Latency Time for a sample to propagate to the ADC outputs 17.5 Clock
cycles
(1) Timing parameters are ensured by design and characterization, and not tested in production.(2) See Table 5 through Table 6 in the Application Information section for timing information at additional sampling frequencies.(3) Data valid refers to 2 V for LOGIC HIGH and 0.8 V for LOGIC LOW.(4) See the Output Information section for details on using the input clock for data capture.(5) These specifications apply when the CLKOUT polarity is set to rising edge (according to Table 2 ). Add 1/2 clock period for the validnumber for a falling edge CLKOUT polarity.(6) Data outputs are available within a clock from assertion of OE; however, it takes 1000 clock cycles to ensure stable timing with respectto input clock.
A. It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the abovetiming matches closely with the specified values.
Figure 1. Timing Diagram
6
Submit Documentation Feedback
www.ti.com
RESET TIMING CHARACTERISTICS
RESET (Pin 35)
t1 10 ms
t2 2 ms t3 2 msSEN Active
Power Supply
(AVDD, DRVDD)
SERIAL PROGRAMMING INTERFACE CHARACTERISTICS
A3
ADDRESS
SDATA
MSB
DATA
A2 A1 A0 D11 D10 D9 D0
ADS5542
SBAS308D – MAY 2004 – REVISED FEBRUARY 2007
Typical values given at T
A
= 25 °C, min and max specified over the full recommended operating temperature range, AV
DD
=DRV
DD
= 3.3 V, and 3-V
PP
differential clock, unless otherwise noted
PARAMETER DESCRIPTION MIN TYP MAX UNIT
Switching Specification
t
1
Power-on delay Delay from power-on of AV
DD
and DRV
DD
to RESET pulse 10 msactivet
2
Reset pulse width Pulse width of active RESET signal 2 µst
3
Register write delay Delay from RESET disable to SEN active 2 µsPower-up time Delay from power-up of AV
DD
and DRV
DD
to output stable 40 ms
Figure 2. Reset Timing Diagram
The ADS5542 has a three-wire serial interface. The ADS5542 latches serial data SDATA on the falling edge ofserial clock SCLK when SEN is active.•Serial shift of bits is enabled when SEN is low. SCLK shifts serial data at the falling edge.•Minimum width of data stream for a valid loading is 16 clocks.•Data is loaded at every 16th SCLK falling edge while SEN is low.•In case the word length exceeds a multiple of 16 bits, the excess bits are ignored.•Data can be loaded in multiples of 16-bit words within a single active SEN pulse.•The first 4-bit nibble is the address of the register while the last 12 bits are the register contents.
Figure 3. DATA Communication is 2-Byte, MSB First
7Submit Documentation Feedback
www.ti.com
16 x M
MSB LSB LSBMSB
SCLK
SEN
SDATA
tSLOADS tSLOADH
tSCLK
tWSCLK
tWSCLK
tsu(D) th(D)
VDFS t2
12 AVDD
4
12 AVDD tVDFS t5
12 AVDD
7
12 AVDD tVDFS t8
12 AVDD
VDFS u10
12 AVDD
ADS5542
SBAS308D – MAY 2004 – REVISED FEBRUARY 2007
Figure 4. Serial Programming Interface Timing Diagram
Table 1. Serial Programming Interface Timing Characteristics
SYMBOL PARAMETER MIN
(1)
TYP
(1)
MAX
(1)
UNIT
t
SCLK
SCLK period 50 nst
WSCLK
SCLK duty cycle 25% 50% 75%t
SLOADS
SEN to SCLK setup time 8 nst
SLOADH
SCLK to SEN hold time 6 nst
DS
Data setup time 8 nst
DH
Data hold time 6 ns
(1) Min, typ, and max values are characterized, but not production tested.
Table 2. Serial Register Table
(1)
A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DESCRIPTION
TP<1> TP<0> Test Mode
1 1 1 0 0 0 0 0 0 0 0 0 0 0 X 0 Normal mode of operation
1 1 1 0 0 0 1 0 0 0 0 0 0 0 X 0 All outputs forced to 0
1 1 1 0 0 1 0 0 0 0 0 0 0 0 X 0 All outputs forced to 1
1 1 1 0 0 1 1 0 0 0 0 0 0 0 X 0 Each output bit toggles between 0 and 1.
(2) (3)
PDN Power Down
1 1 1 1 0 0 0 0 0 0 0 0 0 0 X 0 Normal mode of operation
1 1 1 1 1 0 0 0 0 0 0 0 0 0 X 0 Device is put in power-down (low-current) mode.
(1) The register contents default to the appropriate setting for normal operation up on RESET.(2) The patterns given are applicable to the straight offset binary output format. If two's complement output format is selected, the test modeoutputs will be the binary two's complement equivalent of these patterns as described in the Output Information section.(3) While each bit toggles between 1 and 0 in this mode, there is no assured phase relationship between the data bits D0 through D13. Forexample, when D0 is a 1, D1 in not assured to be a 0, and vice versa.
Table 3. Data Format Select (DFS) Table
DFS-PIN VOLTAGE (V
DFS
) DATA FORMAT CLOCK OUTPUT POLARITY
Straight Binary Data valid on rising edge
Two's Complement Data valid on rising edge
Straight Binary Data valid on falling edge
Two's Complement Data valid on falling edge
8
Submit Documentation Feedback
www.ti.com
PIN CONFIGURATION
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DRGND
D3
D2
D1
D0 (LSB)
CLKOUT
DRGND
OE
DFS
AVDD
AGND
AVDD
AGND
RESET
AVDD
AVDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DRGND
SCLK
SDATA
SEN
AVDD
AGND
AVDD
AGND
AVDD
CLKP
CLKM
AGND
AGND
AGND
AVDD
AGND
OVR
D13 (MSB)
D12
D11
D10
DRGND
DRVDD
DRGND
D9
D8
D7
D6
D5
D4
DRGND
DRVDD
CM
AGND
INP
INM
AGND
AVDD
AGND
AVDD
AGND
AVDD
AGND
AVDD
REFP
REFM
IREF
AGND
64 63 62 61 60 59 58 57 56 55 54
17 18 19 20 21 22 23 24 25 26 27
53 52 51 50 49
28 29 30 31 32
ADS5542
PowerPAD
ADS5542
SBAS308D – MAY 2004 – REVISED FEBRUARY 2007
PAP PACKAGE
(TOP VIEW)
9Submit Documentation Feedback
www.ti.com
ADS5542
SBAS308D – MAY 2004 – REVISED FEBRUARY 2007
PIN CONFIGURATION (continued)PIN ASSIGNMENTS
TERMINAL
NO. OFNAME NO. PINS I/O DESCRIPTION
5, 7, 9, 15, 22,AV
DD
24, 26, 28, 33, 12 I Analog power supply34, 37, 396, 8, 12–14,
16, 18, 21, 23,A
GND
14 I Analog ground (PowerPAD is connected to analog ground.)25, 27, 32, 36,38DRV
DD
49, 58 2 I Output driver power supply1, 42, 48, 50,DR
GND
6 I Output driver ground57, 59INP 19 1 I Differential analog input (positive)INM 20 1 I Differential analog input (negative)REFP 29 1 O Reference voltage (positive); 1- µF capacitor in series with a 1- Ωresistor to GNDREFM 30 1 O Reference voltage (negative); 1- µF capacitor in series with a 1- Ωresistor to GNDIREF 31 1 I Current set; 56.2-k Ωresistor to GND; do not connect capacitorsCM 17 1 O Common-mode output voltageRESET 35 1 I Reset (active high), Internal 200-k Ωresistor to AV
DD
(1)
OE 41 1 I Output enable (active high)
(2)
DFS 40 1 I Data format and clock out polarity select
(3) (2)
CLKP 10 1 I Data converter differential input clock (positive)CLKM 11 1 I Data converter differential input clock (negative)SEN 4 1 I Serial interface chip select
(2)
SDATA 3 1 I Serial interface data
(2)
SCLK 2 1 I Serial interface clock
(2)
D0 (LSB) to 44-47, 51-56,
14 O Parallel data outputD13 (MSB) 60-63OVR 64 1 O Over-range indicator bitCLKOUT 43 1 O CMOS clock out in sync with data
(1) If unused, the RESET pin should be tied to AGND. See the serial programmine interface section for details.(2) Pins OE, DFS, SEN, SDATA, and SCLK have internal clamping diodes to the DRVDD supply. Any external circuit driving these pinsmust also run off the same supply voltage as DRVDD.(3) Table 3 defines the voltage levels for each mode selectable via the DFS pin.
10
Submit Documentation Feedback
www.ti.com
DEFINITION OF SPECIFICATIONS
SNR +10Log10 PS
PN
SINAD +10Log10 PS
PN)PD
(1)
ENOB +SINAD *1.76
6.02
ADS5542
SBAS308D – MAY 2004 – REVISED FEBRUARY 2007
Offset ErrorAnalog Bandwidth
The offset error is the difference, given in number ofThe analog input frequency at which the power of the
LSBs, between the ADC's actual average idlefundamental is reduced by 3 dB with respect to the
channel output code and the ideal average idlelow frequency value.
channel output code. This quantity is often mappedinto mV.Aperture Delay
Temperature DriftThe delay in time between the falling edge of theinput sampling clock and the actual time at which the
The temperature drift coefficient (with respect to gainsampling occurs.
error and offset error) specifies the change perdegree Celsius of the parameter from T
MIN
to T
MAX
. ItAperture Uncertainty (Jitter)
is calculated by dividing the maximum deviation ofThe sample-to-sample variation in aperture delay.
the parameter across the T
MIN
to T
MAX
range by thedifference (T
MAX
– T
MIN
).Clock Pulse Width/Duty Cycle
Signal-to-Noise Ratio (SNR)The duty cycle of a clock signal is the ratio of thetime the clock signal remains at a logic high (clock
SNR is the ratio of the power of the fundamental (P
S
)pulse width) to the period of the clock signal. Duty
to the noise floor power (P
N
), excluding the power atcycle is typically expressed as a percentage. A
dc and the first eight harmonics.perfect differential sine wave clock results in a 50%duty cycle.
Maximum Conversion Rate
SNR is either given in units of dBc (dB to carrier)The maximum sampling rate at which certified
when the absolute power of the fundamental is usedoperation is given. All parametric testing is performed
as the reference or dBFS (dB to Full-Scale) when theat this sampling rate unless otherwise noted.
power of the fundamental is extrapolated to theconverter's full-scale range.Minimum Conversion Rate
Signal-to-Noise and Distortion (SINAD)The minimum sampling rate at which the ADCfunctions.
SINAD is the ratio of the power of the fundamental(P
S
) to the power of all the other spectralDifferential Nonlinearity (DNL)
components including noise (P
N
) and distortion (P
D
),An ideal ADC exhibits code transitions at analog
but excluding dc.input values spaced exactly 1LSB apart. The DNL isthe deviation of any single step from this ideal value,measured in units of LSBs.
Integral Nonlinearity (INL)
SINAD is either given in units of dBc (dB to carrier)when the absolute power of the fundamental is usedThe INL is the deviation of the ADC's transfer
as the reference or dBFS (dB to full-scale) when thefunction from a best fit line determined by a least
power of the fundamental is extrapolated to thesquares curve fit of that transfer function, measured
converter's full-scale range.in units of LSBs.
Effective Number of Bits (ENOB)Gain Error
The ENOB is a measure of a converter'sThe gain error is the deviation of the ADC's actual
performance as compared to the theoretical limitinput full-scale range from its ideal value. The gain
based on quantization noise.error is given as a percentage of the ideal inputfull-scale range. Gain error does not account forvariations in the internal reference voltages (see theElectrical Specifications section for limits on thevariation of V
REFP
and V
REFM
).
11Submit Documentation Feedback
www.ti.com
THD +10Log10 PS
PD
ADS5542
SBAS308D – MAY 2004 – REVISED FEBRUARY 2007
Total Harmonic Distortion (THD) Two-Tone Intermodulation Distortion (IMD3)
THD is the ratio of the power of the fundamental (P
S
) IMD3 is the ratio of the power of the fundamental (atto the power of the first eight harmonics (P
D
). frequencies f
1
and f
2
) to the power of the worstspectral component at either frequency 2f
1
– f
2
or2f
2
– f
1
. IMD3 is either given in units of dBc (dB tocarrier) when the absolute power of the fundamentalis used as the reference, or dBFS (dB to Full-Scale)THD is typically given in units of dBc (dB to carrier).
when the power of the fundamental is extrapolated toSpurious-Free Dynamic Range (SFDR)
the converter's full-scale range.The ratio of the power of the fundamental to the
DC Power Supply Rejection Ration (DC PSRR)highest other spectral component (either spur or
The DC PSSR is the ratio of the change in offsetharmonic). SFDR is typically given in units of dBc
error to a change in analog supply voltage. The DC(dB to carrier).
PSRR is typically given in units of mV/V.
Reference Error
The reference error is the variation of the actualreference voltage (VREFP - VREFM) from its idealvalue. The reference error is typically given as apercentage.
Voltage Overload Recovery Time
The voltage overload recovery time is defined as thetime required for the ADC to recover to within 1% ofthe full-scale range in response to an input voltageoverload of 10% beyond the full-scale range.
12
Submit Documentation Feedback
www.ti.com
TYPICAL CHARACTERISTICS
0
−20
−40
−60
−80
−100
−120
Magnitude −dB
f−Frequency −MHz
0 5 15 25 3510 20 30 40
SFDR = 92.1dBc
SNR = 74.0dBFS
THD = 88.4dBc
SINAD = 73.9dBFS
0
−20
−40
−60
−80
−100
−120 0 5 15 25 3510 20 30 40
SFDR = 92.0dBc
SNR = 73.6dBFS
THD = 88.2dBc
SINAD = 73.5dBFS
Magnitude −dB
f−Frequency −MHz
0
−20
−40
−60
−80
−100
−120 0 5 15 25 3510 20 30 40
SFDR = 87.5dBc
SNR = 73.6dBFS
THD = 83.4dBc
SINAD = 73.2dBFS
Magnitude −dB
f−Frequency −MHz
0
−20
−40
−60
−80
−100
−120
Magnitude −dB
f−Frequency −MHz
0 5 15 25 3510 20 30 40
SFDR = 89.3dBc
SNR = 73.4dBFS
THD = 86.8dBc
SINAD = 73.2dBFS
0
−20
−40
−60
−80
−100
−120 0 5 15 25 3510 20 30 40
SFDR = 87.2dBc
SNR = 72.8dBFS
THD = 83.4dBc
SINAD = 72.5dBFS
Magnitude −dB
f−Frequency −MHz
0
−20
−40
−60
−80
−100
−120 0 5 15 25 3510 20 30 40
SFDR = 83.9dBc
SNR = 72.7dBFS
THD = 81.5dBc
SINAD = 72.2dBFS
Magnitude −dB
f−Frequency −MHz
ADS5542
SBAS308D – MAY 2004 – REVISED FEBRUARY 2007
Typical values given at T
A
= 25 °C, AV
DD
= DRV
DD
= 3.3 V, differential input amplitude = –1dBFS, sampling rate = 80 MSPSand 3-V differential clock, unless otherwise noted
SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE(FFT for 4 MHz Input Signal) (FFT for 16 MHz Input Signal)
Figure 5. Figure 6.
SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE(FFT for 55 MHz Input Signal) (FFT for 70 MHz Input Signal)
Figure 7. Figure 8.
SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE(FFT for 100 MHz Input Signal) (FFT for 125 MHz Input Signal)
Figure 9. Figure 10.
13Submit Documentation Feedback
www.ti.com
0
−20
−40
−60
−80
−100
−120 0 5 15 25 3510 20 30 40
SFDR = 88.6dBc
SNR = 71.9dBFS
THD = 81.2dBc
SINAD = 71.8dBFS
Magnitude −dB
f−Frequency −MHz
0
−20
−40
−60
−80
−100
−120 0 5 15 25 3510 20 30 40
SFDR = 78.4dBc
SNR = 70.7dBFS
THD = 75.8dBc
SINAD = 69.8dBFS
Magnitude −dB
f−Frequency −MHz
0
−20
−40
−60
−80
−100
−120 0 5 15 25 3510 20 30 40
SFDR = 68.4dBc
SNR = 68.5dBFS
THD = 68.2dBc
SINAD = 65.8dBFS
Magnitude −dB
f−Frequency −MHz
0
−20
−40
−60
−80
−100
−120 0 5 15 25 3510 20 30 40
f1 = 10.1MHz (−7dBFS)
f2 = 15.1MHz (−7dBFS)
2−Tone SFDR = 92.8dBc
Magnitude −dB
f−Frequency −MHz
0
−20
−40
−60
−80
−100
−120 0 5 15 25 3510 20 30 40
f1 = 45.1MHz (−7dBFS)
f2 = 50.1MHz (−7dBFS)
2−Tone SFDR = 91.6dBc
Magnitude −dB
f−Frequency −MHz
0
−20
−40
−60
−80
−100
−120 0 5 15 25 3510 20 30 40
f1 = 50.1MHz (−7dBFS)
f2 = 55.1MHz (−7dBFS)
2−Tone SFDR = 91.4dBc
Magnitude −dB
f−Frequency −MHz
ADS5542
SBAS308D – MAY 2004 – REVISED FEBRUARY 2007
TYPICAL CHARACTERISTICS (continued)Typical values given at T
A
= 25 °C, AV
DD
= DRV
DD
= 3.3 V, differential input amplitude = –1dBFS, sampling rate = 80 MSPSand 3-V differential clock, unless otherwise noted
SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE(FFT for 150 MHz Input Signal) (FFT for 220 MHz Input Signal)
Figure 11. Figure 12.
SPECTRAL PERFORMANCE
(FFT for 300 MHz Input Signal) TWO-TONE INTERMODULATION
Figure 13. Figure 14.
TWO-TONE INTERMODULATION TWO-TONE INTERMODULATION
Figure 15. Figure 16.
14
Submit Documentation Feedback
www.ti.com
1.0
0.8
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
−1.0
DNL −LSB
Code
0 2048 4096 6144 12288 143368192 10240 16384
fIN = 10MHz
AIN =−0.5dBFS
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
INL −LSB
Code
0 2048 4096 6144 12288 143368192 10240 16384
fIN = 10MHz
AIN =−0.5dBFS
100
95
90
85
80
75
70
65
60 0 50 100 150 200 250 300
Frequency −MHz
SFDR −dBc
76
75
74
73
72
71
70
69
68
67 0 50 100 150 200 250 300
Frequency −MHz
SNR −dBFS
100
95
90
85
80
72
70
65
60 3.0 3.1 3.2 3.3 3.4 3.5 3.6
fIN = 150MHz
SFDR
SNR
AVDD −Analog Supply Voltage −V
SFDR −dBcSNR −dBFS
98
94
90
86
82
48
74
70
66
AVDD −Analog Supply Voltage −V
3.0 3.1 3.2 3.3 3.4 3.5 3.6
fIN = 70MHz
SFDR
SNR
SFDR −dBcSNR −dBFS
ADS5542
SBAS308D – MAY 2004 – REVISED FEBRUARY 2007
TYPICAL CHARACTERISTICS (continued)Typical values given at T
A
= 25 °C, AV
DD
= DRV
DD
= 3.3 V, differential input amplitude = –1dBFS, sampling rate = 80 MSPSand 3-V differential clock, unless otherwise noted
DIFFERENTIAL NONLINEARITY INTEGRAL NONLINEARITY
Figure 17. Figure 18.
SPURIOUS-FREE DYNAMIC RANGE SIGNAL-TO-NOISE RATIOvs INPUT FREQUENCY vs INPUT FREQUENCY
Figure 19. Figure 20.
AC PERFORMANCE AC PERFORMANCEvs ANALOG SUPPLY VOLTAGE vs ANALOG SUPPLY VOLTAGE
Figure 21. Figure 22.
15Submit Documentation Feedback
www.ti.com
95
90
85
80
75
70
65
DVDD −Digital Supply Voltage −V
3.0 3.1 3.2 3.3 3.4 3.5 3.6
fIN = 150MHz
SFDR
SNR
SFDR −dBcSNR −dBFS
95
90
85
80
75
70
65
SFDR −dBcSNR −dBFS
DVDD −Digital Supply Voltage −V
3.0 3.1 3.2 3.3 3.4 3.5 3.6
fIN = 70MHz
SFDR
SNR
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
Power Dissipation −W
Sample Rate −MSPS
10 20 30 40 50 60 70 80
fIN = 150MHz
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
Power Dissipation −W
Sample Rate −MSPS
10 20 30 40 50 60 70 80
fIN = 70MHz
100
95
90
85
80
75
70
65
60−40 −15 +85+60+35+10
Temperature −_C
SNR −dBFS SFDR −dBc
fIN = 70MHz
SFDR
SNR
100
90
80
70
60
50
40
30
20
10
0
−10
−20
−30
AC Performance −dB
Input Amplitude −dBFS
−100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0
fIN = 70MHz
SFDR (dBc)
SNR (dBc)
SNR (dBFS)
ADS5542
SBAS308D – MAY 2004 – REVISED FEBRUARY 2007
TYPICAL CHARACTERISTICS (continued)Typical values given at T
A
= 25 °C, AV
DD
= DRV
DD
= 3.3 V, differential input amplitude = –1dBFS, sampling rate = 80 MSPSand 3-V differential clock, unless otherwise noted
AC PERFORMANCE AC PERFORMANCEvs DIGITAL SUPPLY VOLTAGE vs DIGITAL SUPPLY VOLTAGE
Figure 23. Figure 24.
POWER DISSIPATION POWER DISSIPATIONvs SAMPLE RATE vs SAMPLE RATE
Figure 25. Figure 26.
AC PERFORMANCE AC PERFORMANCEvs TEMPERATURE vs INPUT AMPLITUDE
Figure 27. Figure 28.
16
Submit Documentation Feedback
www.ti.com
100
90
80
70
60
50
40
30
20
10
0
−10
−20
−30
AC Performance −dB
Input Amplitude −dBFS
−100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0
fIN = 150MHz
SFDR (dBc)
SNR (dBc)
SNR (dBFS)
90
80
70
60
50
40
30
20
10
0
−10
−20
−30
AC Performance −dB
Input Amplitude −dBFS
−100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0
fIN = 220MHz
SFDR (dBc)
SNR (dBc)
SNR (dBFS)
95
90
85
80
75
70
65
Differential Clock Amplitude −V
0 0.5 1.0 1.5 2.0 2.5 3.0
fIN = 70MHz
SFDR
SNR
SFDR −dBcSNR −dBFS
40
35
30
25
20
15
10
5
0
8203
8204
8205
8206
8207
8208
8209
8210
8211
8212
8213
8214
8215
8216
Occurrence −%
Code
0
−20
−40
−60
−80
−100
−120
−140
Amplitude −dB
f−Frequency −MHz
0 5 10 15 20 25 30 35 40
fS= 76.8MSPS
fIN = 170MHz
100
95
90
85
80
75
70
65
Clock Duty Cycle −%
40 5045 55 60
fIN = 20MHz
SFDR
SNR
SFDR −dBcSNR −dBFS
ADS5542
SBAS308D – MAY 2004 – REVISED FEBRUARY 2007
TYPICAL CHARACTERISTICS (continued)Typical values given at T
A
= 25 °C, AV
DD
= DRV
DD
= 3.3 V, differential input amplitude = –1dBFS, sampling rate = 80 MSPSand 3-V differential clock, unless otherwise noted
AC PERFORMANCE AC PERFORMANCEvs INPUT AMPLITUDE vs INPUT AMPLITUDE
Figure 29. Figure 30.
OUTPUT AC PERFORMANCENOISE HISTOGRAM vs CLOCK AMPLITUDE
Figure 31. Figure 32.
WCDMA AC PERFORMANCECARRIER vs CLOCK DUTY CYCLE
Figure 33. Figure 34.
17Submit Documentation Feedback
www.ti.com
TYPICAL CHARACTERISTICS
63
64
65
65
66
66
66
64
62
66
67
67
68
68
69
69
69
69
70
70
70
71
71
71
72
72
72
73
73
73
70
68
70
72
74
74
74
74
50 100 150 200 250 300
10
20
30
40
50
60
70
80
90
100
Input Frequency (MHz)
Sampling Rate (MSPS)
SNR (dBFS)
ADS5542
SBAS308D – MAY 2004 – REVISED FEBRUARY 2007
Typical values given at T
A
= 25 °C, AV
DD
= DRV
DD
= 3.3 V, differential input amplitude = -1dBFS, and 3-V differential clock,unless otherwise noted
SIGNAL-TO-NOISE RATIO (SNR)
Figure 35.
18
Submit Documentation Feedback
www.ti.com
10
20
30
40
50
60
70
80
90
100
100
69
69
71
71
73
73
73
73
71
71 67
75
75
75
75
77
77
77
77
79
79
79
79
79
81
81
81
81
81
81
81
81
81
83
83
83
83
85
85 85
85
85
85
85
85
85
85
85
85
87
87
87
87
87
87
87
87
87
87
87
89
89
89
89
91
91
91
91
150 200 250 300 65
70
75
80
85
90
50 Input Frequency (MHz)
Sampling Rate (MSPS)
SFDR (dBc)
ADS5542
SBAS308D – MAY 2004 – REVISED FEBRUARY 2007
TYPICAL CHARACTERISTICS (continued)Typical values given at T
A
= 25 °C, AV
DD
= DRV
DD
= 3.3 V, differential input amplitude = -1dBFS, and 3-V differential clock,unless otherwise noted
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
Figure 36.
19Submit Documentation Feedback
www.ti.com
APPLICATION INFORMATION
THEORY OF OPERATION
INPUT CONFIGURATION
R3
R1a
L1
L2R1b
C1a
C1b
CA
CP1CP3
VINCM
1V
CP4
CP2
INP
INM
S3a
S3b
S2
S1a
S1b
L1, L2: 6 nH − 10 nH effective
R1a, R1b: 5W − 8W
C1a, C1b: 2.2 pF − 2.6 pF
CP1, CP2: 2.5 pF − 3.5 pF
CP3, CP4: 1.2 pF − 1.8 pF
CA: 0.8 pF − 1.2 pF
R3: 80 W − 120 W
Swithches: S1a, S1b: On Resistance: 35 W − 50 W
S2: On Resistance: 7.5 W − 15 W
S3a, S3b: On Resistance: 40 W − 60 W
All switches OFF Resistance: 10 GW
ADS5542
SBAS308D – MAY 2004 – REVISED FEBRUARY 2007
The ADS5542 is a low-power, 14-bit, 80 MSPS, CMOS, switched capacitor, pipeline ADC that operates from asingle 3.3-V supply. The conversion process is initiated by a falling edge of the external input clock. Once thesignal is captured by the input S&H, the input sample is sequentially converted by a series of small resolutionstages, with the outputs combined in a digital correction logic block. Both the rising and the falling clock edgesare used to propagate the sample through the pipeline every half clock cycle. This process results in adatalatency of 17.5 clock cycles, after which the output data is available as a 14-bit parallel word, coded in eitherstraight offset binary or binary two's complement format.
The analog input for the ADS5542 consists of a differential sample-and-hold architecture implemented using theswitched capacitor technique shown in Figure 37 .
A. All Switches are ON in sampling phase which is approximately one half of a clock period.
Figure 37. Analog Input Stage
20
Submit Documentation Feedback
www.ti.com
R0
50 W
Z0
50 W
1:1 INP
INM CM
ADT1−1WT
R
50 W
1nF 0.1mF
AC Signal
Source
10 W
25 W
25W
ADS5542
400mA fS(in MSPS)
80 MSPS
(2)
ADS5542
SBAS308D – MAY 2004 – REVISED FEBRUARY 2007
This differential input topology produces a high level of ac-performance for high sampling rates. It also results ina very high usable input bandwidth, especially important for high intermediate-frequency (IF) or undersamplingapplications. The ADS5542 requires each of the analog inputs (INP, INM) to be externally biased around thecommon-mode level of the internal circuitry (CM, pin 17). For a full-scale differential input, each of the differentiallines of the input signal (pins 19 and 20) swings symmetrically between CM + 0.575 V and CM – 0.575 V. Thismeans that each input is driven with a signal of up to CM ±0.575 V, so that each input has a maximumdifferential signal of 1.15 V
PP
for a total differential input signal swing of 2.3 V
PP
. The maximum swing isdetermined by the two reference voltages, the top reference (REFP, pin 29), and the bottom reference (REFM,pin 30).
The ADS5542 obtains optimum performance when the analog inputs are driven differentially. The circuit shownin Figure 38 shows one possible configuration using an RF transformer.
Figure 38. Transformer Input to Convert Single-Ended Signal to Differential Signal
The single-ended signal is fed to the primary winding of an RF transformer. Since the input signal must bebiased around the common-mode voltage of the internal circuitry, the common-mode voltage (V
CM
) from theADS5542 is connected to the center-tap of the secondary winding. To ensure a steady low-noise V
CM
reference,best performance is obtained when the CM (pin 17) output is filtered to ground with 0.1 µF and 0.001- µFlow-inductance capacitors.
Output V
CM
(pin 17) is designed to directly drive the ADC input. When providing a custom CM level, be awarethat the input structure of the ADC sinks a common-mode current in the order of 400 µA (200 µA per input) at 80MSPS. Equation 2 describes the dependency of the common-mode current and the sampling frequency:
Where:
f
S
> 2MSPS.
This equation helps to design the output capability and impedance of the driving circuit accordingly.
When it is necessary to buffer or apply a gain to the incoming analog signal, it is possible to combinesingle-ended operational amplifiers with an RF transformer, or to use a differential input/output amplifier withouta transformer, to drive the input of the ADS5542. Texas Instruments offers a wide selection of single-endedoperational amplifiers (including the THS3201, THS3202, OPA695, and OPA847) that can be selecteddepending on the application. An RF gain block amplifier, such as Texas Instruments THS9001, can also beused with an RF transformer for high input frequency applications. The THS4503 is a recommended differentialinput/output amplifier. Table 4 lists the recommended amplifiers.
When using single-ended operational amplifiers (such as the THS3201, THS3202, OPA695, or OPA847) toprovide gain, a three-amplifier circuit is recommended with one amplifier driving the primary of an RFtransformer and one amplifier in each of the legs of the secondary driving the two differential inputs of theADS5542. These three amplifier circuits minimize even-order harmonics. For high frequency inputs, an RF gainblock amplifier can be used to drive a transformer primary; in this case, the transformer secondary connectionscan drive the input of the ADS5542 directly, as shown in Figure 38 , or with the addition of the filter circuit shownin Figure 39 .
21Submit Documentation Feedback
www.ti.com
RIN
RIN
CIN
0.1mF
RT
0.1mF
1000pF
1:1
RS
OPA695
R1
AV= 8V/V
(18dB)
R2
VIN INP
INM CM
-5V+5V
ADS5542
25 W
25 W
10 W
100 W
100 W
57.5 W
400 W
RF
RG
VOCM INP
INM CM
RF
RG
RS
0.1mF
0.1mF
10mF
1mF
RT
+3.3V
+5V
0.1mF10mF
-5V
THS4503
RIN
RIN
10 W
ADS5542
14-Bit / 80 MSPS
ADS5542
SBAS308D – MAY 2004 – REVISED FEBRUARY 2007
Figure 39 illustrates how R
IN
and C
IN
can be placed to isolate the signal source from the switching inputs of theADC and to implement a low-pass RC filter to limit the input noise in the ADC. It is recommended that thesecomponents be included in the ADS5542 circuit layout when any of the amplifier circuits discussed previouslyare used. The components allow fine-tuning of the circuit performance. Any mismatch between the differentiallines of the ADS5542 input produces a degradation in performance at high input frequencies, mainlycharacterized by an increase in the even-order harmonics. In this case, special care should be taken to keep asmuch electrical symmetry as possible between both inputs.
Another possible configuration for lower-frequency signals is the use of differential input/output amplifiers thatcan simplify the driver circuit for applications requiring dc-coupling of the input. Flexible in their configurations(see Figure 40 ), such amplifiers can be used for single-ended-to-differential conversion signal amplification.
Table 4. Recommended Amplifiers to Drive the Input of the ADS5542
INPUT SIGNAL FREQUENCY RECOMMENDED AMPLIFIER TYPE OF AMPLIFIER USE WITH TRANSFORMER?
DC to 20 MHz THS4503 Differential In/Out Amp NoDC to 50 MHz OPA847 Operational Amp YesDC to 100 MHz THS4509 Differential In/Out Amp NoOPA695 Operational Amp Yes10 MHz to 120 MHz THS3201 Operational Amp YesTHS3202 Operational Amp YesOver 100 MHz THS9001 RF Gain Block Yes
Figure 39. Converting a Single-Ended Input Signal to a Differential Signal Using an RF Transformer
Figure 40. Using the THS4503 with the ADS5542
22
Submit Documentation Feedback
www.ti.com
POWER-SUPPLY SEQUENCE
AVDD
REFP
29
28
2 kW
1 W
1 mF
POWER-DOWN
REFERENCE CIRCUIT
29
30
31
REFP
REFM
IREF
1 W
1 W
56.2 kW
1 mF
1 mF
ADS5542
SBAS308D – MAY 2004 – REVISED FEBRUARY 2007
The preferred power-up sequence is to ramp AV
DD
first, followed by DRV
DD
, including a simultaneous ramp ofAV
DD
and DRV
DD
. In the event that DRV
DD
ramps up first in the system, care must be taken to ensure that AV
DDramps up within 10 ms. Optionally, it is recommended to put a 2-k Ωresistor from REFP (pin 29) to AVDD asshown in Figure 41 . This helps to make the device more robust to power supply ramp-up timings.
Figure 41.
The device enters power-down in one of two ways: either by reducing the clock speed or by setting the PDN bitthrought the serial programming interface. Using the reduced clock speed, power-down may be initiated for clockfrequency below 2 MSPS. The exact frequency at which the power down occurs varies from device to device.
Using the serial interface PDN bit to power down the device places the outputs in a high-impedance state andonly the internal reference remains on to reduce the power-up time. The power-down mode reduces powerdissipation to approximately 180 mW.
The ADS5542 has built-in internal reference generation, requiring no external circuitry on the printed circuitboard (PCB). For optimum performance, it is best to connect both REFP and REFM to ground with a 1- µFdecoupling capacitor (the 1- Ωresistor shown in Figure 42 is optional). In addition, an external 56.2-k Ωresistorshould be connected from IREF (pin 31) to AGND to set the proper current for the operation of the ADC, asshown in Figure 42 . No capacitor should be connected between pin 31 and ground; only the 56.2-k Ωresistorshould be used.
Figure 42. REFP, REFM, and IREF Connections for Optimum Performance
23Submit Documentation Feedback
www.ti.com
CLOCK INPUT
5 kW5 kW
3 pF 3 pF
6 pF
CLKP CLKM
CM CM
0.01mF
0.01mF
CLKP
CLKM
Square Wave
or Sine Wave
(3VPP)
ADS5542
0.01mFCLKP
CLKM
0.01mF
Differential Square Wave
or Sine Wave
(3VPP)ADS5542
ADS5542
SBAS308D – MAY 2004 – REVISED FEBRUARY 2007
The ADS5542 clock input can be driven with either a differential clock signal or a single-ended clock input, withlittle or no difference in performance between both configurations. The common-mode voltage of the clock inputsis set internally to CM (pin 17) using internal 5-k Ωresistors that connect CLKP (pin 10) and CLKM (pin 11) toCM (pin 17), as shown in Figure 43 .
Figure 43. Clock Inputs
When driven with a single-ended CMOS clock input, it is best to connect CLKM (pin 11) to ground with a0.01- µF capacitor, while CLKP is ac-coupled with a 0.01- µF capacitor to the clock source, as shown inFigure 44 .
Figure 44. AC-Coupled, Single-Ended Clock Input
The ADS5542 clock input can also be driven differentially, reducing susceptibility to common-mode noise. In thiscase, it is best to connect both clock inputs to the differential input clock signal with 0.01- µF capacitors, asshown in Figure 45 .
Figure 45. AC-Coupled, Differential Clock Input
For high input frequency sampling, it is recommended to use a clock source with low jitter. Additionally, theinternal ADC core uses both edges of the clock for the conversion process. This means that, ideally, a 50% dutycycle should be provided. Figure 46 shows the performance variation of the ADC versus clock duty cycle.
24
Submit Documentation Feedback
www.ti.com
100
95
90
85
80
75
70
65
60
Clock Duty Cycle −%
35 40 5045 55 6560
SFDR
SNR
SFDR −dBcSNR −dBFS
fIN = 20MHz
95
90
85
80
75
70
65
60
Differential Clock Amplitude −V
0 0.5 1.0 1.5 2.0 2.5 3.0
fIN = 70MHz
SFDR
SNR
SFDR −dBcSNR −dBFS
OUTPUT INFORMATION
ADS5542
SBAS308D – MAY 2004 – REVISED FEBRUARY 2007
Figure 46. AC Performance vs Clock Duty Cycle
Bandpass filtering of the source can help produce a 50% duty cycle clock and reduce the effect of jitter. Whenusing a sinusoidal clock, the clock jitter further improves as the amplitude is increased. In that sense, using adifferential clock allows for the use of larger amplitudes without exceeding the supply rails and absolutemaximum ratings of the ADC clock input. Figure 47 shows the performance variation of the device versus inputclock amplitude. For detailed clocking schemes based on transformer or PECL-level clocks, see theADS55xxEVM User's Guide (SLWU010 ), available for download from www.ti.com.
Figure 47. AC Performance vs Clock Amplitude
The ADC provides 14 data outputs (D13 to D0, with D13 being the MSB and D0 the LSB), a data-ready signal(CLKOUT, pin 43), and an out-of-range indicator (OVR, pin 64) that equals one when the output reaches thefull-scale limits.
Two different output formats (straight offset binary or two's complement) and two different output clock polarities(latching output data on rising or falling edge of the output clock) can be selected by setting DFS (pin 40) to oneof four different voltages. Table 3 details the four modes. In addition, output enable control (OE, pin 41, activehigh) is provided to put the outputs into a high-impedance state.
25Submit Documentation Feedback
www.ti.com
SERIAL PROGRAMMING INTERFACE
ADS5542
SBAS308D – MAY 2004 – REVISED FEBRUARY 2007
In the event of an input voltage overdrive, the digital outputs go to the appropriate full scale level. For a positiveoverdrive, the output code is 0x3FFF in straight offset binary output format, and 0x1FFF in 2's complementoutput format. For a negative input overdrive, the output code is 0x0000 in straight offset binary output formatand 0x2000 in two's complement output format. These outputs to an overdrive signal are ensured throughdesign and characterization
The output circuitry of the ADS5542, by design, minimizes the noise produced by the data switching transients,and, in particular, its coupling to the ADC analog circuitry. Output D4 (pin 51) senses the load capacitance andadjusts the drive capability of all the output pins of the ADC to maintain the same output slew rate described inthe timing diagram of Figure 1 . Care should be taken to ensure that all output lines (including CLKOUT) havenearly the same load as D4 (pin 51). This circuit also reduces the sensitivity of the output timing versus supplyvoltage or temperature. Placing external resistors in series with the outputs is not recommended.
The timing characteristics of the digital outputs change for sampling rates below the 80 MSPS maximumsampling frequency. Table 5 and Table 6 show the values of various timing parameters for lower samplingfrequenies.
To use the input clock as the data capture clock, it is necessary to delay the input clock by a delay, t
d
, thatresults in the desired setup or hold time. Use either of the following equations to calculate the value of t
d
.Desired setup time = t
d
– t
STARTDesired hold time = t
END
– t
d
Table 5. Timing Characteristics at Additional Sampling Frequencies
t
SETUP
(ns) t
HOLD
(ns) t
START
(ns) t
END
(ns) t
r
(ns) t
f
(ns)f
S(MSPS)
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
65 4.3 5.7 2 3 2.8 4.5 8.3 11.8 6.6 7.2 5.5 6.440 8.5 11 2.6 3.5 –1 1.5 8.9 14.5 7.5 8 7.3 7.820 17 25.7 2.5 4.7 –9.8 2 9.5 21.6 7.5 8 7.6 810 27 51 4 6.5 -30 -3 11.5 312 284 370 8 19 185 320 515 576 50 82 75 150
Table 6. Timing Characteristics at Additional Sampling Frequencies
CLKOUT Jitter,CLKOUT, Rise Time CLKOUT, Fall Time Input-to-Output Clock DelayPeak-to-Peakf
S
t
r
(ns) t
f
(ns) t
PDI
(ns)t
JIT
(ps)(MSPS)
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
65 3.1 3.5 2.6 2.9 260 380 7.8 8.5 9.440 4.8 5.3 4 4.4 445 650 9.5 10.4 11.420 8.3 9.5 7.6 8.2 800 1200 13 15.5 1810 16 20.7 25.52 31 52 36 65 2610 4400 537 551 567
The ADS5542 has internal registers for the programming of some of the modes described in the previoussections. The registers should be reset after power-up by applying a 2 us (minimum) high pulse on RESET (pin35); this also resets the entire ADC and sets the data outputs to low. This pin has a 200-k Ωinternal pullupresistor to AV
DD
. The programming is done through a three-wire interface. The timing diagram and serial registersetting in the Serial Programing Interface section describe the programming of this register.
Table 2 shows the different modes and the bit values to be written to the register to enable them.
Note that some of these modes may modify the standard operation of the device and possibly vary theperformance with respect to the typical data shown in this data sheet.
26
Submit Documentation Feedback
www.ti.com
PowerPAD PACKAGE
Assembly Process
ADS5542
SBAS308D – MAY 2004 – REVISED FEBRUARY 2007
Applying a RESET signal is absolutely essential to set the internal registers to their default states for normaloperation. If the hardware RESET function is not used in the system, the RESET pin must be tied to ground andit is necessary to write the default values to the internal registers through the serial programming interface. Thefollowing registers must be written in this order.Write 9000h (Address 9, Data 000)Write A000h (Address A, Data 000)Write B000h (Address B, Data 000)Write C000h (Address C, Data 000)Write D000h (Address D, Data 000)Write E000h (Address E, Data 804)Write 0000h (Address 0, Data 000)Write 1000h (Address 1, Data 000)Write F000h (Address F, Data 000)
NOTE:
This procedure is only required if a RESET pulse is not provided to the device.
The PowerPAD package is a thermally enhanced standard size IC package designed to eliminate the use ofbulky heatsinks and slugs traditionally used in thermal packages. This package can be easily mounted usingstandard printed circuit board (PCB) assembly techniques and can be removed and replaced using standardrepair procedures.
The PowerPAD package is designed so that the lead frame die pad (or thermal pad) is exposed on the bottomof the IC. This provides a low thermal resistance path between the die and the exterior of the package. Thethermal pad on the bottom of the IC can then be soldered directly to the printed circuit board (PCB), using thePCB as a heatsink.
1. Prepare the PCB top-side etch pattern including etch for the leads as well as the thermal pad asillustrated in the Mechanical Data section. The recommended thermal pad dimension is 8 mm x 8 mm.2. Place a 5-by-5 array of thermal vias in the thermal pad area. These holes should be 13 mils in diameter.The small size prevents wicking of the solder through the holes.3. It is recommended to place a small number of 25 mil diameter holes under the package, but outside thethermal pad area to provide an additional heat path.4. Connect all holes (both those inside and outside the thermal pad area) to an internal copper plane (suchas a ground plane).5. Do not use the typical web or spoke via connection pattern when connecting the thermal vias to theground plane. The spoke pattern increases the thermal resistance to the ground plane.6. The top-side solder mask should leave exposed the terminals of the package and the thermal pad area.7. Cover the entire bottom side of the PowerPAD vias to prevent solder wicking.8. Apply solder paste to the exposed thermal pad area and all of the package terminals.
For more detailed information regarding the PowerPAD package and its thermal properties, see either theapplication brief SLMA004 B ( PowerPAD Made Easy) or technical brief SLMA002 (PowerPAD ThermallyEnhanced Package).
27Submit Documentation Feedback
www.ti.com
ADS5542
SBAS308D – MAY 2004 – REVISED FEBRUARY 2007
Table 7. Revision History
Added notes regarding the input voltage overstress requirements in the absolute maximum ratings tableChanged minimum recommended sampling rate to 2 MSPS.Added timing parameters - output clock jitter, wakeup time, output clock rise and fall time, Tpdi and timings across Fs.Clarified output capture test modes.Pin table info added - RESET pin, note on OE, SEN, SDATA and SCLK pinsUpdated the definitions section.Removed the input voltage stress section - notes added in absolute maximum ratings tableUpdated the Power Down section to reflect the newly specified 2 MSPS minimum sampling rate.Note added in Power supply sequence section for robust power supply ramp-up.Note on mandatory RESET added
Rev D
Added min/max specs for Offset and Gain errors.
28
Submit Documentation Feedback
PACKAGE OPTION ADDENDUM
www.ti.com 21-May-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
ADS5542IPAP ACTIVE HTQFP PAP 64 160 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ADS5542IPAPG4 ACTIVE HTQFP PAP 64 160 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ADS5542IPAPR ACTIVE HTQFP PAP 64 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ADS5542IPAPRG4 ACTIVE HTQFP PAP 64 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS5542IPAPR HTQFP PAP 64 1000 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Oct-2009
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS5542IPAPR HTQFP PAP 64 1000 346.0 346.0 41.0
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Oct-2009
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products Applications
Amplifiers amplifier.ti.com Audio www.ti.com/audio
Data Converters dataconverter.ti.com Automotive www.ti.com/automotive
DLP® Products www.dlp.com Communications and www.ti.com/communications
Telecom
DSP dsp.ti.com Computers and www.ti.com/computers
Peripherals
Clocks and Timers www.ti.com/clocks Consumer Electronics www.ti.com/consumer-apps
Interface interface.ti.com Energy www.ti.com/energy
Logic logic.ti.com Industrial www.ti.com/industrial
Power Mgmt power.ti.com Medical www.ti.com/medical
Microcontrollers microcontroller.ti.com Security www.ti.com/security
RFID www.ti-rfid.com Space, Avionics & www.ti.com/space-avionics-defense
Defense
RF/IF and ZigBee® Solutions www.ti.com/lprf Video and Imaging www.ti.com/video
Wireless www.ti.com/wireless-apps
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2010, Texas Instruments Incorporated
