SN74F161AN3 - TEXAS INSTRUMENTS

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74F161A, 74F163A Synchronous Presettable Binary Counter

April 2007

74F161A, 74F163A Rev. 1.0.2

74F161A, 74F163A

Synchronous Presettable Binary Counter

Features

■

Synchronous counting and loading

■

High-speed synchronous expansion

■

Typical count frequency of 120MHz

General Description

The 74F161A and 74F163A are high-speed synchro-

nous modulo-16 binary counters. They are synchro-

nously presettable for application in programmable

dividers and have two types of Count Enable inputs plus

a Terminal Count output for versatility in forming

synchronous multi-stage counters. The 74F161A has an

asynchronous Master-Reset input that overrides all other

inputs and forces the outputs LOW. The 74F163A has a

Synchronous Reset input that overrides counting and

parallel loading and allows the outputs to be simulta-

neously reset on the rising edge of the clock. The

74F161A and 74F163A are high-speed versions of the

74F161 and 74F163.

Ordering Information

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

Connection Diagrams

Order

Number

Package

Number Package Description

74F161ASC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74F161ASJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74F161APC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

74F163ASC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74F163ASJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74F163APC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

74F161A 74F163A

74F161A, 74F163A Synchronous Presettable Binary Counter

74F161A, 74F163A Rev. 1.0.2 2

Logic Symbols

Unit Loading/Fan Out

74F161A

IEEE/IEC

74F161A

74F163A

IEEE/IEC

74F163A

Pin Names Description

U.L.

HIGH / LOW

Input I

IH

/ I

IL

Output I

OH

/ I

OL

CEP Count Enable Parallel Input 1.0 / 1.0 20µA / -0.6mA

CET Count Enable Trickle Input 1.0 / 2.0 20µA / -1.2mA

CP Clock Pulse Input (Active Rising Edge) 1.0 / 1.0 20µA / -0.6 mA

MR (74F161A) Asynchronous Master Reset Input (Active LOW) 1.0 / 1.0 20µA / -0.6 mA

SR (74F163A) Synchronous Reset Input (Active LOW) 1.0 / 2.0 20µA / -1.2 mA

P

0

–P

3

Parallel Data Inputs 1.0 / 1.0 20µA / -0.6 mA

PE Parallel Enable Input (Active LOW) 1.0 / 2.0 20µA / -1.2mA

Q

0

–Q

3

Flip-Flop Outputs 50 / 33.3 -1mA / 20mA

TC Terminal Count Output 50 / 33.3 -1mA / 20mA

74F161A, 74F163A Synchronous Presettable Binary Counter

74F161A, 74F163A Rev. 1.0.2 3

Functional Description

The 74F161A and 74F163A count in modulo-16 binary

sequence. From state 15 (HHHH) they increment to

state 0 (LLLL). The clock inputs of all flip-flops are driven

in parallel through a clock buffer. Thus all changes of the

Q outputs (except due to Master Reset of the 74F161A)

occur as a result of, and synchronous with, the LOW-to-

HIGH transition of the CP input signal. The circuits have

four fundamental modes of operation, in order of prece-

dence: asynchronous reset (74F161A), synchronous

reset (74F163A), parallel load, count-up and hold. Five

control inputs—Master Reset (MR, 74F161A), Synchro-

nous Reset (SR, 74F163A), Parallel Enable (PE), Count

Enable Parallel (CEP) and Count Enable Trickle (CET)—

determine the mode of operation, as shown in the Mode

Select Table. A LOW signal on MR overrides all other

inputs and asynchronously forces all outputs LOW. A

LOW signal on SR overrides counting and parallel load-

ing and allows all outputs to go LOW on the next rising

edge of CP. A LOW signal on PE overrides counting and

allows information on the Parallel Data (P

n

) inputs to be

loaded into the flip-flops on the next rising edge of CP.

With PE and MR ('F161A) or SR (74F163A) HIGH, CEP

and CET permit counting when both are HIGH. Con-

versely, a LOW signal on either CEP or CET inhibits

counting.

The 74F161A and 74F163A use D-type edge triggered

flip-flops and changing the SR, PE, CEP and CET inputs

when the CP is in either state does not cause errors, pro-

vided that the recommended setup and hold times, with

respect to the rising edge of CP, are observed.

The Terminal Count (TC) output is HIGH when CET is

HIGH and the counter is in state 15. To implement syn-

chronous multi-stage counters, the TC outputs can be

used with the CEP and CET inputs in two different ways.

Please refer to the 74F568 data sheet. The TC output is

subject to decoding spikes due to internal race condi-

tions and is therefore not recommended for use as a

clock or asynchronous reset for flip-flops, counters or

registers.

Logic Equations:

Count Enable = CEP • CET • PE

TC = Q

0

• Q

1

• Q

2

• Q

3

• CET

Mode Select Table

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Note:

1. For 74F163A only

State Diagram

SR

(1)

PE CET CEP

Action on the Rising

Clock Edge ( )

L X X X Reset (Clear)

HLXXLoad (P

n

→

Q

n

)

HH HHCount (Increment)

HHLXNo Change (Hold)

HHXLNo Change (Hold)

74F161A, 74F163A Synchronous Presettable Binary Counter

74F161A, 74F163A Rev. 1.0.2 4

Block Diagram

Figure 1.

74F161A, 74F163A Synchronous Presettable Binary Counter

74F161A, 74F163A Rev. 1.0.2 5

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Note:

2. Either voltage limit or current limit is sufficient to protect inputs.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to absolute maximum ratings.

Symbol Parameter Rating

T

STG

Storage Temperature –65°C to +150°C

T

A

Ambient Temperature Under Bias –55°C to +125°C

T

J

Junction Temperature Under Bias –55°C to +150°C

V

CC

V

CC

Pin Potential to Ground Pin –0.5V to +7.0V

V

IN

Input Voltage

(2)

–0.5V to +7.0V

I

IN

Input Current

(2)

–30mA to +5.0mA

V

O

Voltage Applied to Output in HIGH State (with V

CC

=

0V)

Standard Output

3-STATE Output

–0.5V to V

CC

–0.5V to +5.5V

Current Applied to Output in LOW State (Max.) twice the rated I

OL

(mA)

ESD Last Passing Voltage (Min.) 4000V

Symbol Parameter Rating

T

A

Free Air Ambient Temperature 0°C to +70°C

V

CC

Supply Voltage +4.5V to +5.5V

74F161A, 74F163A Synchronous Presettable Binary Counter

74F161A, 74F163A Rev. 1.0.2 6

DC Electrical Characteristics

Symbol Parameter V

CC

Conditions Min. Typ. Max. Units

V

IH

Input HIGH Voltage Recognized as a HIGH Signal 2.0 V

V

IL

Input LOW Voltage Recognized as a LOW Signal 0.8 V

V

CD

Input Clamp Diode Voltage Min. I

IN

=

–18mA –1.2 V

V

OH

Output HIGH

Voltage

10% V

CC

Min. 2.5 V

5% V

CC

2.7

V

OL

Output LOW

Voltage

10% V

CC

Min. I

OL

=

20mA 0.5 V

I

IH

Input HIGH Current Max. V

IN

=

2.7V 5.0 µA

I

BVI

Input HIGH Current

Breakdown Test

Max. V

IN

=

7.0V 7.0 µA

I

CEX

Output HIGH Leakage

Current

Max. V

OUT

= V

CC

50 µA

V

ID

Input Leakage Test 0.0 I

ID

=

1.9µA, All Other Pins

Grounded

4.75 V

I

OD

Output Leakage Circuit

Current

0.0 V

IOD

=

150mV, All Other Pins

Grounded

3.75 µA

I

IL

Input LOW Current Max. V

IN

=

0.5V (CEP, CP, MR, P

0

–P

3

) –0.6 mA

V

IN

=

0.5V (CET, PE, SR) –1.2

I

OS

Output Short-Circuit

Current

Max. V

OUT

=

0.0V –60 –150 mA

I

CC

Power Supply Voltage Max. 37 55 mA

74F161A, 74F163A Synchronous Presettable Binary Counter

74F161A, 74F163A Rev. 1.0.2 7

AC Electrical Characteristics

AC Operating Requirements

Symbol Parameter

T

A

=

+25°C,

V

CC

=

+5.0V,

C

L

=

50pF

T

A

=

–55°C to +125°C,

V

CC

=

+5.0V,

C

L

=

50pF

T

A

=

0°C to 70°C,

V

CC

=

+5.0V,

C

L

=

50pF

UnitsMin. Typ. Max. Min. Max. Min. Max.

f

MAX

Maximum Count Frequency 100 MHz

t

PLH

Propagation Delay,

CP to Q

n

(PE Input HIGH)

3.5 5.5 7.5 3.5 9.0 3.5 8.5 ns

t

PHL

3.5 7.5 10.0 3.5 11.5 3.5 11.0

t

PLH

Propagation Delay,

CP to Q

n

(PE Input LOW)

4.0 6.0 8.5 4.0 10.0 4.0 9.5 ns

t

PHL

4.0 6.0 8.5 4.0 10.0 4.0 9.5

t

PLH Propagation Delay,

CP to TC

5.0 10.0 14.0 5.0 16.5 5.0 15.0 ns

tPHL 5.0 10.0 14.0 5.0 15.5 5.0 15.0

tPLH Propagation Delay,

CET to TC

2.5 4.5 7.5 2.5 9.0 2.5 8.5 ns

tPHL 2.5 4.5 7.5 2.5 9.0 2.5 8.5

tPHL Propagation Delay,

MR to Qn (74F161A)

5.5 9.0 12.0 5.5 14.0 5.5 13.0 ns

tPHL Propagation Delay,

MR to TC (74F161A)

4.5 8.0 10.5 4.5 12.5 4.5 11.5 ns

Symbol Parameter

TA = +25°C,

VCC = +5.0V

TA = –55°C to +125°C,

VCC = +5.0V

TA = 0°C to 70°C,

VCC = +5.0V

UnitsMin. Max. Min. Max. Min. Max.

tS(H) Setup Time, HIGH or LOW,

Pn to CP

5.0 5.5 5.0 ns

tS(L) 5.0 5.5 5.0

tH(H) Hold Time, HIGH or LOW,

Pn to CP

2.0 2.5 2.0 ns

tH(L) 2.0 2.5 2.0

tS(H) Setup Time, HIGH or LOW,

PE or SR to CP

11.0 13.5 11.5 ns

tS(L) 8.5 10.5 9.5

tH(H) Hold Time, HIGH or LOW,

PE or SR to CP

2.0 3.6 2.0 ns

tH(L) 00 0

tS(H) Setup Time, HIGH or LOW,

CEP or CET to CP

11.0 13.0 11.5 ns

tS(L) 5.0 6.0 5.0

tH(H) Hold Time, HIGH or LOW,

CEP or CET to CP

00 0ns

tH(L) 00 0

tW(H) Clock Pulse Width (Load),

HIGH or LOW

5.0 5.0 5.0 ns

tW(L) 5.0 5.0 5.0

tW(H) Clock Pulse Width (Count),

HIGH or LOW

4.0 5.0 4.0 ns

tW(L) 6.0 8.0 7.0

tW(L) MR Pulse Width, LOW

(74F161A)

5.0 5.0 5.0 ns

tREC Recovery Time, MR to CP

(74F161A)

6.0 6.0 6.0 ns

74F161A, 74F163A Synchronous Presettable Binary Counter

74F161A, 74F163A Rev. 1.0.2 8

Physical Dimensions

Dimensions are in inches (millimeters) unless otherwise noted.

Figure 2. 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package Number M16A

74F161A, 74F163A Synchronous Presettable Binary Counter

74F161A, 74F163A Rev. 1.0.2 9

Physical Dimensions (Continued)

Dimensions are in millimeters unless otherwise noted.

Figure 3. 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M16D

74F161A, 74F163A Synchronous Presettable Binary Counter

74F161A, 74F163A Rev. 1.0.2 10

Physical Dimensions (Continued)

Dimensions are in inches (millimeters) unless otherwise noted.

Figure 4. 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N16E

74F161A, 74F163A Synchronous Presettable Binary Counter

74F161A, 74F163A Rev. 1.0.2 11

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HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE

APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER

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WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR

SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body or

(b) support or sustain life, and (c) whose failure to perform

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to

result in a significant injury of the user.

2. A critical component in any component of a life support,

device, or system whose failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or In Design This datasheet contains the design specifications for product

development. Specifications may change in any manner without notice.

Preliminary First Production This datasheet contains preliminary data; supplementary data will be

published at a later date. Fairchild Semiconductor reserves the right to

make changes at any time without notice to improve design.

No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor

reserves the right to make changes at any time without notice to improve

design.

Obsolete Not In Production This datasheet contains specifications on a product that has been

discontinued by Fairchild Semiconductor. The datasheet is printed for

reference information only.

Rev. I24