1SC2060P2Ax-17
Prelim i nary Dat a Shee t
Page 10 INTELLIGENT POWER ELECTRONICS
External turn-on gate re sistance: 0.75Ω
External turn-off gate resistance: 1.25Ω
External gate resistor loop: 2.0Ω
9) The values given refer to the total gate resistance, including both external resistors and the internal
resistance of the power module / t r ansistor.
10) The secondary side output voltag e swing must not ex ceed 20V.
11) The maximum current given is the short circuit value of the output stage. Continuous operation is
limited by thermal constraints. The surface temperature of the output stage must not exceed 125°C.
12) HiPot testing (= dielectric testing) must generally be restricted to suitable components. This gate
driver is suited for HiPot te sting. Nevert heless, it is str ongly recomme nded to limit the testing time t o
1s slots as stipulated by EN 50178. Excessive HiPot testing at voltages much higher than 1200V AC(eff)
may lead to insulation degradation. No degradation has been observed over 1min. testing at
5000VAC(eff). Every production sample shipped to customers has undergone 100% testing at
5000VAC(eff) (typical) for 1s.
13) Partial discharge measurement is performed in accordance with IEC 60270 and isolation coordination
specified in EN 50 178. The minimum value given is designed to include appropriate safety margins for
long-term ageing. Accelerated ageing tests show virtually no insulation det erioratio n. Minimum partial
discharge extinction voltages remain >2100V even after 2600 slow thermal cycles between –40°C and
125°C and also after 500 thermal shock cycles between –55°C and 150°C. The partial dischar ge
extinction voltage is coordinated for safe isolation to EN 50178.
14) External blocking capacitors are to be placed between VISO and VE as well as VE and COM for gate
charges exceeding 3µC. Ceramic capacitors are recommended. A minimum external blocking
capacitance of 3µF is recommended for every 1µC of gate charge beyond 3µC. Insufficient ex ternal
blocking can lead to reduced driver efficiency and th us to thermal ove rload .
15) The minimum response time given is valid for the circuit given in the descrip tion and application
manual (Figs. 5 and 6) with the values of table 1 (Ca=0pF, Rth=43kΩ).
16) The blocking time sets a minimum time span between the end of any fault state and the start of
normal operation (remove fault from pin SO). The value of the blocking time can be adjusted at pin
TB. The specified blocking time is valid if TB is connected to GND.
17) This spe cification guara ntees that the drive in formation will be tra nsferred reliabl y even at a high DC-
link voltage and with ultra-fast switching operations.
18) Undervoltage monitoring of the corresponding supply voltage (VCC to GND as well as VISO to VE and
VE to COM which correspond with the approximate turn-on and turn-off g ate-emitter voltages). If the
corresponding voltage drops below this limit, the power semiconductor is switched off and a fault is
transmitted to SO.
19) Transmission delay of fault state from the secondary side to the primary status output.
20) Jitter measurements are performed with input signal IN switching between 0V and 5V referred to
GND, with a corresponding rise tim e and fall time of 5ns.
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