Vishay Dale Electronics, Inc.
Information Display Products
OLED Product Data Sheet
OLED SPE CIFI C ATION
Model No:
OLED-128Y064C-LPP3N00000
SPECIFICATION Ver: C
Module # : OLED-128Y064C-LPP3N00000
Global SAP # : O128Y064CLPP3N0000
APPROVED BY:
( FOR CUSTOMER USE ONLY )
PCB VERSION: DATA:
SALES BY
APPROVED BY
CHECKED BY
PREPARED BY
ISSUED DATE:
MODLE NO
：
RECORDS OF REVI S IO N
DOC. FIRST ISSUE
DATE
REVISED
PAGE
NO.
SUMMARY
A
B
2011.10.26
2012.01.17
2012.02.20
14
14
First issue
Add Power Consumption
Add Optics
Characteristics
2012.05.04
14
Add Brightness
1. Module Classification Information
OLED -128 Y 064 C L P P 3 N 00000
1 2 3 4 5 6 7 8 9 10 11
1 Brand：Vishay Intertechnology, Inc.
2 Horizontal Format: 128 columns
3 Display T y pe：N→Character Type, H→Graphic Ty pe ,Y→TAB Type
4
Vertical Format: 64 lines
5
Serials code: C
6 Emitting
Color
A
：
Amber
R
：
RED
B
：
Blue
C
：
Full colo r
G
：
Green
W
：
White
Y
：
Yellow Green
L
：
Yellow
7 Polarizer P：With Polar i z er ; N: Witho ut Polar i zer
8 Display
Mode P：Passive Matrix ; A: Action Matrix
9
Driver
Voltage
3: 3.0 V; 5: 5.0V
10 Touch Panel N：Without touch panel; T: With touch panel
11 Seria l No. 00000: Sales code
2. General Description
Item
Dimension
Unit
Number of Characters
128 x 64 D
ots
－
Module dim ension
89.7 × 47.2 × 3.4 (mm)
mm
Active Area
61.41 × 30.69 (mm)
mm
Pixel Pitch
0.48 × 0.48 (mm)
mm
Pixel Size
0.45 × 0.45 (mm)
mm
Weight
20.5
g
Display Mode
Passive Matrix
Display Color
Monochrome (Yellow)
Drive Duty
1/64 Duty
3. Absolute Maximum Ratings
Parameter Symbol Min Max Unit Notes
Supply Voltage for Logic
VDD
-0.3
3.5
V
1,2
Supply Voltage for Display
VCC
8
16
V
1,2
Operating Temperatur e
TOP
-40
80
°C
—
Storage Te mperature
TSTG
-40
80
°C
—
Note 1: All the above voltages are on the basis of “VSS = 0V”.
Note 2: When this module is used beyond the above absolute maximum ratings, permanent
breakage of the module may occur. Also, for normal operations, it is desirable to use
this module under the conditions according to Section 3. “Optics & Electrical
Characteristics”. If this module is used beyond these conditi ons, malfunctioning of the
module can occur and the reliability of the modul e may deter i or ate .
4. Block Diagram
4.1.POWER ON/OFF SEQUENCE &APPLICATION CIRCUIT
3.1.1 POWER ON/OFF SEQUENCE
Power ON sequence
1. Power ON VDD ,VDDI O
2. After VDD ,VDDIO become stable , set RES# pin LOW (logic low) for at least 3us(t1)
and then HIGH (logic high).
3. After set RES# pin LOW (logic low), wait for at least 3us(t2). Then Power ON Vcc. (1)
4. After Vcc. become stable , send command AFh for display ON. DEG/COM will be ON
after 100ms(tAF).
OFF
ON
tAF
t2
t1
Send
A
F
h
command for display ON
ON Vcc
RES#
ON
VDD,VDDIO
SEG/COM
GND
Vcc
GND
RES#
GND
VDD,VDDIO
Power OFF sequ ence
1. Send command AEh for display OFF.
2. Power OFF Vcc.(1),(2)
3. Wait for tOFF. Power OFF VDD ,VDDIO. (where Minimum tOFF=80ms,Typical
tOFF=100ms)
OFF
t
OFF VDD,VDDIO
OFF Vcc
Send command AEh for display OFF
GND
VDD,VDDIO
GND
Vcc
Note:
(1) Since an ESD protection circuit is connected between VDD ,VDDIO and Vcc, Vcc
becomes lower than VDD and VDD , VDDIO is ON and Vcc is OFF as shown in the
dotted line of Vcc in above figures.
(2) Vcc should be disabled when it is OFF.
4.2 A PPLICATION CIRCUIT
U1_a
C1_a C3_a C2_a R1_a
1M
0.1uf 4.7uf
4.7uf
22
21
20
18
17
19
3
2
1
VSS
VDD
VCC
E/RD#
WR#
D/C#
RES#
CS#
D7
D6
D5
D4
D3
D2
D1
D0
CS#
RES#
D/C#
WR#
E/RD#
D0
D1
D2
D3
D4
D5
D6
D7
VSS
VSS
NC
BS1
BS2
VDD
IREF
CGOMH
VCC
16
15
14
13
12
11
10
9
8
7
6
5
4
4.3 INTERFACE
4.3.1 FUNCTION BL OCK DIAGRAM
64 rows
128 columns
Dot Matrixes
12864 X 64
SSD1305
COG
BS1,BS2
VSS
D0~D7
CS#
RES#
D/C#
R/W#
E/RD#
IREF
VGOMH
VDD
VCC
4.4 PANEL LAYOUT DIAGRAM
SEG&COM Layout
C1~C63
S0~S127
C62~C0
4.5 GRAPHIC DISPLAY DATA RAM A DDRESS MA P
The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed.
The size of the RAM is 132x64=8448bits
For mechanical flexibility, re-mapping on both Segment and Common outputs can be
selected by software.
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
0x0Fh
0x0Eh
0x0Dh
0x0Ch
0x0Bh
0x0Ah
0x09h
0x08h
0x07h
0x06h
0x05h
0x04h
0x03h
0x02h
0x01h
0x00h
0x30h
0x31h
0x32h
0x33h
0x34h
0x35h
0x36h
0x37h
0x38h
0x39h
0x3Ah
0x3Bh
0x3Ch
0x3Dh
0x3Eh
0x3Fh
PAGE 6
PAGE 7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
0x80h
0x81h
0x82h
0x83h 0x00h
0x01h
0x02h
0x03h
SEG0
SEG0
SEG0
SEG0
SEG0
SEG0
SEG0
SEG0
SEG0
SEG0
SEG0
SEG0
0x83h
0x82h
0x81h
0x80h
0x7Fh
0x7Eh
0x7Dh
0x7Ch0x07h
0x06h
0x05h
0x04h
0x03h
0x02h
0x01h
0x00h
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
PAGE 2
PAGE 1
PAGE 0
0x01h
0x3Eh 0x00h
0x17h
0x16h
0x15h
0x14h
0x13h
0x12h
0x11h
0x10h
0x0Fh
0x0Eh
0x0Dh
0x0Ch
0x0Bh
0x0Ah
0x09h
0x08h
0x07h
0x06h
0x05h
0x04h
0x03h
0x02h
0x28h
0x29h
0x2Ah
0x2Bh
0x2Ch
0x2Dh
0x2Eh
0x2Fh
0x30h
0x31h
0x32h
0x33h
0x34h
0x35h
0x36h
0x37h
0x38h
0x39h
0x3Ah
0x3Bh
0x3Ch
0x3Dh
0x3Fh
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
5. Contour Drawing
The non-specified tolerance of dimension is ±0.3mm.
14.8¡Ó0.5
122
14.50 NC
VDD
D4
D3
E/RD#
D1
16 RES#
CS#
D/C#
R/W#
IREF
D5
VCC
BS2
BS1
15
17
18
19
20
21
22
14
13
12
11
10
9
8
7
6
5
4
3
2
1
VCOMH
D7
D6
D2
D0
131
NC
VCC
VCOMH
IREF
D7
D6
D5
D4
D3
D2
D1
D0
E/RD
R/W
D/C
RES
CS
FR
BS2
BS1
VDDIO
VDD
VCIR
BGGND
VBREF
NC
FB
VDDB
GDR
VSS
NC
VSS
VSS
Active Area
128*64 Pixels
CONTCT SIZE
5.0¡Ó0.5
ICSSD1305T7
Singl e Tape Teraoka 631S
27*8*0.085mm
Double Ta pe Tesa 4972
22*6*0.05mm
69.85¡Ó
2.0
28.00
Seal.white
61.30
11.50
Detail DOTS
Scale 1:10
0.48
0.03
0.48
0.03
2.0
2.0MAX
36.500
122
11.5¡Ó0.2
W=0.3
P0.5*21=10.50.5
Scale 1:2
2-?1.0
0.3¡Ó0.05
39.86
41.86¡Ó0.2
73.00¡Ó
0.2
61.41(AA)
30.69(AA)
32.69(VA)
63.41(VA)
5.795
4.795
3.190
2.190
2.0
View Di rectio n
Active Area
128*64 Pixels
View Di rectio n
82.700¡Ó
0.2
40.200¡Ó0.2
? 3.2
? 7.0
3.400
6. Interface Pin Function
No.
Symbol
Function
1
VCC
Power supply for analog circuit.
2
VCOMH
Com Voltage Output. A capacitor should be
connected
between this pin and VSS.
3
IREF
Reference current input pin.
A resistor should be connected between this pin
and VSS.
4~11
D7~D0
Data bus.
12
E/RD#
Data read operation is initiated when it’s pull low.
13
R/W#
Data write operation is initiated when it’s pull low.
1
4
D/C#
Data/ Command control.
Pull high for write/read display data.
Pull low for write command or read status.
1
5
RES#
Reset signal input.
When it’s low, initializatio n of SSD1305 is
executed.
16
CS#
Chip select input.
1
7
BS2
Communicating Protocol Select
These pins are MCU int
erface selection input. See
the
following table:
68XX-paralle
l
80XX-paralle
l
Serial
BS1
0
1
0
BS2
1
1
0
18
BS1
19
VDD
Power supply for logic circuit.
20
NC
No connection.
21
VSS
Ground.
22
VSS
Ground.
7. Optics & Electrical Characteristics
7.1INTERFACE TIMING CHART
8080-Series MCU Parallel Interface Timing Characteristics
(VDD-VSS=2.4V to 3.5V, VDDIO=VDD,TA=25℃)
Symbol
Parameter
Min
Typ
Max
Unit
tcycle
Clock Cycle T ime
300
-
-
ns
tAS
Address Setup T i me
10
-
-
ns
tAH
Address Hold Time
0
-
-
ns
tDSW
Write Data Setup Time
40
-
-
ns
tDHW
Write Data Hold Time
7
-
-
ns
tDHR
Read Data Hold Time
20
-
-
ns
tOH
Output Disabl e Time
-
-
70
ns
tACC
Access T ime
-
-
140
ns
tPWLR
Read Low Time
120
-
-
ns
tPWLW
Write Low T ime
60
-
-
ns
tPWHR
Read High Time
60
-
-
ns
tPWHW
Write High Time
60
-
-
ns
tR
Rise T ime
-
-
15
ns
tF
Fall T ime
-
-
15
ns
tCS
Chip select setup time
0
-
-
ns
tCSH
Chip select setup hold time to read
signal
0
-
-
ns
tCSF
Chip select set up hol d ti me
20
-
-
ns
8080-seriesparallel interface characteristics (Form 1)
Write cycle(Form 1)
Write cycle(Form 1)
t
OH
t
DHR
t
ACC
t
PWHR
t
PWLR
t
AH
t
R
t
CYCLE
t
F
t
AS
t
CSH
t
cs
t
AH
t
R
t
CYCLE
t
PWHW
t
PWLW
t
F
t
AS
t
CSF
t
cs
CS#
D/C#
RD#
D(7:0)
t
DHW
t
DSW
D(7:0)
WR#
D/C#
CS#
Write cycle(Form 2) Write cycle(Form 2)
t
CYCLE
t
P
t
R
t
PWHW
t
PWLW
t
CS
t
AS
t
AH
t
CSF
t
DHW
t
DSW
t
OH
t
DHR
t
ACC
t
CSH
t
AH
t
AS
t
CS
t
PWHR
t
PWLR
t
R
t
F
t
CYCLE
D(7:0)
RD#
D/C#
CS#
CS#
D/C#
WR#
D(7:0)
7.2 DC Characteristics
Characteristics
Symbol
Condition
Min
Typ
Max
Unit
Supply Voltage for Logic
VDD
－
2.4
2.7
3.5
V
Supply Voltage for Display
VCC － 14.5 15 15.5 V
High Level Input
VIH Iout = 100μA,3.3MHz
0.8×VDD － VDD V
Low Level Input
VIL Iout = 100μA,3.3MHz
0 － 0.2×VDD V
High Level Output
VOH
Iout =100μA,3.3MHZ
0.9×VDD － VDD V
Low Level Input
VOL Iout =100μA,3.3MHZ 0 － 0.1×VDD V
Operating Cur r en t for VD D
(
Panel attached) IDD Note 4
Note 5 －
90
－
mA
－
101
－
mA
Operating Cur r en t for VC C
(
Panel attached) ICC Note 4
Note 5
－
15
－
mA
－ 17 － mA
Sleep Mode Current for
VDD
IDD,
SLEEP
－ － 10 μA
Sleep Mode Current for
VCC
ICC,
SLEEP
－ － 10 μA
Power Consumption
50% Display Area
Turn on
－ 297 － mW
Power Consumption
100% Display Area
Turn on
－ 333 － mW
Note 3: Brightness (Lbr) and Supply Voltage for Display (VCC) are subject to the change of the panel
characteristics and the customer’s request.
Note 4: VDD = 3.3V, VCC = 13.7V, 50% Display Area Turn on. ( Contrast value =0x80 )
Note 5: VDD = 3.3V, VCC = 13.2V, 100% Display Area Turn on.( Contrast value = 0x80)
(Base on 80 nits on 50% checkboard and include DC to DC circuit.)
* Software configuration follows Section 4.4 Initialization.
7.3 Optics Characteristics
Characteristics
Symbol
Condition
Min
Typ
Max
Unit
C.I.E. (Yellow)
(x)
(y)
Without Polarizer
0.44
0.46
0.48
0.50
0.52
0.54
Dark Room Contrast
CR － >2000:1 － －
V iew Angle
>160 － －
Brightness
Yellow With Polarizer 60 80 － cd/m2
8. Reliability
8.1 Contents of Reliability Tests
Item
Conditions
Criteria
Hig h Tempera ture Oper ation
Low Temper atur e Operati on
80
℃,240hrs
-40
℃,240hrs
The operational
functions work.
Hig h Tempera ture Stor age
Low Temper atur e Storag e
80
℃,240hrs
-40
℃,240hrs
High Temperature/Humidity
Operatio n/ Thermal Shock
60
℃,90% RH,120，
-40
℃
80
℃，
24cycles 1 hr dwell
* The samples used for the above tests do not include polarizer.
* No moisture condensation is observed during tests.
8.2 Lifetime
Parameter
Min
Typ
Max
Unit
Condition
Notes
Operating Life
Time
100,000
－ Hrs 80 cd/m2, 50% Checkerboard 6
Note 6: The average operating lifetime at room temperature is estimated by the accelerated
operation at high temperature conditions.
8.3 Failure Check Standard
After the completion of the described reliability test, the samples were left at room
temperature for 2 hrs prior to conducting the failure test at 23±5°C; 55±1 5% RH.
9. Inspecti on specificatio n
NO
Item
Criterion
AQL
01 Electrical
Testing
1.1 Missing vertical, horizontal segment, segment contrast
defect.
1.2 Missing character , dot or icon.
1.3 Display malfunction.
1.4 N o func ti on or no display.
1.5 Current consumption exceeds product specifications.
1.6 Viewing angle defect.
1.7 Mixed product types.
1.8 C ontr as t de fec t.
0.65
02 Black or
white spots
(display only)
2.1 Whit e and black spots on dis pl ay ≦0.2 5m m, no more
than three white or black spots present.
2.2 Densely spaced: No more than two spots or lines within
3mm
2.5
03
Black spots,
white spots,
contaminatio
n
(non-display)
3.1 Round type : As
following drawing
Φ=( x + y ) / 2
SIZE
Acceptable Q
TY
Φ
≦
0.10
Accept no
dense
0.10
＜
Φ≦0.20
2
0.20
＜
Φ
≦
0.25
1
0.25
＜
Φ
0
2.5
3.2 Line ty pe : (As foll o wing drawing)
Length
Width
Acceptable Q
TY
---
W
≦
0.02
Accept no
dense
L
≦
3.0
0.02
＜
W
≦
0.03
2
L
≦
2.5
0.03
＜
W
≦
0.05
---
0.05
＜
W
As round type
2.5
04 Polarizer
bubbles
If bubbles are visible,
judge using black spot
speci ficati o ns , not
easy to find, mus t
check in specify
direction.
Size Φ
Acceptable Q
TY
Φ
≦
0.20
Accept no
dense
0.20
＜
Φ
≦
0.50
3
0.50
＜
Φ
≦
1.00
2
1.00
＜
Φ
0
Total Q TY
3
2.5
NO
Item
Criterion
AQL
05
Scratches
Follow NO.3 B lack spots, white spots, contamination
06 Chipped
glass
Symbols Define:
x: Chip length y: Chip width z: Chip thickness
k: Seal width t: Glass thickness a: Side length
L: Electrode pad length:
6.1 General glass chip :
6.1.1 Chip on panel surface and crack between panels:
z: Chip thickness
y: Chip width
x: Chip length
Z
≦
1/2t
Not over viewing
area
x
≦
1/8a
1/2t
＜
z
≦
2t
Not exceed 1/3k
x
≦
1/8a
☉If there are 2 or more chips, x is total length of each chip.
6.1.2 Corner crack:
z: Chip thickness
y: Chip width
x: Chip length
Z
≦
1/2t
Not over viewing
area
x
≦
1/8a
1/2t
＜
z
≦
2t
Not exceed 1/3k
x
≦
1/8a
☉If there are 2 or more chips, x is the total length of each chip.
2.5
NO
Item
Criterion
AQL
06 Glass
crack
Symbols :
x: Chip length y: Chip width z: Chip thickness
k: Seal width t: Glass thickness a: Side length
L: Electrode pad length
6.2 Protrusion over terminal :
6.2.1 Chip on el ectr ode p ad :
y: Chip width
x: Chip length
z: Chip thickness
y
≦
0.5mm
x
≦
1/8a
0
＜
z
≦
t
6.2.2 Non-conductive portion:
y: Chip width
x: Chip length
z: Chip
thickness
y
≦
L
x
≦
1/8a
0
＜
z
≦
t
☉If the chipped area touches the ITO terminal, over 2/3 of the
ITO must remain and be inspected according to electrode
terminal specifications.
☉If the product will be heat sealed by the customer, the
alignment mark not be damaged.
6.2.3 Substrate protuberance and internal crack.
y: width
x: length
y
≦
1/3L
x
≦
a
2.5
NO
Item
Criterion
AQL
07
Cracked
glass
With extensive crack is not acceptable. 2.5
08 Backlight
elements
8.1 Illumination source flickers when lit.
8.2 Spots or scratched that appear when lit must be judged.
Using Spot, lines and contamination standards.
8.3 Backlight doesn’t light or color wrong.
0.65
2.5
0.65
09 Bezel
9.1 Bezel may not have rust, be deformed or have
fingerprints, stains or other contamination.
9.2 Bezel must comply with job specifications.
2.5
0.65
10 PCB、COB
10.1 COB seal may not have pinholes larger than 0.2mm or
contamination.
10.2 COB seal surface may not have pinholes through to the
IC.
10.3 The hei g ht of the C OB should not exceed the height
indicated in the assembly diagram.
10.4 There may not be more than 2mm of sealant outside
the seal area on the PCB. And there should be no more
than three places.
10.5 No oxidation or contamination PCB terminals.
10.6 Parts on PCB must be the same as on the production
characteristic chart. There should be no wrong parts,
missing parts or excess parts.
10.7 The jumper on the PCB should conform to the product
characteristic chart.
10.8 If solder gets on bezel tab pads, LED pad, zebra pad or
screw hold pad, make sure it is smoothed down.
2.5
2.5
0.65
2.5
2.5
0.65
0.65
2.5
11 Soldering
11.1 No un-melted solder paste may be present on the PCB.
11.2 No cold solder joints, missing solder connections,
oxidation or icicle.
11.3 No residue or solder balls on PCB.
11.4 No short circuits in components on PCB.
2.5
2.5
2.5
0.65
NO
Item
Criterion
AQL
12 General
appearance
12.1 No oxidation, contamination, curves or, bends on
interface Pin (OLB) of TCP.
12.2 No cracks on interface pin (OLB) of TCP.
12.3 No contamination, solder residue or solder balls on
product.
12.4 The IC on the TCP may not be damaged, circuits.
12.5 The uppermost edge of the protective strip on the
interface pin must be present or look as if it cause the
interface pin to sever.
12.6 The residual rosin or tin oil of soldering (component or
chip component) is not burned into brown or black color.
12.7 Sealant on top of the ITO circuit has not hardened.
12.8 Pin type must match type in specification sheet.
12.9 Pin loose or missing pins.
12.10 Product packaging must the same as specified on
packaging specification sheet.
12.11 Product dimension and structure must conform to
product specification sheet.
2.5
0.65
2.5
2.5
2.5
2.5
2.5
0.65
0.65
0.65
0.65
Pattern Check (Display On) in Active Area
Document Number: 91000 www.vishay.com
Revision: 11-Mar-11 1
Disclaimer
Legal Disclaimer Notice
Vishay
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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