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FEATURES
10 years minimu m data retent ion in the
absence o f exter na l po wer
Dat a is aut omatical ly pro tected during power
loss
D irectly replac es 2k x 8 volatile static RAM
or EE P R O M
Unlim ited writ e cycles
Low-power CMOS
JEDEC standard 24-pin DI P p ackag e
Read and wr it e acces s times of 100 ns
Lit hiu m e nergy so ur ce is electrical ly
disconn ected to retain freshness un til power
is a ppl ie d for the fir s t time
Full ±10% VCC o perating range (DS1220AD)
Optional ±5% VCC o per at ing range
(DS1220AB)
Optional industr ial temperature range of
-40°C to +85°C, designated IND
PIN ASSIGNMENT
24-Pin ENC APSULATE D PACKAGE
720-mil EXTENDED
PIN DESCRIPTION
A0-A10 - Address Inputs
DQ0-DQ7 - Data I n/Dat a Out
CE
- Chip Enable
WE
- Wr ite E nable
OE
- Output Enable
VCC - Po wer (+5V )
GND - Ground
DESCRIPTION
The DS1220AB and DS1220AD 16k Nonvolatile SRAMs are 16,384-bit, fu lly st atic, non volatile SRAM s
organized as 2048 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and
c ontr ol c irc uitry wh i ch c on s ta n tly mon itor s V CC fo r a n o ut-of-t o ler a nc e c o nditio n. When s uch a c o nd ition
occurs, the lithium energy source is automatically switched on and write protection is unconditionally
enabled to prevent data corruption. The NV SRAMs can be used in place of existing 2k x 8 SRAMs
directly conforming to the popular bytewide 24-pin DIP standard. The devices also match the pinout of
the 2716 EPROM and the 2816 EEPROM, allowing direct substitution while enhancing performance.
There is no limit o n t he nu mber of write c ycles that can be e xecuted a nd no ad ditional support circu itry is
required for microp ro cessor interfacing.
DS1220AB/AD
16k Nonvolatile SRAM
19-5580; Rev 10/10
www.maxim-ic.com
14
VCC
WE
10
11
12
13
24
15
23
22
21
20
19
18
17
16
A7
A5
A3
A2
A1
A0
DQ0
DQ1
GND
DQ2
A6
A4
A8
A9
OE
A10
CE
DQ7
DQ6
DQ5
DQ3
DQ4
DS1220AB/AD
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READ MODE
The DS1220AB and DS1220AD execut e a read c ycle whenev er
WE
(Wr it e E nable) is inact ive (h igh) and
CE
(Chip Enable) and
OE
(Output Enable) are active (low). The unique address specified by the 11
address inputs (A0-A10) defines which of the 2048 bytes of data is to be accessed. Valid data will be
available to the eight data output drivers within tACC (Access Time) after the last address input signal is
stable, providing that the
CE
and
OE
access t imes are also satisfied. If
CE
and
OE
access times are not
satisfied, then data access must be measured fro m the lat er-o c cu rr ing s ig na l a nd t he li miting pa r a mete r is
either tCO for
CE
or tOE for
OE
rather than address acces s.
WRITE MODE
The DS1220AB and DS1220AD execut e a writ e cycle whenever t he
WE
and
CE
signals are act ive (low)
after address inputs are stable. The latter occurring falling edge of
CE
or
WE
will determine the start of
the wr it e cycle. The writ e cycle is terminated by the earlier r ising edge o f
CE
or
WE
. All address inputs
must be kept va lid t hro ug hout t he wr it e c ycle.
WE
must return to the high state for a minimum recovery
time (tWR ) before another cycle can be initiated. The
OE
control signal should be kept inactive (high)
during write cycles to avoid bus contention. However, if the output drivers are enabled (
CE
and
OE
act ive) t hen
WE
will disable the outp uts in tODW from its falling edge.
DATA RETENTION MODE
The DS1220AB provides full functional capability for VCC greater than 4.75 volts and write protects by
4.5V. T he DS1220AD provides full functional capability for VCC greater than 4.5 volt s a nd write pr ot ect s
by 4.25V. Data is maintained in the absence of VCC without any additional support circuitry. The
nonvolatile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs
automatically write protect themselves, all inputs become “don’t care,” and all outputs become high
impedance. As VCC falls below approximately 3.0 volts, a power switching circuit connects the lithium
energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts,
the power switching circuit connects external VCC to RAM and disconnects the lithium energy source.
No rmal RAM op erat ion can re sume a fter VCC exceeds 4.75 volts for the DS1220AB and 4.5 vo lt s fo r the
DS1220AD.
FRESH NESS SEAL
Each DS1220 device is shipped fro m Dallas Semiconductor with its lit hium energy source disconnected,
guaranteeing full energy capacity. When VCC is first applied at a level of greater than VTP, the lithium
energy so ur ce is ena bled for batt er y backup o per at io n.
DS1220AB/AD
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ABSOLUTE MAXIMUM RA TINGS
Voltage on Any Pin Relative to Ground -0 .3V to +6.0 V
Operating Temperat ur e Range
Commercial: 0°C to +70°C
Industrial: -40°C to +85°C
Stor ag e T emperat ur e -40°C to +85°C
Lead Temperature ( soldering, 10s) +260°C
Note: EDIP is wave or hand soldered only.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this
speci fi c ati on is not i m pli e d. E x pos ur e to absolut e maxi m um rating condi ti ons for extended per iods of time may af fect reli ability.
RECOMMENDED DC OPERATING CONDIT IONS (TA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
DS1220AB Power S upply Voltage
VCC
4.75
5.0
5.25
V
DS1220AD Po wer Supply Voltage
VCC
4.50
5.0
5.50
V
Log ic 1
VIH
2.2
VCC
V
Log ic 0
VIL
0.0
+0.8
V
DC ELECTRICAL CHARACTERISTICS (TA: See Note 10)
(VCC = 5V ± 5% for DS1220AB)
(VCC = 5V ± 10% for DS1220AD)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Leakage Cu r r ent
IIL
-1.0
+1.0
µA
I/O Leakage Cu r r ent
CE
≥ VIH ≤ VCC IIO
-1.0
+1.0 µA
Output Current @ 2.4V
IOH
-1.0
mA
Output Current @ 0.4V
IOL
2.0
mA
St andby Current
CE
= 2.2V ICCS1
5.0 10.0 mA
St andby Current
CE
=
VCC-0.5V
ICCS2
3.0 5.0 mA
Operating Current
(Commercial)
ICC01
75 mA
Operating Current
(Industrial)
ICCO1
85 mA
Write Protection Voltage
(DS1220AB)
VTP 4.5 4.62 4.75 V
Write Protection Voltage
(DS1220AD) VTP 4.25 4.37 4.5 V
CAPACITANCE (TA = +25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance
C
IN
5
10
pF
I npu t/O utput Ca pacita nc e
CI/O
5
12
pF
DS1220AB/AD
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AC ELECTRICAL CHARACTERISTICS (TA: See Note 10)
(VCC = 5.0V ± 5% for DS1220AB)
(VCC = 5.0V ± 10% for DS1220AD)
PARAMETER SYMBOL
DS1220AB-100
DS1220AD-100
UNITS NOTES
MIN
MAX
Re a d Cycle Time
t
RC
100
ns
Acce ss Time
tACC
100
ns
OE
t o Output Val id
tOE 50 ns
CE
to Output Va lid
tCO 100 ns
OE
or
CE
to Output Active
tCOE 5 ns 5
Outpu t High Z from
Deselection tOD 35 ns 5
Output Hold from Address Change
tOH
5
ns
Writ e Cycle Time
tWC
100
ns
Writ e P ulse Width
t
WP
75
ns
3
A ddress Setup Tim e
tAW
0
ns
Writ e Recovery Time
t
WR1
tWR2
0
10
ns
ns
12
13
Outpu t High f rom
WE
tODW 35 ns 5
Output Active from
WE
tOEW 5 ns 4
Da ta S etup T ime
tDS
40
ns
4
Da ta Hold Time
t
DH1
tDH2
0
10
ns
ns
12
13
DS1220AB/AD
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READ CYCLE
SEE NOTE 1
WRITE CYCLE 1
SEE NOTES 2, 3, 4, 6, 7, 8 AND 12
WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8 AND 13
DS1220AB/AD
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POWER-DOWN/POWER-UP CONDITION
SEE NOTE 11
POWER-DOWN/POWER-UP TIMING (TA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
VCC Fail Detect to
CE
and
WE
Inactive tPD 1.5 µs 11
VCC slew from VTP to 0V tF 300 µs
VCC slew from 0V to VTP tR 300 µs
VCC Valid to
CE
and
WE
Inactive tPU 2 ms
VCC Valid to E nd of Write Pr otection tREC 125 ms
(TA = +25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Expect ed Data Retention T ime
tDR
10
years
9
WARNING:
Under no circumstances are negative undershoots, of any amplitude, allowed when device is in the
battery backup mode.
NOTES:
1.
WE
is high for a read cycle.
2.
OE
= VIH or VIL. If
OE
= VIH d ur i ng write cycle, the o utput buffer s remain in a h igh-impedance stat e.
3. tWP is specified as the logical AND of
CE
and
WE
. tWP is measured from the latter of
CE
or
CE
go ing lo w t o t he ear lier o f
CE
or
WE
go ing h ig h.
4. tDS is measured fro m the ear lier of
CE
or
WE
going hig h.
5. T hese para met er s ar e sampled with a 5 pF lo ad an d ar e not 100 % tested .
6. I f the
CE
low transition occurs simultaneously with or later than the
WE
low transitio n, t he out put
buffe rs r emain in a high-impedance stat e during t his period.
7. If t he
CE
hig h t rans it io n o cc urs pr io r to or s imult a ne ou sly w it h t he
WE
high transit ion, t he output
buffers remain in a high-impedance stat e dur ing this period.
DS1220AB/AD
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8. If
WE
is low or th e
WE
low transition occurs prior to or simultaneously wit h the
CE
low t ran sition ,
the outp ut buf fer s remai n in a h igh-impedance state during this period.
9. Each DS1220AB and each DS1220AD has a built-in switc h that disconnects the lit hium source unt il
VCC is first applied by the user. The expected tDR is defined as accumulative time in the absence of
VCC st ar ting fro m t he t ime po wer is first applied by the user. This parameter is guaranteed by design
and is not 100% t est ed.
10. All AC and DC electrical characteristics are valid over the full operating temperature range. For
commercial products, this range is 0°C to 70°C. For industria l product s (IND), this range is -40°C to
+85°C.
11. In a p ower down c ondition the voltage on a ny pin may no t exc eed the voltage on V CC.
12. tWR1 , tDH1 are measured from WE going high.
13. tWR2 , tDH2 are measured from
CE
goi ng h ig h.
14. DS1220 modu les are recognized by Underwr iters Labor atories (UL) under file E99151.
DC TEST CONDITIONS
Output s Open
Cycle = 200ns for Operat ing Curr ent
All Voltag es Are Re fere nced t o G ro und
AC TEST CONDITIONS
Output Load: 100 pF + 1TTL Gate
Input Pulse Levels: 0 - 3.0V
Timing Measur ement Reference Levels
Input: 1.5V
Output : 1.5V
Input Pulse Rise and Fall Times: 5ns
ORDERING INFORMATION
PART TEMP RANGE
SUPPLY
TOLERANCE
PIN-PACKAGE
DS1220AB-100+
0°C to +70°C
5V ± 5%
24 720 EDIP
DS1220AB-100IND+
-40°C to +85°C
5V
±
5%
24 720 EDIP
DS1220AD-100+
0°C to +70°C
5V
±
10%
24 720 EDIP
DS1220AD-100IND+
-40°C to +85°C
5V ± 10%
24 720 EDIP
+Denotes a lead(Pb)-free/RoHS-compliant package.
PACKAGE INFORMATION
For the latest package outline informat ion and land patterns, go to www.maxim-ic.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a
d ifferent suffix character, but the drawing pertains to t he package r egar dless o f RoHS status.
PACKAGE TYPE PACK AG E CODE OUTLINE NO.
LAND
PATTERN NO.
24 EDIP MDT24+1 21-0245
DS1220AB/AD
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REVISION HISTORY
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
121907
Added packag e information t able ; remov ed th e DIP modu le package
dra wing and dimension table
9
10/10
Updated the storag e and soldering temperature inf ormation in the
Absolute Maximum Ratings section, removed the unused AC timing
specs in the AC Electrical Characteristics table, updated the Ordering
Information table, updated th e Package Information table
1, 3, 4, 7