K6R4008V1B-JC12 - Samsung - Datasheet.Live

K6R4008V1B-C/B-L, K6R4008V1B-I/B-P CMOS SRAM

PRELIMINARY

Rev 2.2

- 1 - May 1999

Document Title

512Kx8 Bit High Speed Static RAM(3.3V Operating).

Operated at Commercial and Industrial Temperature Ranges.

Revision History

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the

specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-

tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

Rev No.

Rev. 0.0

Rev. 1.0

Rev. 2.0

Rev. 2.1

Rev. 2.2

Remark

Design Target

Preliminary

Final

History

Initial release with Design Target.

Release to Preliminary Data Sheet.

1.1. Replace Design Target to Preliminary.

Release to Final Data Sheet.

2.1. Delete Preliminary.

2.2. Add 30pF capacitive in test load.

2.3. Relax DC characteristics.

Change operating current at Industrial Temperature range.

Previous spec. Changed spec.

Items (10/12/15ns part) (10/12/15ns part)

Icc 205/200/195mA 230/225/220mA

Add 44 pins plastic TSOP(II) forward Package.

Item Previous Current

ICC 10ns 170mA 205mA

12ns 160mA 200mA

15ns 150mA 195mA

ISB f=max. 40mA 50mA

ISB1 f=0 10 / 1mA 10 / 1.2mA

IDR VDR=3.0V 0.9mA 1.0mA

Draft Data

Jan. 1st, 1997

Jun. 1st, 1997

Feb.11th.1998

Jun.27th 1998

May. 4th 1999

K6R4008V1B-C/B-L, K6R4008V1B-I/B-P CMOS SRAM

PRELIMINARY

Rev 2.2

- 2 - May 1999

512K x 8 Bit High-Speed CMOS Static RAM(3.3V Operating)

GENERAL DESCRIPTIONFEATURES

• Fast Access Time 10,12,15ns(Max.)

• Low Power Dissipation

Standby (TTL) : 50mA(Max.)

(CMOS) : 10mA(Max.)

1.2mA(Max.)- L-Ver.

Operating K6R4008V1B-10 : 205mA(Max.)

K6R4008V1B-12 : 200mA(Max.)

K6R4008V1B-15 : 195mA(Max.)

• Single 3.3 ±0.3V Power Supply

• TTL Compatible Inputs and Outputs

• Fully Static Operation

- No Clock or Refresh required

• Three State Outputs

• 2V Minimum Data Retention ; L-Ver. only

• Center Power/Ground Pin Configuration

• Standard Pin Configuration

K6R4008V1B-J : 36-SOJ-400

K6R4008V1B-T: 36-TSOP2-400F

K6R4008V1B-U: 44-TSOP2-400AF

Clk Gen.

I/O1~I/O8

FUNCTIONAL BLOCK DIAGRAM

Row Select

Data

Cont. Column Select

CLK

Gen.

Pre-Charge Circuit

Memory Array

512 Rows

1024x8 Columns

I/O Circuit PIN FUNCTION

Pin Name Pin Function

A0 - A18 Address Inputs

WE Write Enable

CS Chip Select

OE Output Enable

I/O1 ~ I/O8Data Inputs/Outputs

VCC Power(+3.3V)

VSS Ground

N.C No Connection

The K6R4008V1B is a 4,194,304-bit high-speed Static Random

Access Memory organized as 524,288 words by 8 bits. The

K6R4008V1B uses 8 common input and output lines and has

an output enable pin which operates faster than address

access time at read cycle. The device is fabricated using SAM-

SUNG′s advanced CMOS process and designed for high-

speed circuit technology. It is particularly well suited for use in

high-density high-speed system applications. The

K6R4008V1B is packaged in a 400 mil 36-pin plastic SOJ or

TSOP(II) forward or 44-pin plastic TSOP(II) forward.

A10 A12 A14 A16 A18

K6R4008V1B-C10/C12/C15 Commercial Temp.

K6R4008V1B-I10/I12/I15 Industrial Temp.

ORDERING INFORMATION

A9 A11 A13 A15 A17

K6R4008V1B-C/B-L, K6R4008V1B-I/B-P CMOS SRAM

PRELIMINARY

Rev 2.2

- 3 - May 1999

PIN CONFIGURATION(Top View)

36-SOJ/

N.C

A18

A17

A16

A15

I/O8

I/O7

Vss

Vcc

I/O6

I/O5

A14

A13

A12

A11

A10

N.C

I/O1

I/O2

Vcc

Vss

I/O3

I/O4

TSOP2

PIN FUNCTION

Pin Name Pin Function

A0 - A18 Address Inputs

WE Write Enable

CS Chip Select

OE Output Enable

I/O1 ~ I/O8Data Inputs/Outputs

VCC Power(+3.3V)

VSS Ground

N.C No Connection

N.C

I/O1

I/O2

Vcc

Vss

I/O3

I/O4

N.C

A18

A17

A16

A15

I/O8

I/O7

Vss

Vcc

I/O6

I/O5

A14

A13

A12

A11

A10

N.C

44-TSOP2

ABSOLUTE MAXIMUM RATINGS*

* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Parameter Symbol Rating Unit

Voltage on Any Pin Relative to VSS VIN, VOUT -0.5 to 4.6 V

Voltage on VCC Supply Relative to VSS VCC -0.5 to 4.6 V

Power Dissipation PD1.0 W

Storage Temperature TSTG -65 to 150 °C

Operating Temperature Commercial TA0 to 70 °C

Industrial TA-40 to 85 °C

K6R4008V1B-C/B-L, K6R4008V1B-I/B-P CMOS SRAM

PRELIMINARY

Rev 2.2

- 4 - May 1999

DC AND OPERATING CHARACTERISTICS*(TA=0 to 70°C, Vcc=3.3±0.3V, unless otherwise specified)

* The above parameters are also guaranteed at industrial temperature range.

Parameter Symbol Test Conditions Min Max Unit

Input Leakage Current ILI VIN=VSS to VCC -2 2µA

Output Leakage Current ILO CS=VIH or OE=VIH or WE=VIL

VOUT=VSS to VCC -2 2µA

Operating Current ICC Min. Cycle, 100% Duty

CS=VIL, VIN=VIH or VIL, IOUT=0mA 10ns -205 mA

12ns -200

15ns -195

Standby Current ISB Min. Cycle, CS=VIH -50 mA

ISB1 f=0MHz, CS≥VCC-0.2V,

VIN≥VCC-0.2V or VIN≤ 0.2V Normal -10 mA

L-Ver. -1.2

Output Low Voltage Level VOL IOL=8mA -0.4 V

Output High Voltage Level VOH IOH=-4mA 2.4 -V

CAPACITANCE*(TA=25°C, f=1.0MHz)

* Capacitance is sampled and not 100% tested.

Item Symbol Test Conditions MIN Max Unit

Input/Output Capacitance CI/O VI/O=0V -8pF

Input Capacitance CIN VIN=0V -7pF

RECOMMENDED DC OPERATING CONDITIONS*(TA=0 to 70°C)

* The above parameters are also guaranteed at industrial temperature range.

** VIL(Min) = -2.0V a.c(Pulse Width ≤ 8ns) for I ≤ 20mA.

*** VIH(Max) = VCC + 2.0V a.c (Pulse Width ≤ 8ns) for I ≤ 20mA.

Parameter Symbol Min Typ Max Unit

Supply Voltage VCC 3.0 3.3 3.6 V

Ground VSS 0 0 0 V

Input High Voltage VIH 2.0 -VCC+0.3*** V

Input Low Voltage VIL -0.3** -0.8 V

K6R4008V1B-C/B-L, K6R4008V1B-I/B-P CMOS SRAM

PRELIMINARY

Rev 2.2

- 5 - May 1999

READ CYCLE*

* The above parameters are also guaranteed at industrial temperature range.

Parameter Symbol K6R4008V1B-10 K6R4008V1B-12 K6R4008V1B-15 Unit

Min Max Min Max Min Max

Read Cycle Time tRC 10 -12 -15 -ns

Address Access Time tAA -10 -12 -15 ns

Chip Select to Output tCO -10 -12 -15 ns

Output Enable to Valid Output tOE -5-6-7ns

Chip Enable to Low-Z Output tLZ 3-3-3-ns

Output Enable to Low-Z Output tOLZ 0-0-0-ns

Chip Disable to High-Z Output tHZ 050607ns

Output Disable to High-Z Output tOHZ 050607ns

Output Hold from Address Change tOH 3-3-3-ns

Chip Selection to Power Up Time tPU 0-0-0-ns

Chip Selection to Power DownTime tPD -15 -12 -15 ns

TEST CONDITIONS*

* The above test conditions are also applied at industrial temperature range.

Parameter Value

Input Pulse Levels 0V to 3V

Input Rise and Fall Times 3ns

Input and Output timing Reference Levels 1.5V

Output Loads See below

AC CHARACTERISTICS(TA=0 to 70°C, VCC=3.3±0.3V, unless otherwise noted.)

Output Loads(B)

DOUT

5pF*

319Ω

353Ω

for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ

+3.3V

* Including Scope and Jig Capacitance

Output Loads(A)

DOUT RL = 50Ω

ZO = 50Ω

VL = 1.5V

30pF*

* Capacitive Load consists of all components of the

test environment.

K6R4008V1B-C/B-L, K6R4008V1B-I/B-P CMOS SRAM

PRELIMINARY

Rev 2.2

- 6 - May 1999

WRITE CYCLE*

* The above parameters are also guaranteed at industrial temperature range.

Parameter Symbol K6R4008V1B-10 K6R4008V1B-12 K6R4008V1B-15 Unit

Min Max Min Max Min Max

Write Cycle Time tWC 10 -12 -15 -ns

Chip Select to End of Write tCW 7-8-10 -ns

Address Set-up Time tAS 0-0-0-ns

Address Valid to End of Write tAW 7-8-10 -ns

Write Pulse Width(OE High) tWP 7-8-10 -ns

Write Pulse Width(OE Low) tWP1 10 -12 -15 -ns

Write Recovery Time tWR 0-0-0-ns

Write to Output High-Z tWHZ 0 5 0 6 0 7 ns

Data to Write Time Overlap tDW 5-6-7-ns

Data Hold from Write Time tDH 0-0-0-ns

End Write to Output Low-Z tOW 3-3-3-ns

Address

Data Out Previous Valid Data Valid Data

TIMMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)

tAA

tRC

tOH

NOTES(READ CYCLE)

1. WE is high for read cycle.

2. All read cycle timing is referenced from the last valid address to the first transition address.

3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or

VOL levels.

4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to

device.

5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.

6. Device is continuously selected with CS=VIL.

7. Address valid prior to coincident with CS transition low.

8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

Address

Data out

tAA

tOLZ

tLZ(4,5) tOH

tOHZ

tRC

tOE

tCO

tPU tPD

Valid Data

tHZ(3,4,5)

50%

VCC

Current

ICC

ISB

K6R4008V1B-C/B-L, K6R4008V1B-I/B-P CMOS SRAM

PRELIMINARY

Rev 2.2

- 7 - May 1999

TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)

Address

tWP(2)

tDW tDH

Valid Data

Data in

Data out

tWC

tWR(5)

tAW

tCW(3)

High-Z(8)

High-Z

tOHZ(6)

tAS(4)

TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed)

Address

tWP1(2)

tDW tDH

tOW

tWHZ(6)

Valid Data

Data in

Data out

tWC

tAS(4)

tWR(5)

tAW tCW(3)

(10) (9)

High-Z(8)

High-Z

TIMING WAVEFORM OF WRITE CYCLE(3) (CS = Controlled)

Address

tAW

tDW tDH

Valid Data

Data in

Data out High-Z High-Z(8)

tCW(3)

tWP(2)tAS(4)

tWC

tWR(5)

High-Z

tLZ tWHZ(6)

K6R4008V1B-C/B-L, K6R4008V1B-I/B-P CMOS SRAM

PRELIMINARY

Rev 2.2

- 8 - May 1999

NOTES(WRITE CYCLE)

1. All write cycle timing is referenced from the last valid address to the first transition address.

2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ;

A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of

write.

3. tCW is measured from the later of CS going low to end of write.

4. tAS is measured from the address valid to the beginning of write.

5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.

6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase

of the output must not be applied because bus contention can occur.

7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.

9. Dout is the read data of the new address.

10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be

applied.

FUNCTIONAL DESCRIPTION

* X means Don′t Care.

CS WE OE Mode I/O Pin Supply Current

HXX* Not Select High-Z ISB, ISB1

LH H Output Disable High-Z ICC

LHLRead DOUT ICC

L L XWrite DIN ICC

DATA RETENTION CHARACTERISTICS*(TA=0 to 70°C)

* The above parameters are also guaranteed at industrial temperature range.

Data Retention Characteristic is for L-ver only.

Parameter Symbol Test Condition Min. Typ. Max. Unit

VCC for Data Retention VDR CS ≥ VCC - 0.2V 2.0 -3.6 V

Data Retention Current IDR VCC=3.0V, CS≥VCC - 0.2V

VIN≥VCC - 0.2V or VIN≤ 0.2V - - 1.0 mA

VCC = 2.0V, CS≥VCC - 0.2V

VIN≥VCC - 0.2V or VIN≤0.2V - - 0.7 mA

Data Retention Set-Up Time tSDR See Data Retention

Wave form(below) 0- - ns

Recovery Time tRDR 5- - ms

DATA RETENTION WAVE FORM

VCC

3.0V

VIH

VDR

GND

Data Retention Mode

CS≥VCC - 0.2V

tSDR tRDR

CS controlled

K6R4008V1B-C/B-L, K6R4008V1B-I/B-P CMOS SRAM

PRELIMINARY

Rev 2.2

- 9 - May 1999

PACKAGE DIMENSIONS Units:millimeters/Inches

36-TSOP2-400F

#19

#18

0.075 MAX

0.10 MAX

1.00

0.039

#36

#1 +0.10

0.15 -0.05

+0.004

0.006 -0.002

11.76 ±0.20

0.463 ±0.008

(0.50)

(0.020)

18.41 ±0.10

0.725 ±0.004

MAX

18.81

0.741

MAX

1.20

0.047

MIN

0.002

0.05

(0.705)

(0.028) 0.40 ±0.10

0.016 ±0.004

0~8°

TYP

0.45 ~0.75

0.018 ~ 0.030

1.00 ±0.10

0.039 ±0.004

10.16

0.400

36-SOJ-400

#36

23.50 ±0.12

0.925 ±0.005

MAX

23.90

0.941

MAX

0.148

3.76

1.19

( )

0.047

1.27

( )

0.050

0.95

( )

0.0375

+0.10

0.43 -0.05

+0.004

0.017 -0.002 +0.10

0.71 -0.05

+0.004

0.028 -0.002

1.27

0.050

#18

#19

10.16

0.400

+0.10

0.20 -0.05

+0.004

0.008 -0.002

9.40 ±0.25

0.370 ±0.010

MIN

0.69

0.027

0.004

0.10 MAX

11.18 ±0.12

0.440 ±0.005

K6R4008V1B-C/B-L, K6R4008V1B-I/B-P CMOS SRAM

PRELIMINARY

Rev 2.2

- 10 May 1999

44-TSOP2-400AF

0.002

0.05

#22

#44 #23

0.35 ±0.10

0.014 ±0.004 0.80

0.0315 MIN.

0.047

1.20 MAX.

0.741

18.81MAX.

18.41 ±0.10

0.725 ±0.004

11.76 ±0.20

0.463 ±0.008

+ 0.10

- 0.05

0.50

+ 0.004

- 0.002

0.15

0.006

0.020

10.16

0.400

0.10

0.004

0~8°

0.45 ~0.75

0.018 ~ 0.030

0.25

( )

0.010

( )

0.805

0.032

( )

MAX

1.00 ±0.10

0.039 ±0.004