AW2600CR2IOS - INTEL - Datasheet.Live

1. General description

The PCA9617A is a CMOS integrated circuit that provides level shifting between low

voltage (0.8 V to 5.5 V) and higher voltage (2.2 V to 5.5 V) Fast-mode Plus (Fm+) I2C-bus

or SMBus applications. While retaining all the operating modes and features of the

I2C-bus system during the level shif ts, it also permit s extension of the I2C-bus by providing

bidirectional bu ffering for both the dat a (SDA) a nd the clock (SCL) lines, thus enabling two

buses of 540 pF at 1 MHz or up to 4000 pF at lower speeds. Using the PCA9617A

enables the system designer to isolate two halves of a bus for both voltage and

capacitance. The SDA and SCL pins are overvoltage tolerant and are high-impedance

when the PCA9617A is unpowered.

The 2.2 V to 5.5 V bus port B drivers have the static level offset, while the adjust able

voltage bus port A drivers eliminate the static offset voltage. This results in a LOW on the

port B translating into a nearly 0 V LOW on the port A which accommodates the smaller

voltage swings of lower voltage logic.

The static offset design of the port B PCA9617A I/O drivers prevents them from being

connected to the static or incremented offset of other bus buffers. Port A of two or more

PCA9617As can be connected together, however, to allow a star topography with port A

on the common bus, and po rt A can be connected directly to any othe r buffe r with static or

incremented offset outputs. Multiple PCA9617As can be connected in series, port A to

port B, with no build-up in offset voltage with only time of flight delays to consider.

The PCA9617A drive rs ar e no t en ab le d un les s VCC(A) is above 0.8 V and VCC(B) is above

2.2 V. The EN pin is referenced to VCC(B) and can also be used to turn the drivers on and

off under system control. Caution should be observed to only change the state of the

enable pin when the bus is idle.

The output pull-down on the port B internal buffer LOW is set for approximately 0.55 V,

while the input threshold o f the internal buf fer is set about 90 mV lower (0.45 V). When the

port B I/O is driven LOW internally, the LOW is not recognized as a LOW by the input.

This prevents a latching condition from occurring. The output pull-down on port A drives a

hard LOW and the input level is set at 0.35VCC(A) to accommodate the need for a lower

LOW level in systems where th e low voltage side su pply voltage is as low as 0.8 V.

2. Features and benefits

2 channel, bidirectional buffer isolates capacitance and allows 54 0 pF on either side of

the device at 1 MHz and up to 4000 pF at lower speeds

Voltage level translation from 0.8 V to 5.5 V and from 2.2 V to 5.5 V

Footprint and functional replacement for PCA9517A at Fast-mode speeds

Port A operating supply voltage range of 0.8 V to 5.5 V with normal levels

PCA9617A

Level translating F m+ I2C-bus repeater

Rev. 1 — 20 March 2013 Product data sheet

Product data sheet Rev. 1 — 20 March 2013 2 of 23

NXP Semiconductors PCA9617A

Level translating Fm+ I2C-bus repeater

Port B operating supply voltage range of 2.2 V to 5.5 V with static offset level

5V tolerant I

2C-bus and enable pins

0 Hz to 1000 kHz clock frequency (the maximum system operating frequency may be

less than 1000 kHz because of the delays added by the repeater)

Active HIGH repeater enable input referenced to VCC(B)

Open-drain input/outputs

Latching free operation

Supports arbitration an d cloc k stre tching across th e re pe a ter

Accommodates Standard-mode, Fast-mode and Fast-mode Plus I2C-bus devic es,

SMBus (standard and high power mode), PMBus and multiple masters

Powered-off high-impedance I2C-bus pins

ESD protection exceeds 5500 V HBM per JESD22-A114 and 1000 V CDM per

JESD22-C101

Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

Packages offered: TSSOP8 and HWSON8

3. Ordering information

[1] Also known as MSOP8.

3.1 Ordering options

Table 1. Ordering information

Tamb =





C to +85



Type number Topside

mark Package

Name Description Version

PCA9617ADP P617A TSSOP8[1] plastic thin shrink sma ll outline package; 8 leads;

body width 3 mm SOT505-1

PCA9617ATP P7A HWSON8 plastic thermal enhanced very very thin small outline package;

no leads; 8 terminals; body 2 30.8 mm SOT1069-2

Table 2. Ordering options

Type number Orderable

part number Package Packing method Minimum

order

quantity

Temperature range

PCA9617ADP PCA9617ADPJ TSSOP8 Reel 13” Q1/T1

*standard mark SMD 2500 Tamb =40 C to +85 C

PCA9617ATP PCA9617ATPZ HWSON8 Reel 7” Q2/T3 *standard mark 4000 Tamb =40 C to +85 C

Product data sheet Rev. 1 — 20 March 2013 3 of 23

NXP Semiconductors PCA9617A

Level translating Fm+ I2C-bus repeater

4. Functional diagram

Fig 1. Functional diagram of PCA9617A

002aag641

PCA9617A

SDAA

SCLA

SDAB

SCLB

VCC(A) VCC(B)

GND

VCC(B)

pull-up

resistor

Product data sheet Rev. 1 — 20 March 2013 4 of 23

NXP Semiconductors PCA9617A

Level translating Fm+ I2C-bus repeater

5. Pinning information

5.1 Pinning

5.2 Pin description

[1] HWSON8 package die supply ground is connected to both GND pin and exposed center pad. GND pin

must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and

board level performance, the exposed pad needs to be soldered to the board using a corresponding

thermal pad on the board and for proper head conduction through the board, thermal vias need to be

incorporated in the printed-circuit board in the thermal pad region.

Fig 2. Pin confi gura tio n for TSSOP8

(MSOP8) Fig 3. Pin configuration for HWSON8

PCA9617ADP

VCC(A) VCC(B)

SCLA SCLB

SDAA SDAB

GND EN

002aag643

terminal 1

index area

1SDAA

PCA9617ATP

002aag644

Transparent top view

2GND

3EN

5SDAB

SCLA

VCC(A)

VCC(B)

SCLB

Table 3. Pin description

Symbol Pin Description

TSSOP8 HWSON8

VCC(A) 1 7 port A supply voltage (0.8 V to 5.5 V)

SCLA 2 8 serial clock port A bus

SDAA 3 1 serial data port A bus

GND 4 2[1] supply ground (0 V)

EN 5 3 active HIGH repeater enable input

SDAB 6 4 serial data port B bus

SCLB 7 5 serial clock port B bus

VCC(B) 8 6 port B supply voltage (2.2 V to 5.5 V)

Product data sheet Rev. 1 — 20 March 2013 5 of 23

NXP Semiconductors PCA9617A

Level translating Fm+ I2C-bus repeater

6. Functional description

Refer to Figure 1 “Functional diagram of PCA9617A”.

The PCA9617A enables I2C-bus or SMBus translation down to VCC(A) as low as 0.8 V

without degradation of system performance. The PCA9617A contains two bidirectional

open-drain buffers specifically designed to support up-translation/down-translation

between the low volt age (as low as 0.8 V) and a 2.5 V, 3.3 V or 5 V I2C-bus or SMBus. All

inputs and I/Os are overvoltage tolerant to 5.5 V even when the device is unpowered

(VCC(B) and/or VCC(A) = 0 V). The PCA9617A includes a power-up circuit that keeps the

output drivers turned off until VCC(B) is above 2.2 V and until after the internal reference

circuits have settled ~400 s, and the VCC(A) is above 0.8 V. VCC(B) and VCC(A) can be

applied in any sequence at power-up. After power-up and with the enable (EN) HIGH, a

LOW level on port A (below 0. 3VCC(A)) turns the correspondin g port B driver (either SDA

or SCL) on and drives port B down to about 0.55 V. When port A rises above 0.3VCC(A),

the port B pull-down driver is turned off and the external pull-up resistor pulls the pin

HIGH. When port B falls first and goes below 0.4 V, the port A driver is turned on and

port A pulls down to ~0 V. The port A pull-down is not enabled unless the port B voltage

goes below 0.4 V. If the port B low voltage goes below 0.4 V, the port B pull-down driver is

enabled and port B will only be able to rise to 0.55 V until port A rises above 0.3VCC(A),

then port B will continue to rise being pulled up by the external pull-up resistor. The VCC(A)

is only used to provide the 0.35VCC(A) reference to the port A in p ut comparato rs and fo r

the power good detect circuit. The PCA9617A includes a VCC(A) overvoltage disable that

turns the channel off if 0.4VCC(A) +0.8V>V

CC(B). The PCA9617A logic and all I/Os are

6.1 Enable

The EN pin is active HIGH with thresholds referenced to VCC(B) and an internal pull-up to

VCC(B) that maintains the device active unless the user selects to disable the repeater to

isolate a badly behave d slave on power-up until af ter the system power -up reset. It should

never change st ate dur ing an I2C- bus operatio n because disablin g during a bus operatio n

will hang the bus and enabling part way through a bus cycle could confuse the I2C-bus

parts being enabled. The enable does not switch the internal reference circuits so the

~400 s delay is only seen when VCC(B) comes up.

The enable pin sh ould o nly change state when th e globa l bus and the repe ater port a re in

an idle state to prevent system failures.

6.2 I2C-bus systems

As with the standard I2C-bus system, pull-u p resistors are required to provide the logic

HIGH levels on the buffered bus (standard open-collector configuration of the I2C-bus).

The size of these pull-up resistors depends on the system, but each side of the repeater

must have a pull-up resistor. This part designed to work with Standard mode, Fast-mode

and Fast-mode Plus I2C-bus devices in addition to SMBus devices. Standard mode and

Fast-mode I2C-bus devices only specify 3 mA output drive; this limits the termination

current to 3 mA in a generic I2C-bus system where Standard-mode devices, Fast-mode

devices and multiple masters are possible. When only Fast-mode Plus devices are used

with 30 mA at 5 V drive strength, then lower value pull-up resistors can be used. The

Product data sheet Rev. 1 — 20 March 2013 6 of 23

NXP Semiconductors PCA9617A

Level translating Fm+ I2C-bus repeater

B-side RC should not be less than 67.5 ns because shorter RCs increase the turnaround

bounce when the B-side transitions from being externally driven to pulled down by its

offset buffer.

Please see Application Note AN255, “I2C/SMBus Repeaters, Hubs and Expanders” for

additional information on sizing resistors and precautions when using more than one

PCA9617A in a system or using the PCA9617A in conjunction with other bus buffers.

7. Application design-in information

A typical application is shown in Figure 4. In this example, the system master is running

on a 3.3 V I2C -bus while the slave is connec t ed to a 1.2 V bu s. Bo th bu se s ru n at

1000 kHz. Master devices can be placed on either bus.

The PCA9617A is 5 V tolerant, so it does not require any additional circuitry to translate

between 0.8 V to 5.5 V bus voltages and 2.2 V to 5.5 V bus voltages.

When port A of the PCA9617A is pulled LOW by a driver on the I2C-bus, a comparator

detects the falling edge when it goes below 0.3VCC(A) and causes the int er na l driv er on

port B to turn on, causing port B to pull down to about 0.5 V. When port B of the

PCA9617A falls, first a CMOS hysteresis type input detects the falling edge and causes

the internal driver on port A to turn on and pull the port A pin down to ground. In order to

illustrate what would be seen in a typical application, refer to Figure 8 and Figure 9. If the

bus master in Figure 4 were to write to the slave through the PCA9617A, waveforms

shown in Figure 8 would be observed on the A bus. This looks like a normal I2C-bus

transmission except that the HIGH level may be as low as 0.8 V, and the turn on and turn

off of the acknowledge signals are slightly delayed.

The internal comparator requires that 0.4 VCC(A) be less than or equal to VCC(B) 0.8 V

for the device to operate. Since A port is 5 V tolerant, the VCC(A) can be lowered to support

device spectrum while still supporting 5 V signals on the A port.

On the B bus side of the PCA9617A, the clock and dat a lines wou ld have a p ositive of fse t

from ground equal to the V OL of the PCA9617A. After the eigh th clock pulse, the dat a line

will be pulled to the VOL of the slave device which is very close to ground in this example.

At the end of the acknowledge, the level rises only to the LOW level set by the driver in the

PCA9617A for a short de lay while th e A bus side rises above 0. 3VCC(A) then it continues

Fig 4. Typical application

002aag653

VCC(A)

VCC(B)

PCA9617A

SDAB SDAA

SCLB SCLA

1.4 kΩ 1.4 kΩ

SDA

SCL

BUS

MASTER

1000 kHz

SLAVE

1000 kHz

SDA

SCL

bus B bus A

1.2 V

3.3 V

1.4 kΩ 1.4 kΩ

Product data sheet Rev. 1 — 20 March 2013 7 of 23

NXP Semiconductors PCA9617A

Level translating Fm+ I2C-bus repeater

HIGH. It is import ant to note that any arbitrat ion or clock stretch ing event s require th at the

LOW level on the B bus side at the input of the PCA9617A (VIL) be at or below 0.4 V to be

recognized by the PCA9617A and then transmitted to the A bus side.

Multiple PCA9617A port A sides can be connected in a star configuration (Figure 5),

allowing all nodes to communicate with each other.

Multiple PCA9617As can be connected in series (Figure 6) as long as port A is connected

to port B. I2C-bus slave devices can be connected to any of th e bus segments. The

number of devices that can be connected in series is limited by repeater

delay/time-of-flight considerations on the maximum bus speed requirements.

Fig 5. Typical star application

VCC(B)

VCC(A)

PCA9617A

SDAA SDAB

SCLA SCLB

1.4 kΩ 1.4 kΩ

SDA

SCL

BUS

MASTER SLAVE

1000 kHz

SDA

SCL

VCC(B)

VCC(A)

1.4 kΩ 1.4 kΩ

VCC(B)

VCC(A)

PCA9617A

SDAA SDAB

SCLA SCLB

1.4 kΩ 1.4 kΩ

SLAVE

1000 kHz

SDA

SCL

002aag645

VCC(B)

VCC(A)

PCA9617A

SDAA SDAB

SCLA SCLB

1.4 kΩ 1.4 kΩ

SLAVE

1000 kHz

SDA

SCL

Product data sheet Rev. 1 — 20 March 2013 8 of 23

NXP Semiconductors PCA9617A

Level translating Fm+ I2C-bus repeater

Decoupling capacitors not shown for simplicity, but they are required. It is especially important that the decoupling for the

PCA9617A VCC(B) be close to the VCC(B) pin.

Fig 6. Typical series application

002aag646

PCA9617A

SDAA SDAB

SCLA SCLB

SDA

SCL

BUS

MASTER SLAVE

1000 kHz

SDA

SCL

1.4 kΩ 1.4 kΩ

PCA9617A

SDAA SDAB

SCLA SCLB

VCC

PCA9617A

SDAA SDAB

SCLA SCLB

1.4 kΩ 1.4 kΩ 1.4 kΩ 1.4 kΩ 1.4 kΩ 1.4 kΩ

Decoupling capacitors not shown for simplicity, but they are required. It is especially important that

the decoupling for the PCA9617A VCC(B) be close to the VCC(B) pin.

Fig 7. Typical application of PCA9617A driving a short cable

002aag647

CC(B)

CC(A)

SDAA SDAB

SCLA SCLB

10 kΩ 10 kΩ

CC(B)

CC(A)

RPU

GND

75 Ω

RPU 10 kΩ

(optional)

MASTER

SLAVE

CARD 1

CARD 2

Product data sheet Rev. 1 — 20 March 2013 9 of 23

NXP Semiconductors PCA9617A

Level translating Fm+ I2C-bus repeater

8. Limiting values

Fig 8. Bus A (0.8 V to 5.5 V bus) waveform

Fig 9. Bus B (2.2 V to 5.5 V) waveform

002aac775

9th clock pulse

acknowledge

SCL

SDA

002aag648

9th clock pulse

acknowledge

SCL

SDA

VOL of slave

VOL of PCA9617A

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VCC(B) supply voltage port B 0.5 +7 V

VCC(A) supply voltage port A adjustable 0.5 +7 V

VI/O voltage on an input/output pin port A and port B; enable pin (EN) 0.5 +7 V

II/O input/outpu t current port A; port B - 50 mA

IIinput curr en t EN, VCC(A), VCC(B), GND - 50 mA

Ptot total power dissipation - 100 mW

Tstg storage temperature 55 +125 C

Tamb ambient temperature operating in free air 40 +85 C

Tjjunction temperature - +125 C

Product data sheet Rev. 1 — 20 March 2013 10 of 23

NXP Semiconductors PCA9617A

Level translating Fm+ I2C-bus repeater

9. Static characteristics

Table 5. Static characteristics

VCC(A) = 0.8 V to 5.5 V[1]; VCC(B) = 2.2 V to 5.5 V; GND = 0 V; Tamb =





Cto+85



C; unless otherwise specified.

Typical values measured with VCC(A) = 0.95 V and VCC(B) = 2.5 V at 25



C, unless otherwise noted.

Symbol Parameter Conditions Min Typ Max Unit

Supplies

VCC(B) supply voltage port B 2.2 - 5.5 V

VCC(A) supply voltage port A [2] 0.8 - 5.5 V

ICC(A) supply current port A VCC(A) =0.95V - - 8 A

VCC(A) =5.5V - - 50 A

ICCH(B) port B HIGH-level

supply current VCC(B) =5.5V;

SDAn = SCLn = VCC(n)

-1.52.5 mA

ICCL(B) port B LOW-level

supply current VCC(B) = 5.5 V ; one SDA and

one SCL = GND; other SDA and

SCL open (with pull-up resistors)

-1.72.9 mA

Input and output SDAB and SCLB

VIH HIGH-level input voltage 0.7VCC(B) -5.5 V

VIL LOW-level input voltage 0.5 - +0.4 V

VIK input clamping voltage II=18 mA 1.2 - 0.3 V

ILI input leakage current VI=5.5V - - 1A

IIL LOW-level input current SDA, SCL; VI=0.2V - - 10 A

VOL LOW-level output voltage IOL =150A at VCC(B) =2.2V [3] 0.47 - - V

IOL =13mA atV

CC(B) =2.2V [4] -0.540.60V

VOLVIL difference between

LOW-level output and

LOW-level input voltage

VOL at IOL =1mA;

guaranteed by design 60 90 160 mV

Cio input/output capacitance VI= 3 V or 0 V; VCC(B) =3.3V;

EN = LOW - 7 10 pF

VI= 3 V or 0 V; VCC =0V - 7 10 pF

Input and output SDAA and SCLA

VIH HIGH-level input voltage 0.7VCC(A) -5.5 V

VIL LOW-level input voltage [5] 0.5 - +0.25VCC(A)[6] V

VIK input clamping voltage II=18 mA 1.2 - 0.3 V

ILI input leakage current VI=5.5V - - 1A

IIL LOW-level input current SDA, SCL; VI=0.2V - - 10 A

VOL LOW-level output voltage IOL =13mA; V

CC(B) =2.2V - 0.1 0.2 V

Cio input/output capacitance VI= 3 V or 0 V; VCC =3.3V;

EN = LOW - 7 10 pF

VI= 3 V or 0 V; VCC =0V - 7 10 pF

Enable

VIL LOW-level input voltage 0.5 - +0.3VCC(B) V

VIH HIGH-level input voltage 0.7VCC(B) -5.5 V

IIL(EN) LOW-level input current on

pin EN VI= 0.2 V, EN; VCC(B) =2.2V 18 74A

Product data sheet Rev. 1 — 20 March 2013 11 of 23

NXP Semiconductors PCA9617A

Level translating Fm+ I2C-bus repeater

[1] VCC(A) may be as high as 5.5 V for overvoltage tolerance but 0.4VCC(A) +0.8VVCC(B) for the channels to be enabled and functional

normally.

[2] For part to function, 0.4 VCC(A) must be equal or less than VCC(B) 0.8 V. The voltage on the A port can still be up to 5.5 V without

damage to the pins.

[3] Pull-up should result in IOL 150 A.

[4] Guaranteed by design and characterization.

[5] VIL for port A with envelope noise must be below 0.3VCC(A) for stable performance.

[6] When VCC(A) is less than 1 V, care is required to make certain that the system ground offset and noise are minimized such that there is

reasonable difference between the VIL present at the PCA9617A A-side input and the 0.25VCC(A) input threshold.

[7] Power supply decoupling capacitors need to be present for both VCC(A) and VCC(B) and the 0.1 F decoupling for VCC(B) needs to be

located near the VCC(B) pin.

ILI input leakage current 1-+1 A

Ciinput capacitance VI=V

CC(B) -67 pF

Table 5. Static characteristics …continued

VCC(A) = 0.8 V to 5.5 V[1]; VCC(B) = 2.2 V to 5.5 V; GND = 0 V; Tamb =





Cto+85



C; unless otherwise specified.

Typical values measured with VCC(A) = 0.95 V and VCC(B) = 2.5 V at 25



C, unless otherwise noted.

Symbol Parameter Conditions Min Typ Max Unit

Fig 10. Port B VOL versus IOL Fig 11. Port A VOL versus IOL

RC = 67.5 ns, VCC(A) = 0.95 V, VCC(B) = 2.5 V, and Tamb =25C.

Fig 12. Nominal port B tPHL with load capacitance at constant RC

port B I

(mA)

0302010

002aah461

0.70

port B V

(V)

0.50

0.60

0.65

0.55

CC(B)

= 2.2 V (Nom = 25 °C)

2.2 V (Hot = 85 °C)

3.0 V (Hot = 85 °C)

002aag896

Port A I

(mA)

0302010

0.3

0.2

0.1

0.4

Port A V

(V)

CC(B)

= 2.2 V (Nom = 25 °C)

2.2 V (Hot = 85 °C)

002aag897

at constant RC (pF)

50 200150100

100

110

Port B

PHL

(ns)

maximum

typical

minimum

Product data sheet Rev. 1 — 20 March 2013 12 of 23

NXP Semiconductors PCA9617A

Level translating Fm+ I2C-bus repeater

10. Dynamic characteristics

[1] 0.4VCC(A) +0.8VVCC(B) for the channels to be enabled and function normally.

[2] Times are specified with loads of 1.3 5 k pull-up resistance and 50 pF load capacitance on port A and port B, and a falling edge slew

rate of 0.05 V/ns input signals.

[3] Pull-up voltages are VCC(A) on port A and VCC(B) on port B.

[4] Typical values were measured with VCC(A) = 0.95 V, VCC(B) = 2.5 V at Tamb =25C, unless otherwise noted.

[5] The tPLH2 delay data from port B to port A is measured at 0.45 V on port B to 0.5VCC(A) on port A.

[6] The tTLH of the bus is determined by the pull-up resistance (1.35 k) and the total capacitance (50 pF).

[7] The proportional delay data from port A to port B is measured at 0.5VCC(A) on port A to 0.5VCC(B) on port B.

[8] The enable pin, EN, should only change state when the global bus and the repeater port are in an idle state.

Table 6. Dynamic characteristics

VCC(A) = 0.8 V to 5.5 V[1]; VCC(B) = 2.2 V to 5.5 V; GND = 0 V; Tamb =





Cto+85



C; unless otherwise specified.[2][3]

Symbol Parameter Conditions Min Typ[4] Max Unit

tPLH LOW to HIGH propagation delay port B to port A; Figure 15 -42 65 103 ns

tPLH2 LOW to HIGH propagation delay 2 port B to port A; Figure 15 [5] 67 94 130 ns

tPHL HIGH to LOW propagation delay port B to port A; Figure 13 46 76 152 ns

tTLH LOW to HIGH output transition time port A; Figure 13 [6] -60-ns

SRffalling slew rate port A; 0.7VCC(A) to 0.3VCC(A) 0.022 0.037 0.11 V/ns

tPLH LOW to HIGH propagation delay port A to port B; Figure 14 [7] 40 60 102 ns

tPHL HIGH to LOW propagation delay port A to port B; Figure 14 [7] 63 80 173 ns

tTLH LOW to HIGH output transition time port B; Figure 14 [6] -60-ns

SRffalling slew rate port B; 0.7VCC(B) to 0.3 VCC(B) 0.029 0.056 0.09 V/ns

ten enable time quiescent 0.3 V;

EN HIGH to enable; Figure 16 [8] --100ns

tdis disable time quiescent + 0.3 V;

EN LOW to disable; Figure 16 [8] --100ns

Product data sheet Rev. 1 — 20 March 2013 13 of 23

NXP Semiconductors PCA9617A

Level translating Fm+ I2C-bus repeater

10.1 AC waveforms

11. Test information

Fig 13. Propagation delay a nd transition times;

port B to port A Fig 14. Propagation de lay and transi tio n tim e s;

port A to port B

Fig 15. Propagation delay Fig 16. En ab le and disable times

002aag649

VCC(B)

VCC(A)

tPLH

tTHL

0.5VCC(B) 0.5VCC(B)

input

output 30 %

0.5VCC(A) 0.5VCC(A) 70 %

30 %

70 %

tPHL

tTLH

VOL

002aag650

VCC(A)

VCC(B)

tPLH

tTHL

0.5VCC(A) 0.5VCC(A)

input

output 30 %

0.5VCC(B) 0.5VCC(B) 70 %

30 %

70 %

tPHL

tTLH

PLH

0.45 V

input

SDAB, SCLB

output

SCLA, SDAA

PLH2

50 % of V

CC(A)

002aag651

50 % of V

CC(B)

002aag894

CC(B)

0.5V

CC(B)

0.5V

CC(B)

input

EN to output

+0.3 V

−0.3 V

dis

output

RL= load resistor; 1.35 k on port A and port B.

CL= load capacitance includes jig and probe capacitance; 50 pF

RT= termination resistance should be equal to Zo of pulse generators

Fig 17. Test circuit for open -drain outputs

PULSE

GENERATOR

002aab649

VCC(B)

DUT

VCC(A)

Product data sheet Rev. 1 — 20 March 2013 14 of 23

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12. Package outline

Fig 18. Package outline SOT505-1 (TSSOP8)

UNIT A1

max. A2A3bpLHELpwyv

ceD(1) E(2) Z(1) θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.45

0.25 0.28

0.15 3.1

2.9 3.1

2.9 0.65 5.1

4.7 0.70

0.35 6°

0°

0.1 0.10.10.94

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.7

0.4

SOT505-1 99-04-09

03-02-18

0.25

A2A1

(A3)

detail X

vMA

2.5 5 mm0

scale

TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1

1.1

pin 1 index

Product data sheet Rev. 1 — 20 March 2013 15 of 23

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Fig 19. Package outline SOT1069-2 (HWSON8)

References

Outline

version

European

projection Issue date

IEC JEDEC JEITA

SOT1069-2 - - -

MO-229

- - -

sot1069-2_po

09-11-18

12-04-18

Unit

max

nom

min

0.80

0.75

0.70

0.05

0.02

0.00

2.1

2.0

1.9

1.6

1.5

1.4

3.1

3.0

2.9

0.5 1.5

0.45

0.40

0.35

0.05

A(1)

Dimensions

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

HWSON8: plastic thermal enhanced very very thin small outline package; no leads;

8 terminals; body 2 x 3 x 0.75 mm SOT1069-2

0.65

0.55

0.45

0.2

A3b

0.30

0.25

0.18

D(1) D2E(1) E2

1.6

1.5

1.4

0.40

0.35

0.30

0.1

0.05

0 1 2 mm

scale

terminal 1

index area

B A

detail X

terminal 1

index area b

eAC B

1 4

Product data sheet Rev. 1 — 20 March 2013 16 of 23

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13. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

13.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

13.2 Wave and reflow soldering

W ave soldering is a joinin g technology in which the joint s are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circu it board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

•Board specifications, including the board finish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering versus SnPb soldering

13.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath specifications, including temperature and impurities

Product data sheet Rev. 1 — 20 March 2013 17 of 23

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13.4 Reflow soldering

Key characteristics in reflow soldering are:

•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to

higher minimum peak temperatures (see Figure 20) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enoug h for the solder to make reliable solder joint s (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 7 and 8

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 20.

Table 7. SnPb eutectic process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350  350

< 2.5 235 220

 2.5 220 220

Table 8. Lead-free process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 1 — 20 March 2013 18 of 23

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For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

14. Soldering: PCB footprints

MSL: Moisture Sensitivity Level

Fig 20. Temperature profiles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Fig 21. PCB footprint for SOT505-1 (TSSOP8); reflow soldering

sot505-1_fr

occupied areasolder lands Dimensions in mm

3.200

3.600

5.750

0.725

0.650

0.125

0.4500.600

3.600

2.950

0.125

1.150

5.500

Product data sheet Rev. 1 — 20 March 2013 19 of 23

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Fig 22. PCB footprint for SOT1069-2 (HWSON8); reflow soldering

SOT1069-2

DIMENSIONS in mm

Footprint information for reflow soldering of HWSON8 package

Ay By D SLx SLy SPx SPy Gx Gy

3.45 2.2

0.5 0.25

0.625 1.6 1.6 0.6 0.6 2.25 3.25

3.7

nSPx nSPy

occupied area

solder land plus solder paste

solder land

solder paste deposit

sot1069-2_fr

Issue date 12-02-09

12-02-22

SLx

BySLy

SPx

SPy

nSPx

nSPy

Product data sheet Rev. 1 — 20 March 2013 20 of 23

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15. Abbreviations

16. Revision history

Table 9. Abbreviations

Acronym Description

CDM Charged-Device Model

CMOS Complementary Metal-Oxide Semiconductor

ESD ElectroS tatic Discharge

HBM Human Body Model

I2C-bus Inter-Integrated Circuit bu s

I/O Input/Output

PMBus Power Management Bus

RC Resistor-Capacitor network

SMBus System Management Bus

Table 10. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PCA9617A v.1 20130320 Product data sheet - -

Product data sheet Rev. 1 — 20 March 2013 21 of 23

NXP Semiconductors PCA9617A

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17. Legal information

17.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

17.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conf lict with the short data sheet, the

full data sheet shall pre vail.

Product specificat io n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

17.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Se miconductors takes no

responsibility for the content in this document if provided by an inf ormation

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental ,

punitive, special or consequ ential damages (including - wit hout limitatio n - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregat e and cumulative liabil ity towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors pro duct can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconducto rs products in such equipment or

applications and ther efore such inclu sion and/or use is at the cu stomer’s own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liabili ty related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessa ry

testing for th e customer’s applications and pro ducts using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by cust omer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or t he grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product develop ment.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] dat a sheet Production This document contains the product specification.

Product data sheet Rev. 1 — 20 March 2013 22 of 23

NXP Semiconductors PCA9617A

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Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for aut omo tive use. It i s neit her qua lif ied nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standard s, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y

liability, damages or failed product cl aims resulting from custome r design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specif ications.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

17.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

I2C-bus — logo is a trademark of NXP B.V.

18. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors PCA9617A

Level translating Fm+ I2C-bus repeater

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 20 March 2013

Document identifier: PCA9617A

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

19. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

3.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

6 Functional description . . . . . . . . . . . . . . . . . . . 5

6.1 Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

6.2 I2C-bus systems . . . . . . . . . . . . . . . . . . . . . . . . 5

7 Application design-in information . . . . . . . . . . 6

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 9

9 Static characteristics. . . . . . . . . . . . . . . . . . . . 10

10 Dynamic characteristics . . . . . . . . . . . . . . . . . 12

10.1 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . 13

11 Test information. . . . . . . . . . . . . . . . . . . . . . . . 13

12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14

13 Soldering of SMD packages . . . . . . . . . . . . . . 16

13.1 Introduction to soldering . . . . . . . . . . . . . . . . . 16

13.2 Wave and reflow soldering . . . . . . . . . . . . . . . 16

13.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 16

13.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 17

14 Soldering: PCB footprints. . . . . . . . . . . . . . . . 18

15 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 20

16 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 20

17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 21

17.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21

17.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

17.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 21

17.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22

18 Contact information. . . . . . . . . . . . . . . . . . . . . 22

19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23