DABiC-IV, 10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
A6810xA
Data Sheet
26182.124B
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Logic Supply Voltage, VDD ................... 7.0 V
Driver Supply Voltage, VBB ................... 60 V
Continuous Output Current Range,
IOUT ......................... -40 mA to +15 mA
Input Voltage Range,
VIN ....................... -0.3 V to VDD + 0.3 V
Package Power Dissipation,
PD........................................ See Graph
Operating Temperature Range, TA
(Suffix ‘E–’) .................. -40°C to +85°C
(Suffix ‘S–’) .................. -20°C to +85°C
Storage Temperature Range,
TS............................... -55°C to +125°C
Caution: These CMOS devices have input
static protection (Class 2) but are still
susceptible to damage if exposed to
extremely high static electrical charges.
The A6809– and A6810– devices combine 10-bit CMOS shift
registers, accompanying data latches and control circuitry with bipolar
sourcing outputs and pnp active pull downs. Designed primarily to
drive vacuum-fluorescent displays, the 60 V and -40 mA output ratings
also allow these devices to be used in many other peripheral power
driver applications. The A6809– and A6810– feature an increased data
input rate (compared with the older UCN/UCQ5810-F) and a con-
trolled output slew rate. The A6809xLW and A6810xLW are identical
except for pinout.
The CMOS shift register and latches allow direct interfacing with
microprocessor-based systems. With a 3.3 V or 5 V logic supply,
typical serial-data input rates are up to 33 MHz.
A CMOS serial data output permits cascade connections in applica-
tions requiring additional drive lines. Similar devices are avail-able as
the A6811– (12 bits), A6812– (20 bits), and A6818– (32 bits).
The A6809– and A6810– output source drivers are npn Darling-
tons, capable of sourcing up to 40 mA. The controlled output slew rate
reduces electromagnetic noise, which is an important consideration in
systems that include telecommunications and/or microprocessors and
to meet government emissions regulations. For inter-digit blanking, all
output drivers can be disabled and all sink drivers turned on with a
BLANKING input high. The pnp active pull-downs will sink at least
2.5 mA.
All devices are available in two temperature ranges for optimum
performance in commercial (suffix S-) or industrial (suffix E-) applica-
tions. The A6810– is provided in three package styles for through-hole
DIP (suffix -A), surface-mount SOIC (suffix -LW), or minimum-area
surface-mount PLCC (suffix -EP). The A6809– is provided in the
SOIC (suffix -LW) only. Copper lead frames, low logic-power dissi-
pation, and low output-saturation voltages allow all devices to source
25 mA from all outputs continuously over the maximum operating
temperature range.
FEATURES
■Controlled Output Slew Rate
■High-Speed Data Storage
■60 V Minimum
Output Breakdown
■High Data Input Rate
■PNP Active Pull-Downs
Complete part number includes a suffix to identify operating
temperature range (E- or S-) and package type (-A, -EP, or -LW).
Always order by complete part number, e.g., A6810SLW .
6809
AND
6810
■Low Output-Saturation Voltages
■Low-Power CMOS Logic
and Latches
■Improved Replacements
for TL4810–, UCN5810–,
and UCQ5810–
2
3
4
5
6
7
8
910
11
12
13
14
15
16
17
18
SERIAL
DATA OUT
LOAD
SUPPLY
SERIAL
DATA IN
BLANKING
LOGIC
SUPPLY
STROBE
GROUND
CLOCK CLK
V
ST
BLNK
DD
BB
V
OUT
9
OUT
10
OUT
1
OUT
2
OUT
3
Dwg. PP-029
OUT
8
OUT
7
OUT
6
OUT
5
OUT
4
1
LATCHES
REGISTER
REGISTER
LATCHES
6809
AND
6810
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1998, 2000 Allegro MicroSystems, Inc.
A6810xEP
TYPICAL OUTPUT DRIVER TYPICAL INPUT CIRCUIT
A6809xLW
SERIAL
DATA OUT
LOAD SUPPLY
SERIAL
DATA IN
BLANKING
BLNK
V
OUT
1
OUT
2
OUT
3
REGISTER
LATCHES
LOGIC SUPPLY
STROBE
V
ST
DD
OUT
5
OUT
4
1
2
3
8
9
13
14
15
16
17
19
4
5
6
7
12
18
20
GROUND
CLOCK CLK
BB
OUT
9
OUT
10
Dwg. PP-029-9
OUT
8
OUT
7
OUT
6
LATCHES
REGISTER
10 11
NO
CONNECTION NC
NO
CONNECTION
NC
A6810xLW
13
14
15
16
17
19
12
18
20
SERIAL
DATA OUT
LOAD SUPPLY
SERIAL
DATA IN
BLANKING
OUT9
OUT10
OUT1
OUT2
OUT3
11 NO
CONNECTION
1
2
3
8
9
4
5
6
7
LOGIC SUPPLY
STROBE
GROUND
CLOCK
OUT 8
OUT7
OUT 6
OUT 5
OUT 4
10
NO
CONNECTION
CLK
V
ST
BLNK
DD
BB
V
Dwg. PP-029-2
LATCHES
REGISTER
REGISTER
LATCHES
NC
NC
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13 19
20
STROBE
V
DD
Dwg. PP-059
OUT
1
OUT
10
OUT
5
OUT
6
LATCHES
REGISTER
REGISTER
LATCHES
V
BB
CLOCK
NC
GROUND
LOGIC
SUPPLY
SERIAL
DATA OUT
LOAD
SUPPLY
NC
SERIAL
DATA IN
BLANKING
ST
CLK
BLNK
50 75 100 125 150
2.5
0.5
0
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
AMBIENT TEMPERATURE IN °C
2.0
1.5
1.0
25
SUFFIX 'A', R = 60°C/W
θJA
SUFFIX 'EP', R = 59°C/W
θJA
Dwg. GP-024-1
SUFFIX 'LW', R = 70°C/W
θJA
Dwg. EP-010-5
IN
VDD
VBB
Dwg. EP-021-19
OUT
N
6809
AND
6810
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
www.allegromicro.com
FUNCTIONAL BLOCK DIAGRAM
TRUTH TABLE
Serial Shift Register Contents Serial Latch Contents Output Contents
Data Clock Data Strobe
Input Input I1I2I3... IN-1 INOutput Input I1I2I3... IN-1 INBlanklng I1I2I3... IN-1 IN
HHR
1R2... RN-2 RN-1 RN-1
LLR
1R2... RN-2 RN-1 RN-1
XR
1R2R3... RN-1 RNRN
XXX...X X X L R
1R2R3... RN-1 RN
P1P2P3... PN-1 PNPNHP
1P2P3... PN-1 PNLP
1P2P3... PN-1 PN
X X X ... X X H L L L ... L L
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
MOS
BIPOLAR
OUT
1
OUT
2
GROUND Dwg. FP-013-1
OUT
3
OUT
N
CLOCK
SERIAL
DATA IN
STROBE
BLANKING
SERIAL
DATA OUT
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
V
DD
V
BB
LOGIC
SUPPLY
LOAD
SUPPLY
6809
AND
6810
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Limits @ VDD = 3.3 V Limits @ VDD = 5 V
Characteristic Symbol Test Conditions Mln. Typ. Max. Min. Typ. Max. Units
Output Leakage Current ICEX VOUT = 0 V —<-0.1 -15 —<-0.1 -15 µA
Output Voltage VOUT(1) IOUT = -25 mA 57.5 58.3 —57.5 58.3 —V
VOUT(0) IOUT = 1 mA —1.0 1.5 —1.0 1.5 V
Output Pull-Down Current IOUT(0) VOUT = 5 V to VBB 2.5 5.0 —2.5 5.0 —mA
Input Voltage VIN(1) 2.2 ——3.3 —— V
VIN(0) ——1.1 ——1.7 V
Input Current IIN(1) VIN = VDD —<0.01 1.0 —<0.01 1.0 µA
IIN(0) VIN = 0 V —<-0.01 -1.0 —<-0.01 -1.0 µA
Input Clamp Voltage VIK IIN = -200 µA—-0.8 -1.5 —-0.8 -1.5 V
Serial Data Output Voltage VOUT(1) IOUT = -200 µA 2.8 3.05 —4.5 4.75 —V
VOUT(0) IOUT = 200 µA—0.15 0.3 —0.15 0.3 V
Maximum Clock Frequency fc10 33 —10 33 —MHz
Logic Supply Current IDD(1) All Outputs High —0.25 0.75 —0.3 1.0 mA
IDD(0) All Outputs Low —0.25 0.75 —0.3 1.0 mA
Load Supply Current IBB(1) All Outputs High, No Load —1.5 3.0 —1.5 3.0 mA
IBB(0) All Outputs Low —0.2 20 —0.2 20 µA
Blanking
-to-
Output Delay tdis(BQ) CL = 30 pF, 50% to 50% —0.7 2.0 —0.7 2.0 µs
ten(BQ) CL = 30 pF, 50% to 50% —1.8 3.0 —1.8 3.0 µs
Strobe
-to-
Output Delay tp(STH-QL) RL = 2.3 kΩ, CL ≤ 30 pF —0.7 2.0 —0.7 2.0 µs
tp(STH-QH) RL = 2.3 kΩ, CL ≤ 30 pF —1.8 3.0 —1.8 3.0 µs
Output Fall Time tfRL = 2.3 kΩ, CL ≤ 30 pF 2.4 —12 2.4 —12 µs
Output Rise Time trRL = 2.3 kΩ, CL ≤ 30 pF 2.4 —12 2.4 —12 µs
Output Slew Rate dV/dt RL = 2.3 kΩ, CL ≤ 30 pF 4.0 —20 4.0 —20 V/µs
Clock
-to-
Serial Data Out Delay tp(CH-SQX) IOUT = ±200 µA—50 ——50 —ns
Negative current is defined as coming out of (sourcing) the specified device terminal.
Typical data is is for design information only and is at TA = +25°C.
ELECTRICAL CHARACTERISTICS at TA = +25°C (A6809SLW & A6810S-) or over operating
temperature range (A6809ELW & A6810E-), VBB = 60 V unless otherwise noted.
6809
AND
6810
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
www.allegromicro.com
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
Serial Data present at the input is transferred to the shift
register on the logic “0” to logic “1” transition of the CLOCK
input pulse. On succeeding CLOCK pulses, the registers shift
data information towards the SERIAL DATA OUTPUT. The
SERIAL DATA must appear at the input prior to the rising edge
of the CLOCK input waveform.
Information present at any register is transferred to the
respective latch when the STROBE is high (serial-to-parallel
conversion). The latches will continue to accept new data as
long as the STROBE is held high. Applications where the
latches are bypassed (STROBE tied high) will require that the
BLANKING input be high during serial data entry.
When the BLANKING input is high, the output source
drivers are disabled (OFF); the pnp active pull-down sink
drivers are ON. The information stored in the latches is not
affected by the BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of their respective
latches.
CLOCK
SERIAL
DATA IN
STROBE
BLANKING
OUT
N
Dwg. WP-029
50%
SERIAL
DATA OUT
DATA
DATA
10%
90%
50%
50%
50%
C
A B
D E
LOW = ALL OUTPUTS ENABLED
p(STH-QL)
t
p(CH-SQX)
t
DATA
p(STH-QH)
t
BLANKING
OUTN
Dwg. WP-030
DATA
10%
50%
en(BQ)
t
dis(BQ)
t
HIGH = ALL OUTPUTS BLANKED (DISABLED)
90%
r
tf
t
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), tsu(D) ......................................... 25 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), th(D) ............................................... 25 ns
C. Clock Pulse Width, tw(CH) ............................................... 50 ns
D. Time Between Clock Activation and Strobe, tsu(C) ....... 100 ns
E. Strobe Pulse Width, tw(STH) ............................................. 50 ns
NOTE – Timing is representative of a 10 MHz clock. Signifi-
cantly higher speeds are attainable.
6809
AND
6810
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
A6810EA & A6810SA
Dimensions in Inches
(controlling dimensions)
Dimensions in Millimeters
(for reference only)
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Lead thickness is measured at seating plane or below.
0.014
0.008
0.300
BSC
Dwg. MA-001-18A in
0.430
MAX
18
19
0.280
0.240
0.210
MAX
0.070
0.045
0.015
MIN
0.022
0.014
0.100
BSC
0.005
MIN
0.150
0.115
10
0.920
0.880
0.355
0.204
7.62
BSC
Dwg. MA-001-18A mm
10.92
MAX
18
19
7.11
6.10
5.33
MAX
1.77
1.15
0.39
MIN
0.558
0.356
2.54
BSC 0.13
MIN
3.81
2.93
10
23.37
22.35
6809
AND
6810
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
www.allegromicro.com
A6810EEP & A6810SEP
Dimensions in Inches
(controlling dimensions)
Dimensions in Millimeters
(for reference only)
NOTES: 1. Exact body and lead configuration at vendor’s
option within limits shown.
2. Lead spacing tolerance is non-cumulative.
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsi-
bility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
913
0.020
MIN
0.180
0.165
0.050
BSC
120 2
Dwg. MA-005-20A in
0.395
0.385
0.356
0.350
0.032
0.026
0.021
0.013
3
4
8
14
18
19
0.356
0.350
0.395
0.385
INDEX AREA
0.169
0.141
0.169
0.141
913
0.51
MIN
4.57
4.20
1.27
BSC
120 2
Dwg. MA-005-20A mm
10.03
9.78
9.042
8.890
0.812
0.661
0.533
0.331
3
4
8
14
18
19
9.042
8.890
10.03
9.78
INDEX AREA
4.29
3.58
4.29
3.58
6809
AND
6810
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
A6809ELW, A6809SLW, A6810ELW, & A6810SLW
Dimensions in Inches
(for reference only)
Dimensions in Millimeters
(controlling dimensions)
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
0°
TO
8°
1 2 3
0.020
0.013
0.0040
MIN.
0.0125
0.0091
0.050
0.016
Dwg. MA-008-20 in
0.050
BSC
20 11
0.2992
0.2914
0.419
0.394
0.5118
0.4961
0.0926
0.1043
0°
TO
8°
1
20
23
0.51
0.33
0.10
MIN.
Dwg. MA-008-20 mm
1.27
BSC
11 0.32
0.23
1.27
0.40
7.60
7.40
10.65
10.00
13.00
12.60
2.65
2.35
